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In this article, we explore different device and standard cell architectures for scaling the Germanium fin field-effect transistor (FinFET) and nanosheet (NS) at the sub-5-nm node. It is demonstrated that the Germanium device provides approximately 70% improvement in drive current and $3.4\times $ less device resistance. The main concern for Germanium devices remains the high leakage current due to the gate-induced drain leakage, which limits their usage to high-speed applications. Overall, Germanium devices require fewer boosters than silicon to scale beyond the 5-nm node. Contact resistivity is found to be a critical knob for Germanium and it can be relaxed to 3e $- 9\,\,\Omega $ -cm2 to meet the power and performance targets for the sub-5-nm node. Moving to the NS helps in relaxing this constraint further.

For sub-5 nm bulk Si CMOS, a gate-all-around (GAA) nanowire (NW) device is a promising candidate. The new device architecture will have an impact on the transient performance of an electrostatic discharge protection diode. The 100 ns transmission line pulse (TLP) and 2 ns very fast TLP measurement results and TCAD simulations prove that the performance in bulk GAA NW-based diodes is maintained in comparison to bulk FinFET diodes.

The NEREID project (“NanoElectronics Roadmap for Europe: Identification and Dissemination”) is dedicated to mapping the future of European Nanoelectronics. NEREID’s objective is to develop a medium and long term roadmap for the European nanoelectronics industry, starting from the needs of applications to address societal challenges and leveraging the strengths of the European eco-system. The roadmap will also identify promising novel nanoelectronic technologies, based on the advanced concepts developed by Research Centres and Universities, as well as identification of potential bottlenecks along the innovation (value) chain. Industry applications include Energy, Automotive, Medical/Life Science, Security, loT, Mobile Convergence and Digital Manufacturing. The NEREID roadmap covers Advanced Logic and Connectivity, Functional Diversification (Smart Sensors, Smart Energy and Energy for Autonomous Systems), Beyond-CMOS, Heterogeneous Integration and System Design as well as Equipment, Materials and Manufacturing Science. This article gives an overview of the roadmap’s structure and content., Thanks are extended to the support of the EU, which has been funded the NEREID project as a Cooperation and Support action for three years from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 685559.

The performance of n-type silicon nanosheets, nanowires, and FinFETs is benchmarked by Monte Carlo (MC) device simulation. Measurements of nanowire transfer characteristics are provided to validate the MC model supplemented by a corresponding comparison for nanosheets with literature data. At an OFF-current per effective gate width of 10 nA/ $\mu \text{m}$ , the ON-currents of nanowires, FinFETs, and nanosheets are 500, 545, and 570 $\mu \text{A}/\mu \text{m}$ , respectively. A major reason for this inferior nanowire performance is found to be the stronger impact of surface roughness scattering in nanowires due to a higher surface-to-volume ratio. However, the nanowires’ performance disadvantage is reduced for shorter gate lengths due to their better electrostatic control and reduced impact of surface roughness upon scaling.

2-D material FETs hold the promise of excellent gate control, but the impact of nonidealities on their performance remains poorly understood. This is because of the need, so far, to use computationally intensive nonequilibrium Green’s function (NEGF) simulations. Here, we therefore use a semiclassical model to investigate the role of nonidealities in the scaling of back-gated (BG) and top-gated (TG) monolayer MoS2 FETs. We verify the electrostatics and transport of the semiclassical model with density functional theory-based NEGF simulations and calibrate nonidealities, such as interface traps ( ${D}_{\textsf {it}}$ ) and Schottky contact barrier height ( $\phi _{\textsf {SB}}$ ) to experimental monolayer and bilayer MoS2 FETs. We find that among the nonidealities, ${D}_{\textsf {it}}$ has the strongest subthreshold swing impact with 70 mV/dec obtainable in BG devices for a ${D}_{\textsf {it}}$ of $5\times {10}^{11}$ cm−2eV $^{-1}$ , an equivalent oxide thickness (EOT) of 1 nm, and a channel length ( ${L}_{\textsf {ch}}$ ) of 5 nm. For scaled EOT, $\phi _{\textsf {SB}}$ only strongly impacts ${I}_{ \mathrm{\scriptscriptstyle ON}}$ for the TG case, as the overlapping gate thins the Schottky barriers in the BG case. We show in TG devices that a spacer of only 5 nm results in a 1000-fold drop in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ because of the nonidealities. We propose positive spacer oxide charge as a solution and show that a charge density of above 1013 cm−2 is required to fully recover the device performance.

Dopant pockets in combination with a III–V heterostructure have become a staple in simulations of tunnel field-effect transistors (TFET) to achieve acceptable on-currents ( ${I} _{\mathrm{ ON}}$ ) and to break the ${I} _{\mathrm{ ON}}$ -subthreshold swing trade-off in pTFETs. Questions on the scalability and variability of these dopant pockets remain, however. We therefore propose an alternative concept using two opposite sheet charges at the tunnel junction that are realized by exploiting different bonding types. With fully quantum mechanical 30-band k.p-based simulations, we investigate two configurations that exhibit such sheet charges both at the device level and in a ring-oscillator: a lattice-matched GaAs-Ge-GaAs heterostructure TFET and a homostructure InGaAs TFET. By comparing to pocketed broken gap GaSb-InAs TFETs, we show that built-in sheet charge is a valid alternative for both nTFET and pTFET, with the prospect of lower variability and better scalability.

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling.

This letter proposes a metric to assess the quality of high-k dielectrics on III–V substrates and a benchmarking methodology for the gate stack qualification in the region of MOS device operation above threshold voltage, ${V}_{t}$ . The metric is based on a capacitive equivalent thickness (CET) - normalized frequency dispersion ( $\text{D}_{\mathrm {eff}}$ ) evaluated in the accumulation region of capacitance–voltage (C–V) measurements of III–V MOS devices. ${D} _{\mathrm {eff}}$ is found to be CET independent, which allows for a preliminary assessment of the dielectric quality by using relatively thick layers. Several gate stacks, single layer or bi-layer, including those with Al2O3, and the recently reported ASM-imec interfacial layer (IL) with HfO2 are evaluated and compared against Si MOS devices. Using the proposed technique, a clear difference between the various deposition processes is observed. The results indicate that the quality of a single layer Al2O3 or a bi-layer stack of Al2O3/HfO2 on InGaAs is significantly lower compared with Si gate stacks while the ASM-imec IL yields a gate-stack with good performance on the proposed quality metric. In addition, these results correlate well with the reliability performance of the studied gate stacks.

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSi x ) and achieve ultralow contact resistivity ( $\rho _{c}$ ) of (1.3 – 1.5) $\times 10^{-9} ~\Omega \cdot \text {cm}^{2}$ on Si:P. This PCAI + TiSi x technique utilizes light amorphization (low-energy implantation), thin Ti and TiSi x film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSi x -induced $\rho _{c}$ reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced $\rho _{c}$ variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low $\rho _{c}$ is strongly correlated with the formation of interfacial TiSi x crystallites between amorphous TiSi alloy and Si.

We have measured the low-frequency 1/ ${f}$ noise of Si0.55Ge0.45 ${p}$ MOSFETs with a Si capping layer and SiO2/HfO2/TiN gate stack as a function of frequency, gate voltage, and temperature (100–440 K). The magnitude of the excess drain voltage noise power spectral density ( $\textit{S}_{ {vd}}$ ) is unaffected by negative-bias-temperature stress (NBTS) for temperatures below ~250 K, but increases significantly at higher temperatures. The noise is described well by the Dutta-Horn model before and after NBTS. The noise at higher measuring temperatures is attributed primarily to oxygen-vacancy and hydrogen-related defects in the SiO2 and HfO2 layers. At lower measuring temperatures, the noise also appears to be affected strongly by hydrogen-dopant interactions in the SiGe layer of the device.

In this paper, we have developed a straightforward MOS admittance-based technique for defect density extraction, utilizing analytical equations for MOS capacitors with border traps (BTs). We show that these equations can provide an efficient technique to obtain the BT density directly from the measured data without any requirement of numerically involved techniques. This is demonstrated by applying the methodology on measured C–V data from Al2O3- and HfO2-based MOSCAPs. The extracted densities show less than 5% difference from the values extracted using the fitting-based methodology used in previous reports. We show that, due to the analytical nature of these equations, they can be used to understand the impact of each defect parameter on the admittance. We extensively prove the applicability of the analytical solution for a very wide range of parameter values. In addition, we lay out a methodology for defect density extraction, which can be easily automated for the characterization of large scale data sets of high-k dielectrics on III–V MOS devices.

We present for the first time a co-integrated FinFET with vertical nanosheet transistor (VFET) process on a 300 mm silicon wafer for STT-MRAM applications and its related avenues with a holistic design-technology-co-optimization (DTCO) and power-performance-area-cost (PPAC) approach. The STT-MRAM bitcell and a 2 Mbit macro have been optimized and designed to address the viability of the co-integration process and advantages of vertical channel transistors for STT-MRAM selectors. An architectural system simulator GEM5 has been also employed with Polybench workloads to assess energy saving at system-level. In order to enable this co-integration, four extra masks are required, which costs below 10% in embedded chips. A 36% area reduction can be achieved for the STT-MRAM bitcell implemented with VFET selectors. With a UVLT flavor, the STT-MRAM bitcell comprising of 3-nanosheet could deliver the same performance of the 4-fin LVT FinFET selector. A 2 Mbit STT-MRAM macro designed with VFET selector can offer a 17% and a 21% reduction for read access latency and energy per operation respectively, and a 10% for write energy per operation. A 7% energy saving for the STT-MRAM L2 cache using VFET selector has been observed at the system level with Polybench workloads.

The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to $5\text{e}-10\Omega.\text{cm}^{2}$ or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 & N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.

Moore's law, the principle that has powered semiconductor scaling for the past 50 years is nearing its end. However, the industry would like to pursue a dimensional scaling roadmap to reap the full benefit of technology innovation. Results shown on this paper demonstrate traditional dimensional scaling approaches involving multi-patterned lithography would skyrocket the manufacturing cost. Design level techniques collectively known as scaling boosters, and innovative Complementary FET (CFET) devices would help to reduce the cost of the technology nodes. To the best of our knowledge, this is the first approach where semiconductor node transitions are benchmarked based on their economic feasibility. To summarize, we have formulated a cost-driven approach that can guide the industry to continue semiconductor scaling.

We examine the power-performance variability of a projected sub-5-nm GaAsSb/InGaAs vertical tunnel FET considering various process control tolerances in the state-of-the-art device integration and propose countermeasures in device design. Nominal and three-sigma-corner device characteristics generated in quantum-mechanical/TCAD simulations are used to calibrate a semiempirical compact model, based on which the nominal and variability-inclusive energy-delay landscapes are extracted from ring-oscillator circuit simulations at sub-500-mV supply voltages. Variations in four parameters are identified as of major impact on the worst-case speed loss and iso-speed energy penalty: dopant pocket thickness, gate work function, hetero-band offset, and body thickness (in descending order). Variability-resilient device options are explored against pocket thickness variation, including: 1) pocket desensitization with increased thickness and reduced doping concentration and 2) broken-gap tunnel FET with a negative effective band gap. Reengineered devices achieve

The targeted N3 technology node at IMEC is being redefined with respect to the poly pitch, as compared to the previous node definitions [1,2]. The overall industry trend of poly pitch scaling is slowing down, due to difficulties in keeping pace with device performance and yield issues. However, the metal pitch continues to scale down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore’s law. Here we present some of the options for the standard cell design that can enable an N3 technology node by using Design-Technology cooptimization (DTCO).

Advanced technology nodes are based on nFET and pFET fins, which are fabricated on the same Silicon level of the wafer. However, in a complimentary FET (CFET) technology the nFET and pFET devices are stacked on top of each other [1]. This provides a significant area reduction mainly driven by a simplified transistor terminal access and the removal of the lateral physical separation between the two transistors. The combination of the CFET with buried power rails can reduce the track height of the cells and the elusive 3 Track standard cell is seen to be a possibility.

Standard cell track height scaling provides us with sufficient area scaling at the standard cell library level. The efficiency of this technique and the complexities involved with this scaling method have been discussed in detail [1,2]. However, the area benefits of standard cell track height scaling diminish when we consider the complexities of incorporating on-chip power grid into the DTCO exploration loop. We have previously outlined several layout techniques to improve the utilization density of this scaling technology [2,4]. However, the proposed techniques only minimize the impact of the power grid on the design. In this work, we discuss the need to combine 3D – μTSV technology and logic technology to decouple the power grid from the design budget. The proposed technique delivers power from the backside of a thinned device wafer using the process steps depicted in Figure 4. Our analysis demonstrates significant area savings and IR-drop reduction. We use SPICE simulations to extract grid resistances as part of our technology targeting process, based upon a high-level on-chip PDN model. We also verify our findings using a commercially available EDA toolchain.

Voltage transient overshoot is an essential device characteristic of ESD protection diodes under CDM-like stress. Using 3D TCAD and vfTLP characterization, the impact of device architecture and middle-of-line contact scheme on voltage transient overshoot characteristics can be further explored in next bulk FinFET and GAA technology nodes.

The increased complexity of CMOS transistor processing has led to limited scaling of high density SRAM cell at advanced technology nodes. STT-MRAM appears to be a promising candidate for replacing last level caches (LLC). This paper addresses design technology co-optimization (DTCO) of STT-MRAM technology and analyzes its viability as a LLC (compared to SRAM) for the high performance computing (HPC) domain (while maintaining a constraint of occupying merely 43.3% of SRAM macro area at identical capacities). This is the first study that breaks down a power, performance and area (PPA) comparison between SRAM and STT-MRAM based LLCs at the 5nm node. The STT-MRAM design and analysis is based on a silicon verified compact model and can be realized using 193i single patterning at the 5nm node. Our STT-MRAM design manages to achieve a nominal access latency

The effective bandgap for heterojunction band-to-band tunneling ( $ {{E}}_{{\text {g,eff}}}$ ) is a crucial design parameter for a heterojunction tunneling FET (TFET). However, there is significant uncertainty on $ {{E}}_{{\text {g,eff}}}$ , especially for In0.53Ga0.47As/ GaAs0.5Sb0.5. This makes the prediction of TFET performance difficult. We calibrate $ {{E}}_{{\text {g,eff}}}$ by fabricating heterojunction p+/i/n+ diodes, comparing the simulated and the measured current–voltage and capacitance–voltage curves, while taking $ {{E}}_{{\text {g,eff}}}$ as a fitting parameter. Our calibration significantly reduces the uncertainty on $ {{E}}_{{\text {g,eff}}}$ compared with the range found in the literature. The comparison with the previous work on highly doped heterojunction diodes suggests that dopant-dependent bandgap narrowing reduces $ {{E}}_{{\text {g,eff}}}$ and therefore significantly impacts the performance of highly doped TFET.

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1- $\mu \text{m}$ and 70-nm gate lengths. Hole mobility at 1- $\mu \text{m}$ gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.

The electrostatic and leakage effects of extended defects on Si and Ge MOSFETs are investigated. A technology computer-aided design model of extended defects is developed based upon measured device electrical properties. A single extended defect is introduced into simulated 2-D planar and 3-D FinFET structures. It is found that a 2-D extended defect is a source of variability in planar transistors, with the electrical effects depending on its position along the channel. A 2-D extended defect increases the threshold voltage and subthreshold swing when it is in the channel and increases the leakage current when it is in the drain. The dislocation effect on transistor characteristics increases with decreasing transistor width. The effect is less pronounced in FinFETs due to the well-controlled electrostatics and the small dislocation volume.

Strain can strongly impact the performance of III-V tunnel field-effect transistors (TFETs). However, previous studies on homostructure TFETs have found an increase in ON-current to be accompanied with a degradation of subthreshold swing. We perform 30-band quantum mechanical simulations of staggered heterostructure p-n-i-n TFETs submitted to uniaxial and biaxial uniform stress and find the origin of the subthreshold degradation to be a reduction of the density of states in the strained case. We apply an alternative configuration including a lowly doped pocket in the source, which allows to take full benefit of the strain-induced increase in ON-current.

In this work, we demonstrate a High-k Metal Gate (HKMG) Implant Free Quantum Well (IFQW) SiGe-pFET device used as a DRAM periphery device. Using a c:Si 0.55 Ge 0.45 channel and embedded e:Si 0.75 Ge 0.25 source/drain (S/D), a very significant source current of 625 μA/μm @ I OFF =100 pA/μm (at supply voltage V DD =−1 V) is demonstrated. The current improvement compared to DRAM compatible unstrained Silicon baseline technology (featuring HKMG) is large, and IFQW transistors are also competitive with regards to Strained Si devices. In particular, IFQW have a specific potential for Sense Amplifiers, with a demonstrated very good drive current/transconductance boost in the range of targeted gate lengths and excellent matching properties.

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow.

An in-depth study of scaled nanowire Ge pFETs for digital and analog applications is proposed. Improved device characteristics are first obtained after gaining a good understanding of the HPA on device performance. Up to 45% higher ID,SAT is obtained at I OFF =3nA/fin when comparing to best Si GAA nFET and similar ID,SAT is found when benchmarking to mature 14/16nm pFinFET technology at −0.5 V DD . The temperature dependent study of I D,SAT highlights that the mechanism limiting the transport in Ge at short channel are neither purely diffusive nor fully ballistic.

A new platform for Memory periphery device based on FinFET technology is proposed, targeting DRAM technology node 1Y and beyond. Up to 30% power saving is demonstrated at system level with respect to a conventional planar SiON based solution, thanks to an optimized cost-effective process flow (~38% less expensive than equivalent logic flow), compatible with a DRAM technology. This makes the solution perfectly suitable for low power mobile applications or enabling faster server applications. The additional sensing margin can be used to aggressively reduce the analog area (>50%) or to mitigate the process concern on the memory array, paving the way for the introduction of different storage elements. An overview of the device characteristics based on the fabricated hardware is presented, exploring potential knobs to further improve the transistors.

This work presents Si/SiGe superlattice finFETs (FF) for 1.8V/2.5V I/O applications in vertically-stacked Gate-All-Around horizontal nanowire technology (hNW) technology. Superlattice FF have a higher ION than I/O hNW reference devices and can be more easily integrated into a GAA hNW technology than Si I/O FF. These novel I/O FET structures exhibit competitive analog performance and are superior as ESD protection devices.

The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework. Through a double level access it offers a structural scaling of both standard cells (SDC) and SRAM by 50%. The proposed process flow requires accurate control of the elevation dimension for manufacturability. Based on TCAD analysis, the CFET can eventually outperform the finFET device and meet the N3 targets in power and performance. To achieve that, the dominating parasitic resistance of the deep vias needs to be reduced by the introduction of advanced MOL contacts featuring thin barriers.

In this paper, the performance of standard cells scaled down to 4.5 metal tracks based on Lateral NanoSheets is investigated for 3nm technology node targets using relevant logic benchmarks and power-aware metrics. The cell layout and parasitics in 4.5T cells set strong constraints on the NanoSheets geometry. The optimized NanoSheets could still outperform FinFETs by 9 to 20% frequency depending on circuit context, reaching 3nm node targets. An extra 21% performance improvement is expected with device level boosters enablement.

We look at several scaling boosters necessary to accomplish CMOS area scaling towards the 2nm node. We consider aspects of standard cell area scaling, transistor architecture, SRAM, and BEOL. We also demonstrate integrated flows and hardware feasibility for such scaling boosters.