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Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction (LVP) and Memory Renaming (MRN) mitigate load data dependence by predicting the data value of a load instruction. However, they fail to mitigate load resource dependence as the predicted load instruction gets executed nonetheless. Our goal in this work is to improve ILP by mitigating both load data dependence and resource dependence. To this end, we propose a purely-microarchitectural technique called Constable, that safely eliminates the execution of load instructions. Constable dynamically identifies load instructions that have repeatedly fetched the same data from the same load address. We call such loads likely-stable. For every likely-stable load, Constable (1) tracks modifications to its source architectural registers and memory location via lightweight hardware structures, and (2) eliminates the execution of subsequent instances of the load instruction until there is a write to its source register or a store or snoop request to its load address. Our extensive evaluation using a wide variety of 90 workloads shows that Constable improves performance by 5.1% while reducing the core dynamic power consumption by 3.4% on average over a strong baseline system that implements MRN and other dynamic instruction optimizations (e.g., move and zero elimination, constant and branch folding). In presence of 2-way simultaneous multithreading (SMT), Constable's performance improvement increases to 8.8% over the baseline system. When combined with a state-of-the-art load value predictor (EVES), Constable provides an additional 3.7% and 7.8% average performance benefit over the load value predictor alone, in the baseline system without and with 2-way SMT, respectively., Comment: To appear in the proceedings of 51st International Symposium on Computer Architecture (ISCA)

The illegal disposal of trash is a major public health and environmental concern. Disposing of trash in unplanned places poses serious health and environmental risks. We should try to restrict public trash cans as much as possible. This research focuses on automating the penalization of litterbugs, addressing the persistent problem of littering in public places. Traditional approaches relying on manual intervention and witness reporting suffer from delays, inaccuracies, and anonymity issues. To overcome these challenges, this paper proposes a fully automated system that utilizes surveillance cameras and advanced computer vision algorithms for litter detection, object tracking, and face recognition. The system accurately identifies and tracks individuals engaged in littering activities, attaches their identities through face recognition, and enables efficient enforcement of anti-littering policies. By reducing reliance on manual intervention, minimizing human error, and providing prompt identification, the proposed system offers significant advantages in addressing littering incidents. The primary contribution of this research lies in the implementation of the proposed system, leveraging advanced technologies to enhance surveillance operations and automate the penalization of litterbugs.

The people in the world who are hearing impaired face many obstacles in communication and require an interpreter to comprehend what a person is saying. There has been constant scientific research and the existing models lack the ability to make accurate predictions. So we propose a deep learning model trained on ASL i.e. American Sign Language which will take actions in the form of ASL as input and translate it into text. To achieve the translation a Convolution Neural Network model and a transfer learning model based on the VGG16 architecture are used. There has been an improvement in accuracy from 94% of CNN to 98.7% of Transfer Learning, an improvement of 5%. An application with the deep learning model integrated has also been built., Comment: Will be published in IEEE Explore; Typos corrected

Data Prefetching is a technique that can hide memory latency by fetching data before it is needed by a program. Prefetching relies on accurate memory access prediction, to which task machine learning based methods are increasingly applied. Unlike previous approaches that learn from deltas or offsets and perform one access prediction, we develop TransforMAP, based on the powerful Transformer model, that can learn from the whole address space and perform multiple cache line predictions. We propose to use the binary of memory addresses as model input, which avoids information loss and saves a token table in hardware. We design a block index bitmap to collect unordered future page offsets under the current page address as learning labels. As a result, our model can learn temporal patterns as well as spatial patterns within a page. In a practical implementation, this approach has the potential to hide prediction latency because it prefetches multiple cache lines likely to be used in a long horizon. We show that our approach achieves 35.67% MPKI improvement and 20.55% IPC improvement in simulation, higher than state-of-the-art Best-Offset prefetcher and ISB prefetcher.

Machine learning algorithms have shown potential to improve prefetching performance by accurately predicting future memory accesses. Existing approaches are based on the modeling of text prediction, considering prefetching as a classification problem for sequence prediction. However, the vast and sparse memory address space leads to large vocabulary, which makes this modeling impractical. The number and order of outputs for multiple cache line prefetching are also fundamentally different from text prediction. We propose TransFetch, a novel way to model prefetching. To reduce vocabulary size, we use fine-grained address segmentation as input. To predict unordered sets of future addresses, we use delta bitmaps for multiple outputs. We apply an attention-based network to learn the mapping between input and output. Prediction experiments demonstrate that address segmentation achieves 26% - 36% higher F1-score than delta inputs and 15% - 24% higher F1-score than page & offset inputs for SPEC 2006, SPEC 2017, and GAP benchmarks. Simulation results show that TransFetch achieves 38.75% IPC improvement compared with no prefetching, outperforming the best-performing rule-based prefetcher BOP by 10.44%, and ML-based prefetcher Voyager by 6.64%.

An effective two-spin density matrix (TSDM) for a pair of spin-$1/2$ degree of freedom, residing at a distance of $R$ in a spinful Fermi sea, can be obtained from the two-electron density matrix following the framework prescribed in Phys. Rev. A 69, 054305 (2004). We note that the single spin density matrix (SSDM) obtained from this TSDM for generic spin-degenerate systems of free fermions is always pinned to the maximally mixed state $i.e.$ $(1/2) \ \mathbb{I}$, independent of the distance $R$ while the TSDM confirms to the form for the set of maximally entangled mixed state (the so called "X-state") at finite $R$. The X-state reduces to a pure state (a singlet) in the $R\rightarrow 0$ limit while it saturates to an X-state with largest allowed value of von-Neumann entropy of $2 \ln2$ as $R \rightarrow \infty$ independent of the value of chemical potential. However, once an external magnetic field is applied to lift the spin-degeneracy, we find that the von-Neumann entropy of SSDM becomes a function of the distance $R$ between the two spins. We also show that the von-Neumann entropy of TSDM in the $R\rightarrow \infty$ limit becomes a function of the chemical potential and it saturate to $2 \ln2$ only when the band in completely filled unlike the spin-degenerate case. Finally we extend our study to include spin-orbit coupling and show that it does effect these asymptotic results. Our findings are in sharp contrast with previous works which were based on continuum models owing to physics which stem from the lattice model., Comment: 7 pages, 5 figures

We study Leggett-Garg inequality (LGI) of a two level system (TLS) undergoing non-Hermitian dynamics governed by a non-linear Bloch equation (derived in J. Phys. A: Math. Theor. 54, 115301 (2021)) across a PT-transition. We present an algebraic identification of the parameter space for the maximum violation of LGI (in particular $K_{3}$). In the PT-symmetric regime the maximum allowed value for $K_{3}$ is always found to be greater than the quantum bound (L\"{u}ders bound) of $3/2$ but it does not reach the algebraic maximum of $K_{3}=3$ in general. However, in the limit where PT-symmetry breaking parameter approaches the exceptional point from the PT-symmetric side, $K_{3}$ is found to asymptotically approach its algebraic maximum of 3. In contrast, the maximum value of $K_{3}$ always reaches its algebraic maximum in the PT-broken phase $i.e.$ $K_{3}\rightarrow 3$. We find that (i) the speed of evolution (SOE) must reach its maximum value (in the parameter space of initial state and the time interval between successive measurements) to facilitate the value of $K_{3} \rightarrow 3$, (ii) together with the constraint that its minimum value must run into SOE equals to zero during the evolution of the state. In fact we show that the minimum speed of evolution can serve as an order parameter which is finite on the PT-symmetric side and identically zero on the PT-broken side. Finally, we discuss a possible experimental realization of this dynamics by quantum measurement followed by post-selection procedure in a three level atom coupled to cavity mode undergoing a Lindbladian dynamics., Comment: 9 pages, 5 figures

We study Leggett-Garg inequalities (LGIs) for a two level system (TLS) undergoing Markovian dynamics described by unital maps. We find analytic expression of LG parameter $K_{3}$ (simplest variant of LGIs) in terms of the parameters of two distinct unital maps representing time evolution for intervals: $t_{1}$ to $t_{2}$ and $t_{2}$ to $t_{3}$. We show that the maximum violation of LGI for these maps can never exceed well known L\"{u}ders bound of $K_{3}^{L\ddot{u}ders}=3/2$ over the full parameter space. We further show that if the map for the time interval $t_{1}$ to $t_{2}$ is non-unitary unital then irrespective of the choice of the map for interval $t_{2}$ to $t_{3}$ we can never reach L\"{u}ders bound. On the other hand, if the measurement operator eigenstates remain pure upon evolution from $t_{1}$ to $t_{2}$, then depending on the degree of decoherence induced by the unital map for the interval $t_{2}$ to $t_{3}$ we may or may not obtain L\"{u}ders bound. Specifically, we find that if the unital map for interval $t_{2}$ to $t_{3}$ leads to the shrinking of the Bloch vector beyond half of its unit length, then achieving the bound $K_{3}^{L\ddot{u}ders}$ is not possible. Hence our findings not only establish a threshold for decoherence which will allow for $K_{3} = K_{3}^{L\ddot{u}ders}$, but also demonstrate the importance of temporal sequencing of the exposure of a TLS to Markovian baths in obtaining L\"{u}ders bound., Comment: 9 pages, 2 figures

Past research has proposed numerous hardware prefetching techniques, most of which rely on exploiting one specific type of program context information (e.g., program counter, cacheline address) to predict future memory accesses. These techniques either completely neglect a prefetcher's undesirable effects (e.g., memory bandwidth usage) on the overall system, or incorporate system-level feedback as an afterthought to a system-unaware prefetch algorithm. We show that prior prefetchers often lose their performance benefit over a wide range of workloads and system configurations due to their inherent inability to take multiple different types of program context and system-level feedback information into account while prefetching. In this paper, we make a case for designing a holistic prefetch algorithm that learns to prefetch using multiple different types of program context and system-level feedback information inherent to its design. To this end, we propose Pythia, which formulates the prefetcher as a reinforcement learning agent. For every demand request, Pythia observes multiple different types of program context information to make a prefetch decision. For every prefetch decision, Pythia receives a numerical reward that evaluates prefetch quality under the current memory bandwidth usage. Pythia uses this reward to reinforce the correlation between program context information and prefetch decision to generate highly accurate, timely, and system-aware prefetch requests in the future. Our extensive evaluations using simulation and hardware synthesis show that Pythia outperforms multiple state-of-the-art prefetchers over a wide range of workloads and system configurations, while incurring only 1.03% area overhead over a desktop-class processor and no software changes in workloads. The source code of Pythia can be freely downloaded from https://github.com/CMU-SAFARI/Pythia.

It is possible to simulate the dynamics of a single spin-$1/2$ ($\mathsf{PT~}$ symmetric) system by conveniently embedding it into a subspace of a larger Hilbert space with unitary dynamics. Our goal is to formulate a many body generalization of this idea i.e., embedding many body non-Hermitian dynamics. As a first step in this direction, we investigate embedding of "$N$" non-interacting spin-$1/2$ ($\mathsf{PT~}$ symmetric) degrees of freedom, thereby unfolding the complex nature of such an embedding procedure. It turns out that the resulting Hermitian Hamiltonian represents a cluster of $N+1$ spin halves with "all to all", $q$-body interaction terms ($q=1,...,N+1$) in which the additional spin-$1/2$ is a part of the larger embedding space. We can visualize it as a strongly correlated central spin model with the additional spin-$1/2$ playing the role of central spin. We find that due to the orthogonality catastrophe, even a vanishing small exchange field applied along the anisotropy axis of the central spin leads to a strong suppression of its decoherence arising from spin-flipping perturbations., Comment: 10 pages, 5 figures

Deep Neural Network (DNN) inference is emerging as the fundamental bedrock for a multitude of utilities and services. CPUs continue to scale up their raw compute capabilities for DNN inference along with mature high performance libraries to extract optimal performance. While general purpose CPUs offer unique attractive advantages for DNN inference at both datacenter and edge, they have primarily evolved to optimize single thread performance. For highly parallel, throughput-oriented DNN inference, this results in inefficiencies in both power and performance, impacting both raw performance scaling and overall performance/watt. We present Proximu$\$$, where we systematically tackle the root inefficiencies in power and performance scaling for CPU DNN inference. Performance scales efficiently by distributing light-weight tensor compute near all caches in a multi-level cache hierarchy. This maximizes the cumulative utilization of the existing bandwidth resources in the system and minimizes movement of data. Power is drastically reduced through simple ISA extensions that encode the structured, loop-y workload behavior. This enables a bulk offload of pre-decoded work, with loop unrolling in the light-weight near-cache units, effectively bypassing the power-hungry stages of the wide Out-of-Order (OOO) CPU pipeline. Across a number of DNN models, Proximu$\$$ achieves a 2.3x increase in convolution performance/watt with a 2x to 3.94x scaling in raw performance. Similarly, Proximu$\$$ achieves a 1.8x increase in inner-product performance/watt with 2.8x scaling in performance. With no changes to the programming model, no increase in cache capacity or bandwidth and minimal additional hardware, Proximu$\$$ enables unprecedented CPU efficiency gains while achieving similar performance to state-of-the-art Domain Specific Accelerators (DSA) for DNN inference in this AI era., Comment: 18 pages, 21 figures

High main memory latency continues to limit performance of modern high-performance out-of-order cores. While DRAM latency has remained nearly the same over many generations, DRAM bandwidth has grown significantly due to higher frequencies, newer architectures (DDR4, LPDDR4, GDDR5) and 3D-stacked memory packaging (HBM). Current state-of-the-art prefetchers do not do well in extracting higher performance when higher DRAM bandwidth is available. Prefetchers need the ability to dynamically adapt to available bandwidth, boosting prefetch count and prefetch coverage when headroom exists and throttling down to achieve high accuracy when the bandwidth utilization is close to peak. To this end, we present the Dual Spatial Pattern Prefetcher (DSPatch) that can be used as a standalone prefetcher or as a lightweight adjunct spatial prefetcher to the state-of-the-art delta-based Signature Pattern Prefetcher (SPP). DSPatch builds on a novel and intuitive use of modulated spatial bit-patterns. The key idea is to: (1) represent program accesses on a physical page as a bit-pattern anchored to the first "trigger" access, (2) learn two spatial access bit-patterns: one biased towards coverage and another biased towards accuracy, and (3) select one bit-pattern at run-time based on the DRAM bandwidth utilization to generate prefetches. Across a diverse set of workloads, using only 3.6KB of storage, DSPatch improves performance over an aggressive baseline with a PC-based stride prefetcher at the L1 cache and the SPP prefetcher at the L2 cache by 6% (9% in memory-intensive workloads and up to 26%). Moreover, the performance of DSPatch+SPP scales with increasing DRAM bandwidth, growing from 6% over SPP to 10% when DRAM bandwidth is doubled., Comment: This work is to appear in MICRO 2019

We study the dynamics of two level systems described by non-hermitian Hamiltonians with real eigenvalues. Within the framework of hermitian quantum mechanics, it is known that maximal violation of Leggett-Garg inequality is bounded by $3/2$ (Luder's bound). We show that this absolute bound can be evaded when dynamics is governed by non-hermitian Hamiltonians. Moreover, the extent of violation can be optimized to reach its algebraic maximum of $3$ which is otherwise only feasible when the Hilbert space is infinite dimensional in the hermitian case. The extreme violation of Leggett-Garg inequality is shown to be directly related to the two basic ingredients: (i) The Bloch equation for the two level system has non-linear terms which allow for accelerated dynamics of states on the Bloch sphere exceeding all known quantum speed limits of state evolution; and (ii) We need to ensure that the quantum trajectory of states always lies on a single great circle (geodesic path) on the Bloch sphere at all times., Comment: v2: Includes (a) A numerical comparison of our predictions with existing experimental results (Ref. 44 in the article) ; and (b) An extensive discussion of Leggett-Garg Inequality in the context of possible embedding of the non-hermitian dynamics within a higher dimensional Hilbert space following unitary time evolution and postselection

After the rise of E-commerce, social media and messenger bots, rapid developments have been made in the field of connecting things, gadgets, and devices, i.e, the Internet of Things (IoT). In the fast-paced lifestyle, it is very difficult to maintain multiple keys for traditional mechanical locks. Electromagnetic smart locks are a possible solution to this problem. To connect a smart lock with a key, Bluetooth Low Energy (BLE) protocol can be used. BLE protocol is vulnerable to Man-in-the-Middle (MITM) attack. Ensuring security over BLE is an ongoing challenge. This paper aims to analyze the MITM vulnerability of BLE and develop a possible solution for designing smart-locks with an increased level of security. The observation shows that the combination of Image Steganography and Cryptography helps to overcome the vulnerabilities of BLE protocol., Comment: Fifth International Symposium on Security in Computing and Communications (SSCC'17)