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This paper introduces a low-power fully differential fixed window level-crossing analog-to-digital converter (LC-ADC) for wireless medical implantable devices. The LC-ADC could be an excellent candidate for low-power systems due to the reduction of sampling points for bio-potential signals. Different from existing fixed window LC-ADCs, which use a 1-bit DAC or scaler and two reference levels to move the input signal to the comparison window, a simplified scheme is proposed in which the DAC or scaler is removed and a single-reference level is used to create the comparison window. The proposed LC-ADC utilizes a single-reference comparator, which leads to a simplified implementation and significant reduction in power consumption and circuit area. In addition, using a single reference level and removing DAC, leads to a decrease in the complexity of the controlling logic. The proposed LC-ADC is simulated in 0.18 μ m CMOS technology. The simulation results achieve an effective number of bits (ENOB) of up to 6.5 bits with about 59–141 nW power consumption under 0.8 V supply and input signal bandwidth from 5 Hz to 4 kHz. [ABSTRACT FROM AUTHOR]

This paper presents a background calibration method assisted with noise-shaping, for a 10-b bridged SAR ADC. It proposes calibrating the mismatches from the MSB capacitors using the LSBs. First-order noise-shaping has been employed to facilitate the calibration as well as the analog-to-digital conversion. Since noise-shaping is able to shape both the comparator input and quantization noise, it is expected to improve the calibration effects as well as the SNR, for the SAR ADC. Measurement results show, upon the proposed calibration, the SAR's INL and SNR are improved by 3 LSB and 9 dB, respectively, compared to when the noise shaping is off. Fabricated using a 55 nm CMOS MOMCAP technology and tested with a −2.5 dB sinewave input, the bridged SAR ADC achieves an SNR of 62.2 dB and an INL better than 1 LSB, when consuming a power of 7 2 μ W , at a supply voltage of 1.2 V and sampling frequency of 50 kHz. The ADC's active area is 3 0 0 × 3 8 0 μ m 2 . [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65 nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies. [ABSTRACT FROM AUTHOR]

This paper presents a novel second-order passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) based on active gain. The proposed scheme achieves a further improvement in the signal-to-noise ratio (SNR) of the proposed NS SAR ADC by reducing the kT/C noise and the conversion rate. After having presented the conversion principle, the theoretical analysis of the performance enhancement based on noise and other considerations is presented. [ABSTRACT FROM AUTHOR]

Analog-to-digital converters (ADCs) transform the analog signals of time-variant physical quantity into digital signals for storing and processing. As the bridge between natural science and information science, ADCs are indispensable in modern industry and scientific research. Since the 1920s, uniform time-domain sampling has become the basic principle in the field of ADCs with the establishment of its electronic implementation and mathematical theory. In the following decades, applications such as positron emission tomography (PET), nuclear fusion neutron spectrum, neutrino detection, etc., which require sampling of many high-speed signals, have emerged one after another. In these applications, ADCs based on uniform time-domain sampling show disadvantages of high power consumption and high cost, so the signal has to be pre-processed before digitalization with losing the original information of the signal. Based on value-domain sampling, the Multi-Voltage Threshold (MVT) method digitizes the signal through several voltage thresholds and then reconstructs the signal with a computer using prior information. The MVT method makes it possible to accurately digitize a large number of high-speed signals. At present, the MVT method has been applied in PET, X-ray security inspection, neutron logging, proton therapy monitoring, etc. This paper outlines the principle of the MVT method, introduces the research progress of MVT electronics in recent years, and further provides an outlook of the MVT research trend.

The article considers an International Electrotechnical Commission (IEC) standard digital output current sensor with improved current conversion characteristics and expanded functionality. The results of the study of primary electromagnetic current converters used in the current sensor are presented. It is proposed to combine the functions of converting signals into the digital format of the IEC 61850 standard and the functions of current relay protection in the current sensor. The features of the newly developed sensors are shown, allowing for a significant improvement in the main characteristics of relay protection. [ABSTRACT FROM AUTHOR]

Copyright of CT Theory & Applications is the property of Editorial Department of CT Theory & Applications and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A "sandwich" capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays' benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages. [ABSTRACT FROM AUTHOR]

AbstractIn this research, a novel application as an acoustic analog-to-digital converter (ADC) is introduced, utilizing all-solid phononic crystals. The structure consists of a two-channel directional coupler designed to achieve 2-bit quantization. As the input signal amplitude increases, additional stress is applied to the background, inducing a slight change in the mass density of the phononic crystal structure. This structure is composed of an array of iron scatterers embedded in a polymerization of methyl methacrylate (PMMA) medium, with a selected working frequency of 67.5 kHz. To guide the applied acoustic wave, a directional coupler is employed. In the proposed model, transmission values below 0.3 are interpreted as "0," while values exceeding 0.3 are considered "1." It is crucial that a transmission range of 0.4–0.6 signifies a logical "1" for both active outputs. The fabrication tolerance of the directional coupler rods has been calculated, and the maximum transmission change is equal to 0.03 in a 2 µm changing range around the central radius [ABSTRACT FROM AUTHOR]

Mixed-signal applications have emerged as a significant trend in the semiconductor industry, with considerable efforts directed towards developing fast and accurate designs that integrate both analog and digital components. However, mixed-signal verification presents a major challenge due to the slow verification time and limited robustness of traditional verification techniques. In this study, a verification architecture for a successive-approximation register (SAR) analog-to-digital converter (ADC) real number model (Real Number Modeling – RNM) using SystemVerilog is presented, which utilizes an efficient UVM-based methodology. The proposed approach combines the UVM capabilities with the RNM model of the SAR ADC to generate a reusable, fast, and robust verification environment with a reduced time-to-market. The testbench creation and simulation were carried out using Cadence Xcelium. The proposed verification architecture employs constrained-random stimulus generation, analog assertions, and coverage metrics to enhance verification effectiveness. Additionally, aim of this work is to emphasize on the RNM efficiency with SystemVerilog, and apply its modeling capabilities for a SAR ADC. The presented real number model was compared to a Verilog-AMS model. The conducted experiments provided evidence that the proposed RNM model exhibits a significant improvement in simulation efficiency compared to previous works documented in the literature (simulation time was at 0.5 s, compared to a Verilog-AMS reference model's simulation at 20 s). This improvement in efficiency is achieved without compromising on the accuracy of the simulation, ensuring that the model maintains a satisfactory level of precision. [ABSTRACT FROM AUTHOR]

Background. Most modern digital voltmeters use an integrating time-to-pulse analogue-to-digital converter (ADC). The conversion process can be divided into two stages – integration and counting. During the counting, in accordance with the principle of the converter, the integrated input value is compared with the reference value stored in the converter. The goal is to develop a methodology for building f bipolar reference voltage source without reducing the accuracy parameters. Materials and methods. An approach to the construction of a bipolar reference voltage source of an integration analogue-digital converter is presented, in which integration occurs during the entire time of the input signal conversion. The novelty of the approach lies in the development of circuitry solutions for the use of a single precision Zener diode to form a bipolar reference voltage. Results. Presented: principal electrical scheme of a bipolar reference voltage source and its mathematical model of error; recommendations for the choice of a radio elements used; method of the schematic construction of a bipolar reference voltage source. Conclusions. The use of the considered technique allows to increase the stability of the threshold levels of comparison of the Schmitt trigger and, thus, to more accurately integrate the input signal. The results can be used to build integrating ADC for wide application in industrial devices and other fields of science and technology.

The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter's own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of −3.3 V. [ABSTRACT FROM AUTHOR]

This paper investigates a 2-bit all-optical analog-to-digital converter (AO-ADC) using the photonic crystal (PhC) structure. The proposed structure comprises a 27 × 27 grid of silicon rods in air with a refractive index of 3.6. In the design of this converter, a linear demultiplexer and an optical encoder are used. The optical demultiplexer has one input and three outputs. Optical coding has three inputs and two outputs. In general, this converter consists of one input and two outputs, and according to the output light power from the structure and the threshold level of the converter, two logical 0 and 1 states are created in the output. The footprint of the proposed AO-ADC is as small as 118.5 µm2 making it more suitable for use in the optical integrated circuits (OICs) compared to the previous structures. The proposed AO-ADC works at an operating wavelength of 1550 nm with a response time of about 0.6 ps and also works with lower optical intensity. [ABSTRACT FROM AUTHOR]

Analog-to-digital converters of radio signals, which are based on the phenomenon of superconductivity and the Josephson effect, are proposed to use in order to increase the efficiency of digital antenna arrays. Digital beamforming systems were analysed. Application of the proposed approach was shown to promote processing signals directly at carrier frequencies in the SHF and EHF bands. This approach allows to exclude frequency mixers, local oscillators and intermediate frequency filters from a receiving module. A parallel scheme with comparators on superconducting quantum interferometers is proposed for constructing a superconducting ADC. A digital Gray code is formed at the output of the ADC. The proposed scheme being utilizing, when the input signal increases, each comparator passes through several thresholds, and if Gray codes are applied, only one of the output bits changes between consecutive numbers. Therefore, Gray codes are less sensitive to errors that arise due to small differences in comparator’s thresholds. This promotes reduction of the bit error probability. As an outcome the performed analysis, it was shown that generators of single-quantum pulses on single Josephson junction with a hysteresisfree current-voltage characteristic can be used for constructing comparators, that provides obtaining a high time resolution. The dependence of time resolution on Josephson junction parameters, namely dielectric thickness, relative dielectric permeability and critical current density, was investigated. The resolution was shown to be equal units — tenths of a ns, and this allows using such devices for signal processing at frequencies of several hundred GHz. The time resolution changes with changes in the critical current density of a Josephson junction and in the dielectric thickness and it is almost independent on the relative dielectric permittivity. The sensitivity of the comparator on a single Josephson junction was evaluated. An analytical expression was obtained, it can be applied to estimate how parameters of the Josephson junction equivalent circuit, namely, electrostatic capacity, nonlinear conductivity, and critical current impact on the sensitivity of the comparator. The conducted studies showed that the sensitivity can be units of nA, which exceeds significantly the sensitivity of similar circuits based on semiconductors. [ABSTRACT FROM AUTHOR]

Abstract Hybrid combiner and precoder architectures, radio frequency (RF) chain, analog phase shifters, digital-to-analog converter (DAC), and analog-to-digital converter (ADC) are components of a millimeter wave cellular system. Prior works in the area of millimeter wave cellular system design employ receiver with infinite bit and large amount of RF chain that scales linearly with the quantity of transmitting and receiving antennas. This mode of design no doubt increases power demand or requirement of a typical millimeter wave system. In this work, hybrid architecture with few RF chains and small number of ADC bits are proposed and are used as candidate for millimeter wave channel estimation and cellular communication. In that connection, least square (LS), orthogonal matching pursuit (OMP), compressed sampling matching pursuit (CoSAMP), and deep learning (DL) techniques are utilized for analytical investigation. Indeed, computational results reveal that, when ADC consisting of uniform mid- rise quantizer is employed, the performance of 4 and 6 bits at signal-to-noise ratio (SNR) values of − 10 dB and 20 dB is at par with infinite bit (unquantized case). As a validation, DL compares favorably well with adaptive compressed sensing (ACS) technique previously used in the literature for channel estimation, while OMP and CoSAMP show better performance than ACS.

A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. This circuit is based almost entirely on formal expressions for every building block circuit. This approach led to a strikingly short development time where every design choice was defensibly optimum and the prototype chip yielded near-textbook performance from the first silicon. The figure of merit is at the state of the art.

This paper introduces and experimentally validates a switched-capacitor inverter-based second-order 3-tap FIR single-bit Delta-Sigma Modulator ( $\Delta \Sigma $ M) designed for nanowatt-level analog-to-digital conversion in wearable healthcare devices. The focus is on applications with energy harvesters, emphasizing continuous monitoring of chronic conditions and closed-loop drug-delivery systems. The design methodology addresses ultralow-power considerations at both architectural and transistor levels, tackling challenges like process variations without relying on complex digital calibration techniques. Experimental results from prototypes, implemented on a standard 180-nm CMOS process, reveal a peak SINAD of 77.8 dB and SNR of 79.4 dB, with a power consumption of 71.5 nW at a 900-mV supply. Measurements across nine chip samples are consistent, demonstrating low DC offset, with low temperature drift and live sensitivity. The outcomes confirm the modulator suitability for energy-harvested wearable systems.

Hybrid combiner and precoder architectures, radio frequency (RF) chain, analog phase shifters, digital-to-analog converter (DAC), and analog-to-digital converter (ADC) are components of a millimeter wave cellular system. Prior works in the area of millimeter wave cellular system design employ receiver with infinite bit and large amount of RF chain that scales linearly with the quantity of transmitting and receiving antennas. This mode of design no doubt increases power demand or requirement of a typical millimeter wave system. In this work, hybrid architecture with few RF chains and small number of ADC bits are proposed and are used as candidate for millimeter wave channel estimation and cellular communication. In that connection, least square (LS), orthogonal matching pursuit (OMP), compressed sampling matching pursuit (CoSAMP), and deep learning (DL) techniques are utilized for analytical investigation. Indeed, computational results reveal that, when ADC consisting of uniform mid- rise quantizer is employed, the performance of 4 and 6 bits at signal-to-noise ratio (SNR) values of − 10 dB and 20 dB is at par with infinite bit (unquantized case). As a validation, DL compares favorably well with adaptive compressed sensing (ACS) technique previously used in the literature for channel estimation, while OMP and CoSAMP show better performance than ACS. [ABSTRACT FROM AUTHOR]

This article presents a design of a VCO‐based ADC based on n‐type metal oxide thin‐film transistor (TFT). The TFTs are fabricated on a glass substrate using Indium Zinc Oxide technology. The VCO‐based ADC consists of a VCO, a level shifter and a sampling circuit, while the VCO is composed of a charge‐discharge cell and an inverter chain. The ADC has a 1.464 mm 2 area, 0.89 mW power consumption, an output frequency range of 1.41 KHz/V tuning sensitivity, 1.8% maximum linear error and achieves a SNDR of 34.2 dB in the case of an input signal of 1.5 Hz and a sampling rate of 20 S/s. [ABSTRACT FROM AUTHOR]

The increase in the power of power semiconductor converters operated in the railway industry is associated with the use of group connections of power semiconductor devices in them, the variation in the parameters of which, and, therefore, their unequal load, causes a decrease in the reliability of the power semiconductor converters as a whole. In this regard, it becomes necessary to develop and implement innovative methods and devices for express diagnostics in order to identify potentially unreliable semiconductor devices, and the implementation of technical diagnostics should not be associated with dismantling the electrical circuits of the converters. The method is proposed for determining potentially unreliable power semiconductor devices in group connections based on the results of analyzing the distribution of reverse currents in parallel branches, which made it possible to create a series of devices for diagnosing power semiconductor devices in converters, both with and without communication resistors. The methodological error of measurements made using the developed express diagnostics devices of the transducers do not exceed the standard value equal to 10 %.

This paper presents a novel approach for accurately testing triangular waveform generators by leveraging the Ramp Vernier Test methodology commonly used for Analog-to-Digital Converters (ADCs). The proposed procedure enables efficient measurement of the nonlinearity of a triangular waveform using a low-cost data acquisition board. The key idea is to utilize the waveform generator under test to produce the stimulus signal for the data acquisition system's testing. By analyzing the results of this test, the nonlinearity of the acquisition system can be determined and subsequently corrected. This approach effectively eliminates the influence of the acquisition system's nonlinearity on the estimation of the nonlinearity of the waveform generator, ensuring accurate and reliable measurements. [ABSTRACT FROM AUTHOR]

As the preferred architecture for high-speed and high-resolution analog-to-digital converters (ADC), the accuracy of pipelined ADC is limited mainly by various errors arising from multiple digital-to-analog converters (MDAC). This paper presents a multi-dimensional (M-D) MDAC calibration based on a genetic algorithm (GA) in a 12-bit 750 MS/s pipelined ADC. The proposed M-D MDAC compensation model enables capacitor mismatch and static interstage gain error (IGE) compensation on the chip and prepares for subsequent background calibration based on a pseudo-random number (PN) injection to achieve accurate compensation for dynamic IGE. An M-D coefficient extraction scheme based on GA is also proposed to extract the required compensation coefficients of the foreground calibration, which avoids falling into local traps through MATLAB. The above calibration scheme has been verified in a prototype 12-bit 750 MS/s pipelined ADC. The measurement results show that the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are increased from 49.9 dB/66.7 dB to 59.6 dB/77.5 dB with the proposed calibration at 25 °C. With the help of background calibration at 85 °C, the SNDR and SFDR are improved by 3.4 dB and 8.8 dB, respectively. [ABSTRACT FROM AUTHOR]

Variants of the circuitry of storage cells with analog-to-digital conversion in focal plane arrays (FPAs) of the long-wavelength IR range are considered. The necessity of a multiple increase in the charge capacity of the storage cell to improve the threshold characteristics of the FPA is substantiated. A new version of the storage cell with analog-to-digital conversion, which has several advantages in comparison with analogues (high linearity, low consumption, and low noise) is proposed. The results of the study of a test crystal of a CMOS integrated readout circuit manufactured using the HCMOS8D technology of Mikron JSC with a design standard of 0.18 micrometers are presented. [ABSTRACT FROM AUTHOR]

The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter’s own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of −3.3 V.

Background. Most modern digital voltmeters use an analog-to-digital converter (ADC) of the time-pulse type with two-stage integration, which takes place in two stages – integration and counting. During the counting, in accordance with the principle of operation of the converter, the input information is not received in the ADC and is lost. The aim is to develop a technique for converting an analog quantity into a discrete one without losing information the input signal. Materials and methods. An approach to the construction of an integrating converter of the measured voltage in a time and interval in which integration occurs during the entire time of the input signal conversion is presented. The novelty of the approach is to eliminate the waste of time on service signals for resetting (or zeroing) the voltage on the storage capacitor, due to the use of a controlled generator of linearly varying voltage on two op-amps, and the possibility of direct measurement of the bipolar input signal. Results. A technique for the circuit design of an analog magnitude converter in a time interval is proposed, which allows the conversion of a bipolar input signal without additional circuit elements. The following are presented: a schematic electrical diagram of the converter; a mathematical model of converting the input signal into a time interval; recommendations for obtaining a digital code at the output of the converter; a method of circuit design of the converter. Conclusions. The use of the considered technique makes it possible to integrate the input signal without losing time to perform transformations on service signals. The results can be used to build integrating ADCs for wide application in industrial devices and in other fields of science and technology.

Copyright of Journal of Tiangong University is the property of Journal of Tianjin Polytechnic University and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

However, the approach to designing laboratory stands for training students and electrical per-sonnel on the specifics of using digital protections in most cases has remained the same, which does not allow for fully realizing their potential. The purpose of the work is to improve the qual-ity of the knowledge and practical skills received by students in the work with digital protection blocks. To achieve the goal, a specialized laboratory stand for testing digital security terminals has been developed. The stand consists of a mathematical model of the protected object, imple-mented in the form of a computer program and hardware, which allows real-time conversion of changes in model mode parameters into physical signals transmitted to the digital protection de-vice. The stand provides the terminal feedback with the model, which makes it possible to study the protection behavior in the characteristic operating modes of the protected element. The pro-tection of the "line-transformer" block using the Siprotec 4 7SJ6 Siemens terminal is considered. It is possible to calculate the protection operation parameters, configure the digital protection device, and also check the correct operation of the protections by automatically simulating nor-mal and emergency operation modes of the protected object. The software and hardware of the stand makes it easy to expand its capabilities by adding new models of power system objects and other digital protection devices. The equipment used in the developed stand does not require significant capital investments, which makes this approach accessible to higher educational insti-tutions.

The article is aimed at familiarizing medical specialists involved in registration and analysis of electroencephalographic (EEG) examinations with the basic principles of operation and the design of a modern EEG recorder. Understanding the technical fundamentals behind operation of EEG equipment should help medical personnel to correctly use all its capabilities and ultimately improve quality of medical care. The basic diagram of the electroencephalograph operation, the types and features of EEG electrodes, the opportunities and limitations of digitally processed bioelectric signals are discussed. A review on the main technical characteristics of EEG equipment and their influence on the quality of the recorded signal is presented.

The authors update the issue disassembly-free control and correction of all components of the error of measuring channels with multi-bit analog-to-digital converters (ADCs). The main disadvantages of existing methods for automatic control of the parameters of multi-bit ADCs, in particular their nonlinearity, are identified. Methods for minimizing instrumental errors and errors caused by limited internal resistances of closed switches, input and output resistances of active elements are investigated. The structures of devices for determining the multiplicative and nonlinear components of the error of multi-bit ADCs based on resistive dividers built on single-nominal resistors are proposed and analyzed. The authors propose a method for the correction of additive, multiplicative and nonlinear components of the error at each of the specified points of the conversion range during non-disassembly control of the ADC with both types of inputs. The possibility of non-disassembly control, as well as correction of multiplicative and nonlinear components of the error of multi-bit ADCs in the entire range of conversion during their on-site control is proven. ADC error correction procedures are proposed. These procedures are practically invariant to the non-informative parameters of active structures with resistive dividers composed of single-nominal resistors. In the article the prospects of practical implementation of the method of error correction during non-dismantling control of ADC parameters using the possibilities provided by modern microelectronic components are shown. The ways to minimize errors are proposed and the requirements to the choice of element parameters for the implementation of the proposed technical solutions are given. It is proved that the proposed structure can be used for non-disassembly control of multiplicative and nonlinear components of the error of precision instrumentation amplifiers.

Results of measurement of higher harmonic currents using a device for measuring telluric currents with a limiting registration bandwidth of 250 kHz are presented. A four-channel 18-bit analog-to-digital converter with a sampling rate of 500 000 Hz (1 count per 2 μs) is used to digitize information. On the stand created on the basis of the developed device, industrial frequency currents flowing along the ground were recorded. Dynamic spectrograms of current harmonics in the static mode and when switching loads of electricity consumers were recorded. It is shown that increased levels of high-frequency interference are recorded at frequencies of 60 kHz and above. The possibility of developing a special device for continuous monitoring of the levels of high-frequency harmonics of currents flowing through the neutral without direct connection of the measuring device to the power-supply equipment is shown. [ABSTRACT FROM AUTHOR]

Compressed Sensing (CS) has been applied to electrocardiogram monitoring in wireless sensor networks, but existing sampling and compression circuits consume too much hardware. This paper proposes a low-power and small-area sampling and compression circuit with an Analog-to-Digital Converter (ADC) and a CS module. The ADC adopts split capacitors to reduce hardware consumption and uses a calibration technique to decrease offset voltage. The CS module uses an approximate addition calculation for compression and stores the compressed data in pulsed latches. The proposed addition completes the accurate calculation of the high part and the approximate calculation of the low part. In a 55 nm CMOS process, the ADC has an area of 0.011 mm2 and a power consumption of 0.214 μW at 10 kHz. Compared with traditional design, the area and power consumption of the proposed CS module are reduced by 19.5% and 31.7%, respectively. The sampling and compression circuit area is 0.325 mm2, and the power consumption is 2.951 μW at 1.2 V and 100 kHz. The compressed data are reconstructed with a percentage root mean square difference of less than 2%. The results indicate that the proposed circuit has performance advantages of hardware consumption and reconstruction quality. [ABSTRACT FROM AUTHOR]

Objectives. The study aimed to develop interspecies and interclass methods for constructing coherent radio engineering systems based on a modular complementary structure.Methods. A set of modules and submodules having no narrow specialization and together constituting a flexible broadband hardware-reconfigurable software-defined radio engineering structure is considered as the basic set for constructing a digital radio photonic system path. Due to their broadbandness and complementary structure, modules and submodules have many applications both as self-sustained devices and as part of more complex systems.Results. Functional diagrams of modern digital receiver-shapers, as well as modules for amplifying radio frequency signals and converting radio frequency signals into an optical signal are presented along with a radio photonic synchronization network for generating clock signals. Calculations of the introduced phase error of a quartz singlemode fiber and graphs of the dependence of the change in the signal phase on external influencing factors are given. A concept for integrating the presented modules into the construction of a modular transceiver multiposition wideband coherent digital radio photonic system is proposed. The results of calculating radiation patterns and mathematical modeling the beam deflection of a broadband antenna array are presented along with antenna systems based thereon.Conclusions. The proposed circuit design solutions allow the time required for developing new types of systems to be significantly reduced due to the range of ready-made technical solutions. Not only are the parameters of the developed devices comparable to the best world analogues, but they also surpass existing solutions in terms of system integration. The developments have been tested under R&D project at the Kaluga Scientific Research Institute of Radio Technology and Hardware Solution Technologies (TAR). The proposed solutions are integrated at the subsystem level into advanced developments of products for civil and special purpose. Further development of the concept of building ultra-wideband devices allows reaching a new level in the technology of constructing modular multiposition coherent digital radio photonic systems.

This paper presents a 1-GS/s12-bit pipelined analog-to-digital converter (ADC) fabricated in 40-nm CMOS technology that optimizes the settling time, bit error rate, and robustness. This ADC uses an improved timing called pre-quantization timing (PQT), which implements quantization in half the time of the sampling phase to maximize the output-settling time of the operational amplifier (op-amp). A complete clocking scheme along with a delay lock loop (DLL) is proposed to generate an accurate timing no matter how process, voltage, and temperature (PVT) change. Based on PQT, a high-speed comparator circuit is adopted to obtain a bit error rate (BER) below 10−15. Sample and hold amplifier (SHA) is used to guarantee robustness over the wide input frequency. Furthermore, a low-cost automatic calibration is implemented to correct residual curves, and inter-stage gain errors are also corrected. This ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.3 dB and a spurious-free dynamic range (SFDR) of 78.5 dB at a 227 MHz input frequency. The measured differential nonlinearities (DNL) and integral nonlinearities (INL) after calibration are ±0.7 LSB and ±1.50 LSB, respectively. The power consumption of the ADC core is 97.6-mW, and the Walden figure of merit (FoM) is 172.9-fJ/conversion-step. [ABSTRACT FROM AUTHOR]

For newly developed measuring systems, it is easy to estimate type-B uncertainties based on technical data from the measuring modules applied. However, it is difficult to estimate A-type uncertainties due to the unknown type and level of interferences infiltrating the measuring system. This is a particularly important problem for measurements carried out in the presence of typical of power grid disturbances. The aim of the research was to develop a method and a measurement stand for experimental assessment of uncertainties in a measuring system that makes use of data acquisition modules containing analog-to-digital converters (ADCs). The paper describes, in detail, the design of a completed test stand. It presents an original application in the LabVIEW environment, which enables testing the dependence of the uncertainties with the quantity of the measurements averaged in a series, for different kinds and levels of interferences infiltrating the measuring path. The results of tests for several popular measuring modules are presented. An analysis of the determined uncertainties was carried out in relation to the parameters of the tested measurement modules and for various levels of interferences. It is proved that an increase in the number of averaged measurements to approx. 100–200 always results in a decrease in uncertainty for each tested module and under all conditions. However, a further increase in the quantity of measurements, even up to 1000 averaged measurements, proved reasonable only for high-accuracy modules, in particular with a high level of interferences. An excessive increase in the quantity of averaged measurements proved a low effect for modules characterised by a low resolution and with a low level of interferences. The measurement results also proved that when estimated, uncertainties in the interference probability distribution are significant, especially if they deviate from normal distribution. [ABSTRACT FROM AUTHOR]

This paper presents a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It uses a coarse-conversion 5-bit asynchronous self-timed SAR ADC combined with a fine-conversion second-order delta-sigma modulator to efficiently obtain a high signal-to-noise distortion ratio (SNDR). An integrator circuit using a high-gain dynamic amplifier is proposed to achieve higher SNDR. The dynamic amplifier uses a switched tail current source to operate periodically, simplifying the common-mode feedback circuit, reducing unnecessary static current, and improving the PVT robustness. Dynamic error correction techniques, such as redundancy, chopping, and dynamic element matching (DEM) are used to achieve low offset and high linearity. And a 2-bit asynchronous SAR quantizer with an embedded feed-forward adder is used in the second-order delta-sigma modulator to reduce the quantization noise caused by redundancy, and further achieve higher energy efficiency. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth at a 200 kHz sampling clock while consuming only 170 μ W from a 2.5 V supply and the core area is 0.55 mm 2 . This results in a Schreier figure of merit (FoM) of 184.7 dB. [ABSTRACT FROM AUTHOR]