Search

The potential to exploit single-walled carbon nanotubes (SWNTs) in advanced electronics represents a continuing, major source of interest in these materials. However, scalable integration of SWNTs into circuits is challenging because of difficulties in controlling the geometries, spatial positions, and electronic properties of individual tubes. We have implemented solutions to some of these challenges to yield radio frequency (RF) SWNT analog electronic devices, such as narrow band amplifiers operating in the VHF frequency band with power gains as high as 14 dB. As a demonstration, we fabricated nanotube transistor radios, in which SWNT devices provide all of the key functions, including resonant antennas, fixed RF amplifiers, RF mixers, and audio amplifiers. These results represent important first steps to practical implementation of SWNTs in high-speed analog circuits. Comparison studies indicate certain performance advantages over silicon and capabilities that complement those in existing compound semiconductor technologies.

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and Si[O.sub.2] with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeterwave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz. Index Terms--Electrostatic discharges (ESDs), fin-shaped fieldeffect transistor (FinFET), mixed analog integrated circuits, nanotechnology.

This paper investigates both theoretical and implementation-level aspects of switching-feedback control strategies for the development of harmonic oscillators. We use sliding-mode compensation based on various norms of the system state to achieve amplitude control over a wide-tuning range. A 7.6-MHz I/Q LC oscillator is developed and tested. Measurements show that implementation of the proposed switch-based amplitude controller provides accurate amplitude control over the entire frequency tuning range while inducing only a minor phase noise degradation (of less than 2 dBc/Hz). Index Terms--Amplitude control, analog circuits, harmonic distortion, nonlinear systems, sliding-mode control, voltage-controlled oscillator (VCO), wide tuning range.

In this brief, the author proposes a novel symbolic analysis method for analog behavioral modeling by Boolean logic operations and graph representation. The exact symbolic analysis problem is formulated as a logic circuit synthesis problem where we build a logic circuit that detects whether or not a given symbolic term is a valid product term from a determinant. The logic circuit is represented by binary decision diagrams (BDDs), which can be trivially transformed into zero-suppressed BDDs (ZBDDs). ZBDDs are essentially determinant decision diagram (DDD) representation of a determinant. The proposed BBD-based method gives the circuit logic interpretation of symbolic terms in a determinant and exploits such logic interpretation during the BDD/DDD construction process. It demonstrates an inherent relationship between symbolic circuit analysis and logic synthesis. It is the first symbolic analysis method that is not based on traditional Laplace expansion or topological methods. Experimental results show the speedup of our new method over the existing flat method and its improved analysis capacity over both existing flat and hierarchical symbolic analyzers. Index Terms--Behavioral modeling, binary decision diagrams (BDDs), determinant decision diagrams (DDDs), simulation, symbolic analysis.

Four new single-input-multi-output-type universal biquad filters using current-feedback operational amplifiers (CFOAs) are presented, which realize all the five standard filter functions (namely, low-pass, bandpass, high-pass, notch, and all-pass) from the same configuration, provide tunability of the various filter parameters in all the five responses, and offer a resistive or ideally infinite input impedance while employing only four CFOAs and two grounded capacitors as preferred for integrated circuit implementation. The workability of the new biquads has been verified by hardware implementations and SPICE simulations based upon AD844-type CFOAs, and some sample results are presented. Index Terms--Analog circuit design, biquad filters, current-feedback operational amplifiers (CFOAs).

A single-ended to differential linear current driver has been designed and implemented in a 0.25 [micro]m CMOS technology. This full-custom cell is intended for analogue data transmission in large-scale High-Energy Physics (HEP) experiments in the future CERN's Large Hadron Collider (LHC). Intrinsic technology radiation tolerance and specific design methodologies qualify this device to operate over 10 years in the LHC high radiation environment. High linearity and low power-overhead are achieved through a local feedback input stage and a current push-poll output stage. Linearity error is less than 0.1% in the specified operating range and 1% in close to full-swing operation. Static, dynamic and noise performance have been proven to be stable after a total ionising dose of 20 Mrad (Si[O.sub.2]) and after accelerated annealing. Index Terms--CMOS analog integrated circuits, current measurement, data acquisition, driver circuits, radiation hardening.

This paper is concerned with the design of an optimal set of analog signals with prescribed magnitude spectrum and quadratic phase structure such that the maximum cross-correlation is minimized. An analytic expression for the maximum cross-correlation between two signals is derived through mathematical analysis. The optimal set of signals with the lowest maximum cross-correlation is explicitly characterized under certain conditions. Index Terms--Analog signal set design, correlation analysis, quadratic phase, minimax optimization, multiuser code-division multiple access (CDMA) communications, spectrum constraint, time-bandwidth product.

A simple and efficient low-voltage two-stage operational amplifier with Class-AB output stage is introduced. It has a large effective output current boosting factor (~50) and close to a factor 2 bandwidth enhancement. This is achieved at the expense of minimum increase in circuit complexity and no additional static power dissipation. Experimental verification of the characteristics of the proposed circuit is provided. Index Terms--Analog integrated circuits, Class-AB amplifiers, low-voltage analog circuits, operational amplifiers.

The trend in data acquisition systems for modern physics experiments is to digitize analog signals closer and closer to the detector. The digitization systems have followed the progress of commercial analog to digital converters. The state of the art for these devices is currently 225 MSample/s for a 10 to 12 bit range. The new boards, described in this paper, have been designed to improve these performances by an order of magnitude. In its simplest version, this board mainly includes 4 channels sampling analog data up to 2 GSample/s with an analog bandwidth of 300 MHz, and digitizing it with a 12-bit dynamic range. It is based on the custom-designed MATACQ chip. The latter's innovative design permits reaching these performances with power consumption smaller than 1 W. The boards are triggerable either by internal or external signals and several boards are easily synchronizable. The board integrates both GPIB and VME interfaces that permit a maximum readout speed of 500 events/s with the whole memory depth of the 4 channels read. Index Terms--Analog memories, analog-to-digital conversion (ADC), application-specific integrated circuits, very-high-speed integrated circuits.

A new accurate modeling technique based on conformal mapping provides SPICE models for edgeless field-effect transistors (FETs) with arbitrary gate geometries for analog radiation-hardness-by-design. Generated models are compared to data measured from FETs with annular and other geometries fabricated on TSMC 0.25 [micro]m and 0.18 [micro]m processes. Currents, output resistances and capacitances all typically agree to within 10% of measured data. Application of the model to alternative gate geometries useful for analog radiation hardened design is explored. Index Terms--Analog integrated circuits, field-effect transistor (FET) integrated circuits, radiation hardening, semiconductor device modeling.

Abstract--Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic [...]

A versatile low-voltage CMOS circuit with a triangular/trapezoidal transconductance characteristic and independently programmable slope (keeping constant height or constant width), height (keeping constant slope or constant width), and horizontal position is presented. Simulation results using Cadence DFW-II that verify the functionality of the circuit with [+ or -] 1.5-V supplies are presented. A chip prototype has been fabricated in a 0.5-[micro]m technology and experimentally verified. The circuit can find application in the implementation of high resolution, high speed folding analog-to-digital converters, in piecewise-linear approximation, and in the implementation of membership functions in analog and mixed-signal neuro-fuzzy systems. Index Terms--Analog integrated circuits, analog processing circuits, analog-to-digital conversion, nonlinear circuits, piecewise-linear (PWL) techniques.

A novel analysis method for analog circuits test and diagnosis is described in this paper. Diagnosis hypotheses are represented and fuzzy math is used to express the diagnosis hypotheses and strategy. Based on it, new equivalent fault model is presented and used for test node selection and design for test. Especially, parametric fault test for linear analog circuits with tolerance analysis is presented using both sensitivity method and fuzzy analysis method. Index Terms--Diagnosis hypothesis, equivalent faults, fault diagnosis, membership function, parametric fault diagnosis, test node selection.

A systematic method for designing log-domain filter structures that simulate the topology of the corresponding passive prototypes is introduced in this paper. This has been achieved by transposing the i - v characteristic equation of each passive element in the linear domain, to the corresponding one in the log domain. The transposition has been done in such a way that, the current that flows through the terminals of the passive element in the linear domain sustains its value in the corresponding log-domain configuration. In this way the linear operation of the whole filter is preserved. With regard to the voltage at each terminal of the passive prototype, this is logarithmically compressed in order to achieve filtering in the log domain. Following the above considerations, the log-domain equivalents of all passive elements of the prototype filter were derived. Having established the equivalents, the procedure for designing high-order log-domain filters is quite facilitated. The validity of the proposed technique is demonstrated through simulation results for a fifth-order elliptic low-pass filter. Index Terms--Analog filters, analog integrated circuits, log-domain filters.

A novel procedure to approximate wavelet bases using analog circuitry is presented. First, an approximation is used to calculate the transfer function of the filter, whose impulse response is the required wavelet. Next, for low-power low-voltage applications, we optimize the state-space description of the filter for dynamic range, sensitivity and sparsity requirements. The filter design that follows is based on an orthonormal ladder structure with log-domain integrators as the main building blocks. Simulations demonstrate that it approximates the required wavelet base (i.e., Morlet) in an excellent way. The circuit operates from a 1.2-V supply voltage and a bias current of 1.2 [micro]A. Index Terms--Analog electronics, log-domain filters, orthonormal ladder filter, wavelet transform (WT).

In this paper, two voltage-mode circuits that implement the pseudo-exponential function using controllable gain blocks are presented. The gain block of the proposed circuits each utilize a current conveyor and an operational amplifier in a novel manner. They offer the advantages that they are precise, easily implemented in integrated circuit (IC) form and can employ a bank of switched resistors, MOS transistors in triode or transconductors to change their gain according to a control parameter x that is determined by a ratio of resistances. Experimental results using discrete IC components confirm the theory and show the circuits having an output range of approximately 22 dB, with an error of less than 1 dB for x greater than--0.55 and less than 0.63. Index Terms--Analog circuits, current feedback amplifier, operational amplifiers.

A novel square-root domain (SRD) second order filter with automatic tuning control is described. The tuning system is based on a master-slave configuration, where the master is a SRD current-mode magnitude locked loop. The control circuitry allows tuning of the cut-off frequency as well as the quality factor and gain of the filter. The basic building blocks of the complete system are implemented employing a design strategy based on the inherent nonlinear characteristic of Class-AB linear transconductors. A proper biasing scheme in such transconductors leads to operation with very low supply voltages (as low as [V.sub.GS] + 2[V.sub.Dssat]). Simulation and numerical results together with measurements from a fabricated prototype in a 0.8-[micro]m CMOS technology are included in order to validate the design technique proposed. Index Terms--Companding, current-mode circuits, on-chip tuning, square-root domain (SRD), tunable analog filters, very low voltage.

An integrator employing the log-domain principle and fabricated in a 0.8-[micro]m CMOS process is presented. It uses floating-gate MOS transistors biased in weak inversion to achieve low-voltage operation and low power consumption. The circuit does not suffer from initial charge trapped in the floating gates, thus not requiring postfabrication charge removal. It can be frequency tuned over more than three decades, from 25 Hz to 35 kHz, and uses a 1.2-V single supply to achieve a dynamic range at 1% THD of 75 dB thanks to its balanced class-AB operation. For cutoff frequencies in the range of 100 Hz, the supply voltage can be reduced down to 1 V. The circuit occupies an active area of 0.1 [mm.sup.2] and dissipates 4.7 [micro]W. The technique employed can be readily extended to high-order filters. Index Terms--Analog CMOS circuits, class AB, continuous-time filters, floating-gate MOS, log-domain.

Low-power analog driver based on a single-stage amplifier with an embedded current-detection slew-rate enhancement (SRE) circuit is presented. By developing a systematic way to design both the response time and optimal sizing of driving transistors in the SRE circuit, the SRE circuit can be controlled to turn on or turn off properly. In addition, the analog driver only dissipates low static power and its transient responses are significantly improved without transient overshoot when driving large capacitive loads. Implemented in a 0.6-[micro]m CMOS process, a current-mirror amplifier with the current-detection SRE circuit has achieved over 43 times improvement in both slew rate and 1% settling time when driving a 470-pF load capacitor. When the proposed analog driver is employed in a 50-mA CMOS low-dropout regulator (LDO), the resultant load transient response of the LDO has 2-fold improvement for the maximum load-current change, while the total quiescent current is only increased by less than 3%. Index Terms--Amplifiers, analog driver, low-dropout regulator (LDO), slew rate, slew-rate enhancement (SRE) circuit, transient responses.

It is well known that in balanced (or differential) circuits, all even harmonics are canceled. This cancellation is achieved by using two paths and exploiting phase differences of 180[degrees] between the paths. The question addressed in this paper is: what distortion products (harmonics and intermodulation products) are canceled if more than two paths (and phases) are used? These circuits are called polyphase multipath circuits. It turns out that the more paths (and phases) are used, the more distortion products are canceled. Unfortunately, some intermodulation products cannot be canceled without also canceling the desired signal. An analysis of the impact of mismatch between the paths shows that the suppression of distortion products will be larger if more paths are used. As an application example, the design of an upconversion mixer with a clean output spectrum is presented. Index Terms--Analog circuits, circuit analysis, distortion cancellation, harmonic rejection, image rejection, multipath, nonlinear circuits, polyphase.

This paper describes the design strategy and implementation of a low-voltage pseudodifferential double-sampled timing-skew-insensitive sample-and-hold (S/H) circuit with low hold pedestal based on the Miller-effect scheme. The S/H circuit employs bootstrapped switches in order to facilitate low voltage operation. The design considerations for each building block are described in detail. The S/H circuit has been designed using a 0.35-[micro]m 2P4M CMOS technology and experimental results are presented. The 1.5-V S/H circuit operates up to a sampling frequency of 50 MHz with less than -54.6 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8 [V.sub.pp]. In these conditions, a differential hold pedestal of less than 0.8 mV, 1.6 ns acquisition time at 0.8-V step input, and 0.8 [V.sub.pp] full-scale differential input range are achieved. Index Terms--CMOS analog integrated circuits, sample-and-hold (S/H) circuits.

A method for predicting the distortion in weakly nonlinear analog circuits is presented, which relies on the classical theory of regular perturbation. Accordingly, a nonlinear circuit is described and analyzed as a perturbation of its linearized model, and the response to a periodic signal is analytically calculated through frequency-domain recurrent formulas. The method is simple and quite straightforward to apply, as it involves the calculation of frequency-domain transfer functions and of Fourier coefficients only, making it easily adaptable to any circuit topology. The method can be a valid alternative to the Volterra series method. A relationship between the proposed method and the Volterra series method is established, showing that they lead to very similar approximants to the solution. The method has been numerically tested in practical circuits wherein the devices are modeled by polynomial and exponential nonlinearities. Index Terms--Analog integrated circuits, nonlinear analysis, nonlinear distortion, perturbation methods, Volterra series, weakly nonlinear circuits.

This paper analyzes and compares CMOS output stages for very low-voltage operational amplifiers. The analysis was carried out by taking into account output stage performance parameters which also affect the characteristics of the overall amplifier. In particular, three quality factors were defined to afford the designer a better understanding of the relationships between current dissipation, area consumption, bandwidth, and linearity. Exploiting these new parameters, four output stages were analyzed in detail and compared. Finally, comparison results were validated by simulations. Index Terms--Analog integrated circuits, CMOS analog circuits, low-voltage, operational amplifiers, output stages.

This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater flexibility. In order to verify the viability of the proposed design step, SPICE simulation results of the opamp designed by the proposed procedure, under a variety of temperature and process conditions, are given. Index Terms--CMOS analog integrated circuits, frequency compensation, operational amplifier, poles and zeroes.

In this paper, simple analog circuits to implement a repetitive control scheme are discussed. The repetitive control has shown to be a useful tool for tracking of periodic reference signals and for compensation of periodic disturbances. The main advantages of the proposed circuitry are: 1) no digital conversion required; 2) easy tuning to the corresponding frequency; and 3) cost effectiveness. A description of the circuits and corresponding experimental frequency responses are given. Index Terms--Delay circuits, harmonic distortion, repetitive control, resonant filters.

Log-domain filters use the large-signal exponential current-voltage relationship of the bipolar junction transistor to convert signals to logarithmic form, where they are processed, and to map them back to the linear domain after processing. Due to their internally nonlinear nature, application of standard linear circuit design techniques to such networks can give rise to unexpected externally nonlinear behavior. Methods of nonlinear dynamics are used here to explain the undesired nonlinearities recently observed in a differential first-order log-domain integrator and to investigate the input/output behavior of the corresponding low-pass filter. The nonlinear behavior of a floating-capacitor differential second-order log-domain bandpass filter is also investigated and explained. Index Terms--Analog circuits, log-domain circuits, nonlinear circuits, nonlinear oscillations, translincar circuits, stability.

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as 'flipped voltage follower (FVF)' have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive fist of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits. Index Terms--Analog circuits, analog integrated circuits, continuous time filters, differential amplifiers, low-power design, low-voltage design.

A new low-voltage CMOS winner-take-all (WTA) circuit is presented. The proposed circuit exhibits a linear increase of complexity with the number of inputs at the rate of only three transistors per input and it is based on a modified version of the common source scheme. In this case, each input follower is enhanced by local shunt feedback to increase its gain and to reduce its output impedance. Simulations demonstrate the potential of the circuit to operate at very high speed, with high precision and with a supply voltage close to a transistor's threshold voltage. Experimental verification of the circuit using a 0.5-[micro]m CMOS technology is also provided. Index Terms--Analog CMOS circuits, winner-take-all (WTA) analog circuits.

Based upon state-space representation, the effects of component mismatch in a complex (or polyphase) Gm-C filter are examined. It was found that the effects of component mismatch in this kind of filter are twofold. The first is that it will distort the filter's frequency response. The second and probably more severe consequence is the crosstalk in which the unwated image signal is leaked into the passband frequencies, interfering with the wanted signal of the selected channel. A simulation method of a polyphase filter is also presented, and simulation results based on Monte Carlo analysis are given. Index Terms--Analog integrated circuits, circuit theory, filter theory, state-space methods, transceivers.

Neurons in the mammalian primary visual cortex are selective along multiple stimulus dimensions, including retinal position, spatial frequency, and orientation. Neurons tuned to different stimulus features but the same retinal position are grouped into retinotopic arrays of hypercolumns. This paper describes a neuromorphic implementation of orientation hypercolumns, which consists of a single silicon retina feeding multiple chips, each of which contains an array of neurons tuned to the same orientation and spatial frequency, but different retinal locations. All chips operate in continuous time, and communicate with each other using spikes transmitted by the address-event representation protocol. This system is modular in the sense that orientation coverage can be increased simply by adding more chips, and expandable in the sense that its output can be used to construct neurons tuned to other stimulus dimensions. We present measured results from the system, demonstrating neuronal selectivity along position, spatial frequency and orientation. We also demonstrate that the system supports recurrent feedback between neurons within one hypercolumn, even though they reside on different chips. The measured results from the system are in excellent concordance with theoretical predictions. Index Terms--Address-event representation (AER), Gabor filter, image processing, mixed analog-digital integrated circuits, neural chips, neuromorphic engineering, visual cortex.

An improved version of an inductor-switching fast-response dc-dc converter is presented that will provide the requirements and features of the new generation of microprocessor and digital systems. Lower output voltage, higher output current, and smaller output voltage ripple requirements have greatly increased the difficulty of the power supply design. To further increase the problem, power-saving 'stop-clock' modes of the microprocessor has demanded faster and more stable transient response from the dc-dc converter. A novel method of inductor switching is applied to a dc-dc converter, and it provides the prominent features of current amplification and absorption during the heavy burden of load transients. The design and simulation of the concept is verified by experiment with a 12-V input and 3.3-V/30-A output converter. Index Terms--Analog circuit, dc-dc power conversion, inductor switching, voltage control.

Analog RF front-end circuits are typically designed to perform one specific task, while key parameters such as dynamic range, bandwidth and selectivity are fixed by the hardware design and not by the communication system in an adaptive way. As a result, today's receiver topologies are designed to function under the most stringent conditions, which increases circuit complexity and power consumption. However, the conditions under which the RF circuits operate are not fixed but vary widely and depend upon a multitude of factors. Therefore, a concept of design for adaptivity is introduced in this paper. It establishes a trajectory for an all-round performance characterization of adaptive oscillators with an explicit qualitative and quantitative description of all the existing relations and tradeoffs among the oscillator performance parameters. As a proof of concept, an 800-MHz adaptive voltage-controlled oscillator is designed with phase-noise tuning range of 7 dB and more than a factor 3 saving in power consumption, suitable for unobtrusive mobile equipment, foreseen to operate in this band. Index Terms--Adaptive circuits, analog circuits, loop gain, low-power integrated circuit (IC) design, phase-noise tuning, RF circuits, voltage-controlled oscillators (VCOs).

This paper describes a novel matched filter (MF) design and its basic operations. The MF is based on the charge-domain operations that have a very simple structure compared to ordinary designs. To investigate the charge transfer characteristics and operations of correlator circuits that compose the MF, prototype designs are made by standard CMOS and fabricated by MOSIS 1.5 u, double overlapping poly, and double metal technology. The power consumption of the fabricated design was 7.0 pJ/Sample/tap. This value should be 1/10 of that of the current state of the art switched capacitor MF design, given that the same process technology was applied to both. Circuit area was 0.151 mm2/tap and this is also 1/2 of that of switched capacitor designs of the same technology. The correlator circuit of the new MF is composed of several steps of charge transfer operations. Hence, no special fabrication process such as those used for CCD imager is required. The detailed structure and operation of the correlator is explained. Index Terms--Charge transfer, CMOS analog integrated circuits, correlators, matched filters (MFs).

Nonlinear distortion in single-, two-, and three-stage operational amplifiers (opamps) is the main scope of this paper. For each opamp, distortion contributions from different groups of transistors are identified and plotted versus frequency. This makes it possible to find the strongest sources of distortion in the various frequency regions. Further, equations that describe the third harmonic as a function of circuit parameters and input frequency are presented. Despite the simplifications, these equations describe the third harmonic accurately. Further, they provide insight and understanding by connecting distortion to circuit parameters such as transconductances, capacitances, poles, and zeros. The comparison of the opamps shows that each opamp has a frequency region where the distortion is lower than for the other two. The three-stage opamp has far lower distortion at low frequencies, the single-stage opamp is better at high frequency and the two-stage opamp is best for the mid frequency range. Index Terms--Analog integrated circuits, feedback amplifiers, harmonic distortion, nonlinear distortion, operational amplifiers.

The computation of local visual motion can be accomplished very efficiently in the focal plane with custom very large-scale integration (VLSI) hardware. Algorithms based on measurement of the spatial and temporal frequency content of the visual motion signal, since they incorporate no thresholding operation, allow highly sensitive responses to low contrast and low-speed visual motion stimuli. We describe analog VLSI implementations of the three most prominent spatio-temporal frequency-based visual motion algorithms, present characterizations of their performance, and compare the advantages of each on an equal basis. This comparison highlights important issues in the design of analog VLSI sensors, including the effects of circuit design on power consumption, the tradeoffs of subthreshold versus above-threshold MOSFET biasing, and methods of layout for focal plane vision processing arrays. The presented sensors are capable of distinguishing the direction of motion of visual stimuli to less than 5% contrast, while consuming as little as 1 [micro] W of electrical power. These visual motion sensors are useful in embedded applications where minimum power consumption, size, and weight are crucial. Index Terms--Analog very large-scale integration (VLSI), biomimetic, spatio-temporal frequency, vision chip.

The physical principles governing ion flow in biological neurons share interesting similarities to electron flow through the channels of MOSFET transistors. Here, is described a circuit which exploits the similarities better than previous approaches to build an elegant circuit with electrical properties similar to real biological neurons. A two-channel model is discussed including sodium ([Na.sup.+]) and potassium (K.sup.+]). The [Na.sup.+] channel uses four transistors and two capacitors. The [K.sup.+] channel uses two transistors and one capacitor. One more capacitor simulates the neuron membrane capacitance yielding a total circuit of four capacitors and six transistors. This circuit operates in real-time, is fabricated on standard CMOS processes, runs in subthreshold, and has a power supply similar to that of real biology. Voltage and current responses of this circuit correspond well with biology in terms of shape, magnitude, and time. Index Terms--Analog circuits, bioelectric potentials, biological cells, nervous system.

A high-performance current feedback amplifier circuit referred to as an operational current feedback amplifier is described in this paper. The technique employed involves the incorporation of the input circuit of the current feedback amplifier in the feedback loop of an operational amplifier to reduce the input impedance at the inverting terminal of the current feedback amplifier. The new circuit possesses the gain accuracy and bandwidth of the current feedback amplifier but realizes significant improvement in bandwidth accuracy and bandwidth gain-independence. Experimentally, using AD844s, an order of magnitude reduction in bandwidth variation with changing gain was achieved in the non-inverting configuration and almost complete bandwidth invariance was realized in the inverting configuration. Index Terms--Analog processing circuits, current feedback amplifier, high-speed integrated circuits, operational amplifier.

A CMOS high-performance current-mode winner-take-all circuit is presented. The circuit employs a novel technique for inhibitory and excitatory feedbacks based on input currents average computation, achieving both high speed and high precision. The circuit is designed for operation with a wide range of input current values, allowing its integration with circuits operating both in subthreshold and in strong inversion regions. Two circuits, each for a different range of input currents, have been implemented in a standard 0.35-[micro]m CMOS process available through MOSIS and are operated via a 3.3-V supply. Their operation is discussed, simulation results are reported and preliminary measurements from a test chip are presented. Index Terms--Analog circuits, analog integrated circuits, CMOS analog integrated circuits, neural networks, winner take all (WTA).

A new circuit configuration uses a single operational transresistance amplifier (OTRA) and four passive elements to realize both first- and second-order allpass filters. Owing to internal grounding of the OTRA input terminals, effects of input parasitics are significantly reduced. Applications of the circuit include the realization of the phase equalizer, the quadrature oscillator, and the high-Q bandpass filter for analog signal processing. The performance of the allpass filter is illustrated by circuit-level simulation of a quadrature oscillator with CMOS realization of the OTRA. Index Terms--Allpass filters, analog integrated circuits, operational transresistance amplifiers (OTRAs).

This brief focuses on the performance analysis of general charge-sampling circuits for signal capture. The theoretical analysis in the brief can be applied not only for weak signal capture, but also for the normal signal sampling. Based on a general charge-sampling model, the transfer function, the noise performance, and the clock jitter tolerance are analyzed and compared to conventional voltage sampling. The results provide a theoretical basis for charge-sampling circuit design. Index Terms--Analog circuits, analog-digital conversion, charge sampling, jitter, sample-and-hold circuits, sampling methods, switched circuits, switched system,.

A new compact CMOS continuous-time analog rank-order filter topology is presented. The hardware complexity grows linearly with the number of inputs at the rate of only two transistors per input. The implementation is based on a multiple input differential structure. The rank is programmable with the tail current source for all rank-order values from the Min to the Max case. The circuit has low voltage and low power consumption requirements. Experimental results are presented that verify the functionality and accuracy of the circuit. Simulation results show satisfactory operation in the 100-MHz frequency range for 0.5-[micro]m CMOS technology and using a single 1.8-V supply. Two buffered versions of the circuit and efficient techniques for reduction of corner errors are also discussed. Index Terms--CMOS analog circuits, low-voltage analog circuits, median filter, minimum circuit, rank-order filter, transconductance comparator, winner-take-all circuit.

In this paper, the possibilities of employing full scalability to on-wafer complementary metal-oxide-semiconductor (CMOS) test fixtures is studied experimentally. Several test fixtures and in-fixture sets were fabricated and measured in order to find the significant parasitic components in shield-based fixtures. An improved method for applying hi-directional scaling to on-wafer shield-based test fixtures is proposed. This method takes into account the parasitic series resistance, series inductance, and parallel capacitance that are present in the test fixture. The proposed method can be used successfully in commonly known deembedding methods. This is verified through measurements. The test fixtures were fabricated on top of a lossy substrate using double-poly, three-metal-layer 0.35-[micro]m CMOS technology. Index Terms--Calibration, complementary metal-oxide-semiconductor (CMOS) analog integrated circuits (ICs), microwave measurements.

Designing a low-jitter clock synthesizer is not a trivial task. Multiple noise and disturbance sources combine together in the nonlinear blocks of the phased-lock loop (PLL) affecting its performance. Moreover, deceptively small circuit nonideal characteristics can have nonnegligible effects in the behavior of the whole system. A behavioral modeling approach allowing a systematic design of the PLL is discussed here. This approach allows the designer to maintain a grasp of the fundamentals using coarse models at the early stage of the design and to eventually gain insight on the lower order effects by gradually increasing the level of detail as the design develops. Moreover, accurate design specifications for the actual circuit blocks are obtained and, eventually the transistor-level results can be back-annotated into the behavioral model for further verification. This methodology is here demonstrated in the context of the modeling, design and the implementation of a fully integrated BiCMOS 1.76 ps rms jitter 180-MHz clock synthesizer. A detailed functional model including the crystal oscillator, the main circuit nonlinearities, and noise sources of the PLL is presented. The building blocks' models development has been motivated by actual circuit implementations. Moreover, computational pitfalls have been identified and solutions have been proposed. Finally, the key behavioral model results have been compared against measured results obtained from an actual fabricated prototype validating the effectiveness of the proposed approach. Index Terms--Analog integrated circuits, BiCMOS analog-integrated circuits, circuit modeling, circuit simulation, frequency synthesizers, integrated-circuit design, integrated-circuit modeling, jitter, nonlinear circuits, ocillator noise, phase jitter, phase-locked loops (PLL), phase noise, voltage-controlled oscillators (VCO).