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This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

The LSOT (low saturation onset transistor) is a four-transistor network that emulates a MOS device with much lower saturation onset voltage by compensating the reverse saturation component of the drain current through its main transistor. Due to current overcompensation in the structure, the DC output characteristic of the equivalent device may present an undesirable hump. This work presents a methodology to properly size the LSOT leading to a smoother characteristic. Moreover, the addition of a simple switch to automatically cut-off an auxiliary branch of the LSOT structure is also proposed, to allow the use of shorter devices without augmenting overall power.

A CMOS current-mode companding integrator for application in continuous time analog filters is presented. It is a modified version of the Proportional Source Transconductances Integrator. The main improvements are increased compactness, larger first-order behavior bandwidth and manual calibration capability. The circuit has been designed in a CMOS 130 nm technology and analyzed through simulation, featuring: −20 dB/decade slope from 7 kHz to 80 MHz, 180 μW-static power and 3rd order intermodulation distortion lower than −40 dB for input sweep of +0.8 μA.

This work presents the training and realization of a CMOS analog two-layer FSR CNN obtained through the extension of an existing one-layer version. A genetic algorithm has been developed for the learning process and has been applied to the determination of templates parameters in a gray-scale image filtering task. Networks implementing first order Butterworth spatial filters have been simulated and the results are compared to its ideal model and FFT computations, allowing to validate the proposed learning process and circuit applicability.

This work aims to provide solutions and perspectives for CMOS analog designers by reducing the time spent in iteratively dimensioning the devices and simulating the circuits. For this purpose, by-hand design methodologies for a few analog cells are proposed employing a MOSFET compact model which has been earlier improved by adding sub-models for some second order effects. A semiempirical sub-model and characterization method is presented for the Early voltage, thus enhancing the set of model equations for hand calculations. The accomplishment of several by-hand design examples and the comparison between simulation results and specifications succeeded in demonstrating the usefulness and advantages of using the improved MOSFET compact model in the proposed methodologies.

This work presents a comparison between three distinct criteria for evaluating distortion of analog multipliers: the two-dimensional integral nonlinear function and the double input total harmonic distortion, both proposed by us, and the conventional single input total harmonic distortion. A methodology is proposed to experimentally determine these figures of merit using DC characterization. Intending to fit a two-variable polynomial to the multiplier DC transfer surface, distortion coefficients are obtained which can be used to assess the total harmonic distortions. Four different topologies of analog multipliers in CMOS technology have been characterized, by simulation or measurement, and the results demonstrate that DC analysis provides meaningful and reliable distortion figures of merit. An experimental analysis over three additional analog multipliers of commercial integrated circuits using DC characterization is also accomplished.

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. The circuit has voltage-mode inputs and a current-mode output and includes a signal application method that avoids voltage or current reference generators. Simulations have been accomplished for a CMOS 130 nm technology, featuring $\pm 50\ \mathrm{mV}$ input voltage range, $60\ \mu\mathrm{W}$ static power and −25 dB maximum THD. The active area is $346\ \mu\mathrm{m}^{2}$ .

In this work a four-transistor network is presented which is almost equivalent to a single transistor with lower saturation onset voltage. Output characteristics are analyzed and the reduction on saturation onset voltage is assessed. This network is adequate to replace output transistors in cascode mirrors, so that the low output conductance is achieved with much less prejudice to output voltage swing.

This work illustrates how to take advantage of the distortion analysis of analog multipliers through DC characterization to establish design and implementation guidelines for the circuit. For this purpose, a CMOS voltage-mode analog multiplier is theoretically analyzed in order to relate the distortion coefficients of its DC transfer surface to the technology parameters and to the geometry of the transistors. The most relevant distortion coefficients are thus discriminated from a set of coefficients obtained from measurement, thus allowing the identification of the most critical circuit parameters that contribute for the distortion level of the analog multiplier.

This work addresses the impact of short-channel effects in the series association of MOS transistors. It has been observed that the simulation results obtained through the use of series association of short transistors in submicron technologies greatly diverge from the obtained through the use of a single device with equal total length. A simple procedure is proposed to circumvent this problem in the design by hand of CMOS analog circuits applying an improved compact MOSFET model to series associations of devices. Simple current sinks and sources are dimensioned and simulated in order to assess the reliability of the design methodology with the improved model.

This work presents a methodology for determining figures of merit to assess distortion in analog multipliers using only DC analysis. Besides the direct determination of two dimensional integral nonlinear function, the distortion coefficients are calculated to fit the DC transfer surface and are used to estimate the total harmonic distortions for single and double input. Simulation and experimental results demonstrate that figures of merit determined either by AC or DC analysis agree with enough reliability.

This paper presents a comparative performance analysis of two learning algorithms developed for the use in Cellular Neural Networks (CNN): the Center of Mass Algorithm, a back-propagation like technique, and an adaptation of the Genetic Algorithm. Both methods are applied for the training of a CNN built with Full Signal Range (FSR) cells, for the implementation of several well-known bipolar functions of image processing. Performance parameters such as total execution time, number of CNN runs and success rate are assessed in order to provide guidelines for the learning method choice.

This work presents a CMOS analog multiplier architecture for application as the synapse in analog cellular neural networks. The circuit comprises two voltage-mode inputs and a current-mode output. Simulated performance features obtained from a circuit design in CMOS 130 nm technology include: +100 mV input voltage range, 23 µW static power, −32 dB maximum total harmonic distortion and −3 dB bandwidth of 51.2 kHz. The active area totalizes only 40 µm2.

In this work, an improved version of the basic structure of a compact MOSFET model and the respective parameters extraction methodology are proposed. The aim of this approach is to increase accuracy in hand calculations for analog circuit design without significantly increasing its complexity. The influences of both inversion level and channel length are considered in the modeling of a few features such as mobility, threshold voltage and onset of saturation. Simple design examples of current sinks and sources are accomplished to compare the basic and the improved models.

In this work, the methodology for the extraction of threshold voltage and specific current of a compact MOSFET model is extended in order to incorporate second order effects such as mobility degradation and threshold voltage dependence on channel length. As the original method, the proposed one is based on transconductance-to-current ratio characteristics and gives rise to a more accurate semi-empirical model, yet simple enough for hand calculations.

This work presents a theoretical comparison between three distinct criteria for evaluating distortion of analog multipliers: the two dimensional integral nonlinear function and the double input total harmonic distortion, both proposed by us, and the conventional single input total harmonic distortion. DC measurements have been accomplished over commercially available devices in order to identify difficulties and advantages implied in the methodology for determining the two dimensional integral nonlinear function.

A compact low-power CMOS analog circuit implementation of a Cellular Neural Network which uses continuously programmable weight values has been presented recently. Now the operation of this full signal range CNN in image filtering is verified through simulation. A learning tool comprising a friendly graphical interface and the center of mass learning algorithm has been developed, which made it possible to determine optimal coefficients for CNN application in image filtering. Circuit simulations of low-pass and high-pass filters have been accomplished with satisfactory results.

Texto completo: acesso restrito. p.1510-1519 Submitted by Suelen Reis (suelen_suzane@hotmail.com) on 2013-01-25T12:13:00Z No. of bitstreams: 1 Cunha.pdf: 289468 bytes, checksum: d553ef47764ff7358568970f4f62f210 (MD5) Made available in DSpace on 2013-01-25T12:13:00Z (GMT). No. of bitstreams: 1 Cunha.pdf: 289468 bytes, checksum: d553ef47764ff7358568970f4f62f210 (MD5) Previous issue date: 1998-10 This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model.

This work presents a new architecture of analog four-quadrant multiplier in CMOS technology based on the behavior of MOSFET in the linear region from weak to strong inversion. The proposed multiplier has voltage and current inputs and a current output, thus being adequate for the implementation of compact synapses in analog Cellular Neural Network (CNN). Simulation results exhibit low power consumption and low distortion.

A compact low-power CMOS analog circuit implementation of a Cellular Neural Network based on Full Signal Range Model (FSR-CNN) is presented. The required operations in cell definition are synapses (multiplication and summation) and saturated integration. In each synapse, a new multiplier architecture is employed with voltage and current inputs and a current output, which allows sharing building blocks and using continuously programmable weight values. Feasibility and usefulness of the proposed FSR cell architecture is verified through the simulation of two applications: the connected component detector and the border extractor.

This paper presents an application of the Interior-Point method of optimization to the design of a CMOS analog integrated circuit. We have chosen the minimum voltage log-domain Seevinck's integrator, where devices operate in weak inversion, so that model equations, required bias conditions and circuit architecture lead to nonposynomial general equations and restrictions that are represented by nonconvex functions. The optimization problem is formulated and the MATLAB optimization toolbox is used to find transistor dimensions and biasing currents. Circuit simulation is performed with these results.

This work presents a compact new architecture of analog companding integrator for application in CMOS current-mode filters. Since MOS transistors are not constrained to operate in the weak inversion region, as in the log-domain counterparts, an improvement in frequency response and in signal-to-distortion ratio is verified.

This paper presents a new processor architecture for high performance computing of fixed-point feedforward multi layered perceptron neural networks. The number of layers, the number of neurons in each layer, the weight values and the activation function look-up table are configurable parameters so that this system can be used for several neural network models. Low latency and high throughput are achieved by means of a massive parallel hardware that separates required arithmetical operations among many multiply-accumulate units (MAC) and adopts a dual core structure to alternate on data sets processing. In order to access weight values from MACs, dual port RAM modules and a special memory organization have been used, allowing simultaneous reading from both cores and decreasing the connection wiring. This neuroprocessor has been designed for ASIC implementation using CMOS 90 nm technology and standard cell methodology. A performance comparison between the proposed architecture and some commercial neuroprocessors has been made.

This work presents an adaptation to the definition of the Integral Nonlinear Function (INLF) for distortion analysis of analog multipliers. Up to this time distortion in two-input multipliers has been evaluated by applying a constant signal to one of the inputs and verifying the linearity of the response with respect to the other input. This method however proves to be ineffective for assuring undistorted multiplying operation. Moreover, the conventional procedures, involving noisy and extensive AC measurements or FFT computation, are time-consuming and cumbersome, particularly if both multiplier input signals are taken into account simultaneously. Current-mode CMOS analog multiplier designs are simulated and analyzed concerning distortion by means of the proposed figure of merit (2D-INFL) and through a conventional procedure.

This work presents a methodology for the design of Seevinck's CMOS log-domain integrators. Since companding circuits in general and log-domain circuits in particular impose many restrictions concerning the correct operating point of transistors and the perfect cancellation of nonlinearities, their dimensioning is not simple. In order not to such a difficulty become a drawback against the achievable low power consumption and high signal-to-noise(distortion) ratio, if compared to conventional small-signal circuits, a careful design methodology is required.

In this paper we propose a four-quadrant multiplier based on a core cell that exploits the relationship between the saturation current of an MOS transistor and the source transconductance. The advantages of the proposed topology are simplicity and feasibility of low-power and low-voltage operation. Experimental results in a 0.35 mum CMOS prototype indicate 1 mA consumption for 1 MHz bandwidth, and distortion level below 1% for an input current equal to 80% of the full scale range. The multiplier area is around 10,000 mum2.

Most of the new generation compact models for the MOSFET have many commonalities since they are based on the same main approximations: gradual channel, charge-sheet, and depletion charge linearization. In this study we show that if we include some additional physics-consistent conditions for the MOSFET equations we obtain a very compact model that we call the advanced compact MOSFET (ACM) model. The core ACM model, design-oriented equations, parameter extraction, and a design example are presented.

This work presents a new architecture of companding integrator for application in CMOS current-mode filters. Since MOS transistors can operate in the whole inversion region, this circuit can be classified either as log-domain or as square-root domain. Due to the higher bias currents allowed, signal-to-noise(distortion) ratio is improved in comparison to the log-domain counterparts. Circuit complexity is intermediate between log-domain and square-root domain companding integrators.

This work presents an automatic sizing tool for optimal design of CMOS OTA, where the formulation is based on the Advanced Compact MOSFET (ACM) model. Several design examples prove that the methodology is reliable, provides useful guidelines, exploits the entire design space and is also adequate for small load capacitances.

This work presents a methodology for optimal design of CMOS OTA, through an automatic sizing tool, where the entire formulation is based on the Advanced Compact MOSFET (ACM) model. Since this model describes the device behavior in the whole inversion regime of operation, the proposed methodology provides more reliable prediction of circuit performance and allows optimization in a much more extended design space.

This paper presents a physically based model for the MOS transistors suitable for design and simulation of integrated circuits. The static and dynamic characteristics of the MOSFET are accurately described by single-piece functions of the inversion charge densities at source and drain. A new compact and physical approach to short-channel effects is presented. We have run some tests to compare the performances of our model and widely used MOSFET models.

This paper presents a physically based model of the MOSFET output conductance. The drain current and the output conductance of the MOS transistor are accurately described by single-piece functions of the inversion charge densities at source and drain. Carrier velocity saturation, channel length modulation (CLM) and drain induced barrier lowering (DIBL) are included in a single-piece analytical model. The results can be readily applied for first order analog circuit hand calculation.

This paper presents a design methodology for MOS amplifiers based on a universal model of the MOSFET, valid from weak to strong inversion. A set of very simple expressions allows quick design by hand as well as an evaluation of the design in terms of power consumption and silicon real estate. The design and integration of a common-source amplifier illustrate the appropriateness of the proposed methodology.

This paper presents a physics-based model for the MOS transistor, suitable for circuit design and simulation and valid from weak to strong inversion. Each static or dynamic characteristic is accurately described by a single-piece function of two saturation currents.

This paper presents an explicit analytical model of the MOS transistor valid in all regions of operation weak, moderate and strong inversion. The proposed model, physically derived, uses the inversion charge density as the key variable and is very simple to be incorporated in CAD programs. Moreover, our model contains only the classical parameters of the MOSFET theory. The inclusion of our model in SABER has led to simulation results which agree very closely with experiments.

This paper introduces the advanced compact MOSFET (ACM) model, a physically based model of the MOS transistor, derived from the long-channel transistor model presented by Cunha et al. (1998). The ACM model is composed of very simple expressions, is valid for any inversion level, conserves charge and preserves the source-drain symmetry of the transistor. Short-channel effects are included using a compact and physical approach. The performance of the ACM model in benchmark tests demonstrates its suitability for circuit simulation.

The aim of this paper is to provide some guidelines on the design of MOS V-I converters. An explicit formula for the harmonic distortion based on an analytic model of the MOSFET has been derived for any inversion level. Experimental results for the distortion in the MOSFET V-I characteristics as well as biasing and tuning strategies applied to MOSFET-C filters are presented.