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Modern digital systems require one or more frequency shaping modules that realize certain transfer functions, usually in the form of digital filters. Breaking up the design into multiple stages results in reducing the implementation area and power consumption. However, there is no well-defined automation methodology to design an optimum multistage multirate filter. This article proposes a new design flow automation tool using a hybrid sampling strategy-based differential evolution (HSS-DE). The user specifies the inputs and outputs of the system, including the input spectrum, the sample rate change, the magnitude and phase responses, and the required signal-to-noise ratio. The tool uses this information to generate a solution indicating the number of stages and the filters’ specifications for each stage such that the generated architecture satisfies the user requirements. We compared the proposed tool to subsystems designed by experts in the ASIC industry. Several case studies are presented to demonstrate the proposed tool’s efficiency in different design problems. The case studies include decimation filters for sigma–delta ( $\Sigma \Delta $ ) analog-to-digital converters (ADCs) and interpolation filters for wideband transmitters such as wideband code division multiple access (WCDMA). The case studies’ results indicate that the proposed design automation flow reduces the design time remarkably, in addition to reducing the implementation in all cases.

With the skyrocketing advances of process technology, the increased need to process huge amount of data, and the pivotal need for power efficiency, the usage of Graphics Processing Units (GPUs) for General Purpose Computing becomes a trend and natural. GPUs have high computational power and excellent performance per watt, for data parallel applications, relative to traditional multicore processors. GPUs appear as discrete or embedded with Central Processing Units (CPUs), leading to a scheme of heterogeneous computing. Heterogeneous computing brings as many challenges as it brings opportunities. To get the most of such systems, we need to guarantee high GPU utilization, deal with irregular control flow of some workloads, and struggle with far-friendly-programming models. The aim of this paper is to provide a survey about GPUs from two perspectives: (1) architectural advances to improve performance and programmability and (2) advances to enhance CPU–GPU integration in heterogeneous systems. This will help researchers see the opportunities and challenges of using GPUs for general purpose computing, especially in the era of big data and the continuous need of high-performance computing.

Recent technology trends to miniaturize spectrometers have opened the doors for mass production of spectrometers and for new applications that were not possible before and where the spectrometer can possibly be used as a ubiquitous spectral sensor. However, with the miniaturization from large reliable bench-top to chip-size miniaturized spectrometers and with the associated mass production, new issues have to be addressed such as spectrometers unit-to-unit variations, variations due to changing the measurement setup and variations due to changing the measurement medium. The unit-to-unit variations of the sensors usually result from changing mode of operation, aging, and production tolerances. The aim of this work is to study the issues emerging from the use of miniaturized Fourier Transform Near-Infrared (FT-NIR) spectral sensors and evaluate the influence of these issues on the multivariate classification model used in many applications. In this work, we also introduce a technique to transfer a classification model from a reference calibration sensor to other target sensors to help reducing the effect of the variations and to alleviate the degradation that occurs in the classification results. To validate the effectiveness of the model transfer technique, we developed a Gaussian Process Classification (GPC) model and Soft Independent Modeling Class Analogy (SIMCA) model both using spectral data measured from ultra-high temperature (UHT) pasteurized milk with different levels of fat content. The models aim to classify milk samples according to the percentage of their fat content. Three different experiments were conducted on the models to mimic each type of variations and to test how far they affect the models’ accuracy once the transfer technique is applied. Initially, we achieved perfect discrimination between milk classes with 100% classification accuracy. The largest retardation in accuracy appeared while changing the measuring medium reaching 45.4% in one of the cases. However, the proposed calibration transfer technique showed a significant enhancement in most of the cases and standardized the accuracy of all retarded cases to get the accuracy back to over 90%.

Typical modern HW designs include many blocks associated with thousands of design properties. Having today's commercial formal verifiers utilize a complementary set of state-of-art formal algorithms is a key in enabling the formal verification tools to successfully cope with verification problems of different sizes, types, and complexities. Formal engines orchestration is the methodology used to pick the most appropriate formal engine for a specific verification problem. It assures proper scheduling of the formal engines to minimize the time consumed to solve individual design verification problems, hence highly impacts the time required to verify the overall design properties. This work proposes the utilization of supervised machine learning classification techniques to guide the orchestration step by predicting the formal engines that should be assigned to a design property. Up to 16,500 formal verification runs on RTL designs and their properties are used to train the classifier to create a prediction model. The classifier assigns any new verification problem to an appropriate list of formal engines associated with a probability distribution over the set of engines classes. Our results indicate how the proposed model is able to improve the formal suite total run-time by up to 59% of its maximum allowable time improvement using multi-classification-based orchestration and to nominate with 88% accuracy the appropriate formal engines for new-to-verify HW designs.

Modern graphical processing units (GPUs) are equipped with general-purpose L1 and L2 caches to reduce the memory bandwidth demand and improve the performance of some irregular general-purpose GPU (GPGPU) applications. However, due to the massive multithreading, GPGPU caches suffer from severe resource contention and low data-sharing which may lead to performance degradation instead. This paper proposes a low-cost streaming-aware conflict-avoiding thrashing-resistant (SACAT) GPGPU cache management scheme that efficiently utilizes the GPGPU cache resources and addresses all the problems associated with GPGPU caches. The proposed scheme employs three orthogonal techniques. First, it dynamically detects and bypasses streaming applications at fine granularity. Second, a dynamic warp throttling via cores sampling (DWT-CS) is proposed to alleviate cache thrashing. DWT-CS runs an exhaustive search over cores to find the best number of warps that achieves the highest performance. Third, it employs pseudo random interleaving cache (PRIC), which is an improved cache indexing function based on polynomial modulus mapping, to mitigate associativity stalls and eliminate conflict misses. Experimental results demonstrate that the proposed scheme achieves a 1.87 $\times$ and a 1.5 $\times$ performance improvement over the cache-conscious wavefront scheduler (CCWS) and the memory request prioritization buffer (MRPB), respectively.

In this paper, we present an IoT application targeting food quality. We utilize the spectrometer as a ubiquitous sensor to provide a Near-infrared (NIR) spectrum that can be used to develop regression models targeting milk quality. We solve a regression problem for different milk components such as Fat, Protein, Lactose, and Solids-Non-Fat. We apply a variety of comparative configurations of regression models, pre-processing techniques, wavelength selection, and feature extraction methods. Our study shows that for the milk data, non-linear models (GPR and SVR) are better choices when compared to linear models.

Indoor positioning is needed in many localization applications such as navigation, autonomous robotic movement, and asset tracking. In this paper, an indoor localization method based on fusion of WiFi RSSI positioning and inertial navigation system (INS) is proposed. Using WiFi positioning only is affected by the indoor communications environment that distort the RSSI signals, also using INS standalone solution has very degraded long-term performance, a Kalman filter (KF) is adopted in this paper to fuse and filter the RSSI signals with the INS data to have more accurate positioning results with average distance error of 0.6m.

The aim of this paper is to study the unit-to-unit variations in miniaturized Fourier Transform Near-InfraRed (FT-NIR) spectral sensors and the effects of these variations on a classification model developed on a single reference calibration sensor. The paper introduces a simple technique to transfer a classification model from the reference calibration sensor to any other target sensor taking into account variations that might occur. The unit-to-unit variations of the sensors usually result from changes in the signal to noise ratio (SNR) of the sensor due to changes in the mode of operation, variations due to aging, variations due to production tolerances, or changes that occur due to the setup and usage scenario such as scanning through a different medium. To prove the effectiveness of the model transfer technique, we use a Gaussian process classification (GPC) model developed using spectral data from ultra-high temperature (UHT) pasteurized milk with different levels of fat content. The model aims to classify the milk samples based on their fat content. After the model is developed, three experiments are held to mimic each type of the variations and to test how far this will influence the GPC model accuracy after applying the transfer technique.

Genetic algorithms is used as a wrapper feature selection technique in many research studies. In this paper we investigate GA capabilities in selecting the best set of time-series features for human activity recognition application. We propose a hybrid GA-PCA approach, where GA is used to select a subset of N features from 561 features, then PCA is used to reduce the subset into M orthogonal features. Experimental results show the ability of GA to eliminate low performance features without affecting the classification accuracy.

Visual odometry (VO) is gaining a huge popularity in many disciplines and applications. All the way from smart driving, robotics, surveillance, search and rescue missions, among many others. This is due to the availability of high-performance inexpensive cameras and the revolutionary advances in the accuracy and precision of different VO algorithms. One of the main issues designers of such algorithms confront is the tuning of different systems' parameters as well as the testing and evaluation of their algorithms across a wide range of configurations. In this paper, a brief overview of different efforts exerted to solve this problem is given. This is followed by a detailed discussion of the need to design a generic extendable framework and a simulator for VO engines that take different design considerations into account. Consequently, the paper proposes a framework for testing, evaluating, and simulating conventional monocular VO engines in order to solve the two previously mentioned problems. The paper also discusses briefly different available options for extending the functionality of this framework to cover a wider range of VO engines and algorithms.

This work proposes the application of clustering machine learning to simplify functional coverage analysis. It introduces a two-round clustering algorithm to group the functional coverage goals that share similar cover items. In the first round, the associations between cover-crosses are encoded as a binary connectivity matrix. K-Means with Jaccard similarity is used to group highly correlated cover-crosses. In the second round, coverage ratio is used as the main measure to sub-group the clusters resulted from the first round. The resulted clusters are then analyzed to identify which cover-crosses mostly contribute to low coverage clusters. Dropping the number of cover-crosses to analyze into a limited number of representative buckets that can further be used by advanced analysis engines to help reach coverage closure faster.

In this paper we present an approach for measuring the hardness of SMT problems.We present the required features, the statistical hardness model used and the machinelearning technique which we used. We apply our method to estimate the hardness ofproblems in Quantier Free Bit Vector (QFBV) theory and we used four of the contestingsolvers in SMT2011 to demonstrate our technique. We have qualitatively expanded somepropositional SAT features existing in the literature to directly work on general SMTproblem instances without preprocessing. The results show that our work is a promisingproof of concept.

Full-system FPGA prototyping is now being widely used in the industry for System-on-Chip (SoC) verification. Prototyping platforms run tests in a fraction of time compared to traditional simulation based verification. However, unlike simulation, they do not provide a good visibility about the Design under Verification (DUV) or its achieved verification results. Coverage is the standard measure of validation effectiveness and is extensively used pre-silicon. But it is very challengeable to analyze coverage data in post-silicon validation. This usually requires the addition of extra logic to the silicon as coverage monitors, which are costly in terms of area, power and timing. In this paper, we propose a framework for coverage data construction from the HW design trace buffer values during silicon execution. Our approach avoids the addition of extra synthesized coverage monitors logic. Additionally, it overcomes the challenge of processing huge traces result from the execution of tests that are impossibly expensive to run in pre-silicon simulation. Our work applies state-of-the-art big data techniques to reduce the processing and coverage data construction overhead. Our results indicate how the proposed framework managed to extract coverage data from FPGA prototyping runs that matches the one generated from the pre-silicon verification results for new-to-verify HW designs.

Biochemical networks depict the chemical interactions that take place among elements of living cells. They aim to elucidate how cellular behavior and functional properties of the cell emerge from the relationships between its components, i.e. molecules. Biochemical networks are largely characterized by dynamic behavior, and exhibit high degrees of complexity. Hence, the interest in such networks is growing and they have been the target of several recent modeling efforts. Signal transduction pathways (STPs) constitute a class of biochemical networks that receive, process, and respond to stimuli from the environment, as well as stimuli that are internal to the organism. An STP consists of a chain of intracellular signaling processes that ultimately result in generating different cellular responses. This primer presents the methodologies used for the modeling and simulation of biochemical networks, illustrated for STPs. These methodologies range from qualitative to quantitative, and include structural as well as dynamic analysis techniques. We describe the different methodologies, outline their underlying assumptions, and provide an assessment of their advantages and disadvantages. Moreover, publicly and/or commercially available implementations of these methodologies are listed as appropriate. In particular, this primer aims to provide a clear introduction and comprehensive coverage of biochemical modeling and simulation methodologies for the non-expert, with specific focus on relevant literature of STPs.

We analyzed the delay failure induced in standard-cell ASICs by total-ionizing dose. We developed a novel cell-level fault model for delay failures. We used this fault model to identify worst-case test vectors (WCTV) for delay failures induced in ASIC devices exposed to total ionizing dose. The fault model was experimentally validated using SPICE simulation and total dose data. We introduced a fast search algorithm based on directed graph and genetic algorithms to help identify WCTV for large ASICs within reasonable search time. The methodology was validated using ASIC test chip and Cobalt 60 facility.

Formal Verification is a computationally expensive step in the verification of today's complex hardware designs. Effective results can be obtained from formal runs by planning ahead the effort and cost that are required for them. Additionally estimating in-advance the expected formal's complexity promotes a lot of potential tricks and clever setup techniques to overcome the initial push-button capacity limitation of the formal verifies and improve their capabilities to handle designs with higher complexity. This paper illustrates the application of regression machine learning (ML) techniques to build an estimation model for the cost of formal verification. Up to 10,000 formal verification runs on RTL designs with good varieties of design/properties attributes are used to learn the relationship between HW designs and the final formal cost in terms of formal run time. We demonstrate the use of Ridge-Regression to decide on the bias-variance trade-off during the regression-model design step as well as the application of Lasso-Regression for the feature selection phase. Finally a comparison between the proposed multiple linear regression approach and another non-parametric K-nearest neighbors kernel based regression technique is done to conclude on the presented work. Our results indicate how the proposed model managed to estimate with reasonable error ratio the expected formal verification effort for new-to-verify HW designs.

We introduce a novel methodology for identifying worst-case test vectors for sequential circuits in ASIC devices exposed to total dose. Testing of sequential circuits requires the use of sequence of test vectors. Those test vectors were generated using cell-level fault models for failures induced by total dose. In this paper we focused on three types of failures: logic, leakage current, and delay failures. A novel cell-level fault model for delay failures induced by total dose is introduced in this paper. This methodology was validated using SPICE simulation as well as experimental results.

We developed a cell-level fault model for logic failure induced in standard-cell ASIC devices exposed to total ionizing dose. This fault model is valid for CMOS process technologies that exhibit field-oxide leakage current under total dose. The fault model was represented at the cell level using hardware descriptive languages (HDL) such as VHDL or Verilog which consequently allowed for cell-level simulation of ASIC devices under total dose using functional simulation tools normally used within the HDL design flow of ASIC devices. We then developed a methodology to identify worst-case test vectors (WCTV) using commercially available automatic test pattern generation (ATPG) tools targeting the developed fault model. Finally, we experimentally validated the significance of using WCTV in total-dose testing of CMOS ASIC devices.

In this paper, we investigate the time and frequency synchronization algorithms as well as, the sector and cell search for the 3GPP Long Term Evolution (LTE) downlink. The proposed algorithms rely on the synchronization and cell-specific reference signals and are, hence, compliant to most recent 3GPP specifications. Time and fractional frequency offset coarse synchronization are performed in the time domain using the cyclic prefix based auto-correlation, while the sector and cell search as well as the integer frequency offset are estimated in the frequency domain using the primary and secondary synchronization signals. All algorithms are evaluated under multipath channel conditions and an initial carrier frequency mismatch. Trading off high performance with reasonable implementation complexity, the algorithms are realized in hardware using a total logic area of 125,460 um2 in 0.13 um technology.

Recent GPUs are equipped with general-purpose L1 and L2 caches in an attempt to reduce memory bandwidth demand and improve the performance of some irregular GPGPU applications. However, due to the massive multithreading, GPGPU caches suffer from severe resource contention and low data-sharing which may degrade the performance instead. In this work, we propose three techniques to efficiently utilize and improve the performance of GPGPU caches. The first technique aims to dynamically detect and bypass memory accesses that show streaming behavior. In the second technique, we propose dynamic warp throttling via cores sampling (DWT-CS) to alleviate cache thrashing by throttling the number of active warps per core. DWT-CS monitors the MPKI at L1, when it exceeds a specific threshold, all GPU cores are sampled with different number of active warps to find the optimal number of warps that mitigates thrashing and achieves the highest performance. Our proposed third technique addresses the problem of GPU cache associativity since many GPGPU applications suffer from severe associativity stalls and conflict misses. Prior work proposed cache bypassing on associativity stalls. In this work, instead of bypassing, we employ a better cache indexing function, Pseudo Random Interleaving Cache (PRIC), that is based on polynomial modulus mapping, in order to fairly and evenly distribute memory accesses over cache sets. The proposed techniques improve the average performance of streaming and contention applications by 1.2X and 2.3X respectively. Compared to prior work, it achieves 1.7X and 1.5X performance improvement over Cache-Conscious Wavefront Scheduler and Memory Request Prioritization Buffer respectively.

System-level design of packet switching fabrics focuses on performance metrics and rarely considers the physical requirements that are usually addressed later at the circuit-level. However, low-power dissipation has become a major requirement in such fabrics dictated by the requirements of emerging applications and by the recent advances in fabrication and VLSI technologies. This paper proposes a framework for system-level design of packet switching fabrics that integrates performance specifications along with physical requirements and constraints. Moreover, realistic traffic models are used to derive the transition activity and the packet arrival and departure events needed for power estimation. Physical requirements are defined by an architectural model for power dissipation based on the stochastic traffic model, models for silicon area, chip count, and input-output pins, which provide a complete system-level specification of the fabric. Performance constraints are also derived from the stochastic traffic model. This framework formulates and solves the power optimization problem subject to those physical and performance constraints as an integer nonlinear optimization problem. The results obtained emphasize the importance of traffic-driven system-level optimization and show the efficiency of this framework as a system-level design space exploration tool.

The rise of Chip-Multiprocessors (CMPs) as a promising trend for the state of the art high-performance processors design raised the need for a scalable cache directory organization along with a simple cache coherence protocol as a hot research area. While thousands of cores are expected to fit on a single chip soon, the previously proposed cache directory schemes still lacks the scalability to accommodate more than tens of cores. The inefficiencies of these directory schemes come in the form of unaffordable memory overhead, excessive coherence traffic leading to performance degradation due to inexact representation of sharers and very complex coherence protocols. In this paper we introduce a new cache directory scheme for many core CMPs. The proposed scheme acquires, and actually improves, the scalability and low coherence traffic of cache-based linked list directory schemes while avoiding its completely sequential operation by exploiting the parallel operation of limited pointer directory schemes. We compare the proposed organization with these two previously proposed ones on different CMP configurations starting with a 4-core CMP and ending with a 32-core CMP. We show that the proposed scheme can avoid one third of the excessive broadcasted invalidation messages and two thirds of the extraneous acks in case of directory pointer overflows in limited pointer schemes. On the other hand, the proposed scheme achieves around 10% better performance than that of the completely sequential cache-based linked list directory while reducing the number of invalidation messages per invalidation event by 24%.

Timing verification is an essential process in nanometer design. Therefore, static timing analysis (STA) is currently the main aspect of performance verification. Traditional STA is based on lookup tables with input slew and output load capacitance. It is becoming insufficient to accurately characterize many significant aspects of the conventional cell delays models, such as: the process variations, nonlinear waveforms, nonlinear loads, and multiple inputs switching (MIS). Therefore, the current trend in modern designs is to use current source based models (CSM), which model MOSFETs as a transconductance. This paper proposes a CSM for combinational logic cells which can accommodate single input switching (SIS) signals. It can also handle where small capacitances are connected at the gate output, while fast ramp signals are applied to the gate input. When compared with ELDO, the proposed model produces more accurate stage delay than that obtained from the standard cell lookup tables.

Moore's law still offers more transistors to fit per die unit area and this leads to the expectation of having thousands of cores fit on a single chip soon. Thus, Network-on-Chip proved to be a successful approach to accommodate this increasing number of cores on chip. However, the previously proposed 2D architectures still lack the scalability to more than few tens of cores where the inefficiencies of those architectures come in the form of long interconnect delays leading to performance degradation and high power consumption due to long wires. Fortunately, the rapid advances in 3D die-stacking technology as a promising trend for the state of the art high-performance processor designs raised the possibilities of having new approaches towards a scalable interconnection network. Thus, in this paper, we propose a novel 3D crossbar-based architecture that separates cores from cache modules in different 3D stacked dies.We introduce area model of the adopted crossbar and analyze the scalability of the proposed architecture up to 1024 communicating entities; cores and L2 cache banks.

As the usage of very large scale integration (VLSI) in computers continues to increase, debugging of timing problems on actual hardware becomes more and more difficult. The post-layout gate-level simulation constitutes a critical design step for timing closure. The major drawback of traditional post-layout gate-level simulation is its long analysis time, which increases as design complexity increases. An alternative method is static timing analysis (STA), which can reduce analysis time. Going deeper through the nanometer technology, new STA techniques have to be present to provide more accurate results for cell delay models characterization. New STA techniques now go for current source based models (CSM) which are based on modeling MOSFETs as trans-conductance. In this paper, a SW engine is presented and used to perform a comparison on accuracy and speed between the default STA technique based on library lookup tables (LUT) and a proposed CSM-based technique for combinational logic cells. Moreover, an adaptive technique, which is based on utilizing both the LUT and CSM methods, is presented. The adaptive technique uses the method with the more accurate delay results when solving for circuits combined of NAND2X0, NOR2X0 and INVX0 standard cells. Also, provides the calculation for some metrics like (arrival time and slack delay values at each node in the combinational circuit).

We develop a methodology for identifying worst-case test vectors necessary to detect leakage current failures in standard-cell based ASIC devices exposed to a total ionizing dose. We developed a novel search methodology based on the Particle Swarm Optimization technique.

To continue scaling the circuit features down, Double Patterning (DP) technology is needed in 22nm technologies and lower. DP requires decomposing the layout features into two masks for pitch relaxation, such that the spacing between any two features on each mask is greater than the minimum allowed mask spacing. The relaxed pitches of each mask are then processed on two separate exposure steps. In many cases, post-layout decomposition fails to decompose the layout into two masks due to the presence of conflicts. Post-layout decomposition of a standard cells block can result in native conflicts inside the cells (internal conflict), or native conflicts on the boundary between two cells (boundary conflict). Resolving native conflicts requires a redesign and/or multiple iterations for the placement and routing phases to get a clean decomposition. Therefore, DP compliance must be considered in earlier phases, before getting the final placed cell block. The main focus of this paper is generating a library of decomposed standard cells to be used in a DP-aware placer. This library should contain all possible decompositions for each standard cell, i.e., these decompositions consider all possible combinations of boundary conditions. However, the large number of combinations of boundary conditions for each standard cell will significantly increase the processing time and effort required to obtain all possible decompositions. Therefore, an efficient methodology is required to reduce this large number of combinations. In this paper, three different reduction methodologies are proposed to reduce the number of different combinations processed to get the decomposed library. Experimental results show a significant reduction in the number of combinations and decompositions needed for the library processing. To generate and verify the proposed flow and methodologies, a prototype for a placement-aware DP-ready cell-library is developed with an optimized number of cell views.

Double Patterning (DP) is still the most viable lithography option for sub-22nm nodes. The two main types of DP are Litho Etch Litho Etch (LELE) and Self-Aligned Double Patterning (SADP). Of those two, SADP has the advantage of lower sensitivity to overlay error. However SADP imposes a lot of restrictions on the layout. One of the ways to do SADP decomposition is to use an LELE decomposer while prohibiting stitches, and to generate mandrel and trim masks from LELE masks using some Boolean characterization equations. In this paper, we propose an SADP decomposer based on an LELE decomposer that is used to decide which target polygons are mandrel and which are non-mandrel. However the core of the LELE decomposer has been made SADP-aware, such that it gives less priority to pairs of polygons separated by spacing values that are prohibited by SADP. Then, a mandrel and trim masks generator uses the LELE decomposer output and produces the final mandrel and trim masks. Experimental results show that adding SADPawareness to the core of the decomposer has decreased the average number of coloring conflicts by 38%. The proposed decomposer is faster than the previous SADP decomposition approaches that use Integer Linear Programming (ILP) and Satisfiability (SAT).

An interface for MEMS gyroscope is implemented in 0.18µm HVCMOS technology, and achieves a low noise floor of 1m°/sec/√Hz over 200Hz BW. Electromechanical ΣΔ force-feedback and self-clocking scheme based on gyro resonance are implemented. The interface includes on-chip reference generation, decimation, and temperature compensation.

We introduce a novel methodology for identifying worst-case test vectors for sequential circuits in ASIC devices exposed to total dose. Testing of sequential circuits requires the use of sequence of test vectors. Those test vectors we generated using cell-level fault models for failures induced by total dose. In this paper we focused on three types of failures: logic, leakage current, and delay failures. A novel cell-level fault model for delay failures induced by total dose is introduced in this paper. This methodology was validated using SPICE simulation as well as experimental results.