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Design of a CMOS 18th-order IF (intermediate frequency) bandpass filter for integrated low-IF Bluetooth receivers is presented. The centre frequency and bandwidth of the filter are 3 and 1 MHz, respectively. The proposed filter is based on unity gain fully differential voltage buffers and provides efficient, low power and a small area design solution. The filter, including its automatic tuning circuit, occupies an area of 0.6 mm(2) in a standard 0.5 mu m-CMOS chip. Experimental results show that the filter satisfies the selectivity and dynamic range requirements of Bluetooth while operating from a total supply current of 0.9 mA., QC 20100525

The design and implementation of a high performance CMOS fully balanced second-generation current conveyor (FBCCII) is presented. The proposed circuit is essential to extend the use of the CCII based circuits to integrated circuits (ICs) applications. The circuit is developed by applying the current sensing technique to a fully balanced version of a differential difference amplifier (DDA). A low power class AB circuit realization is implemented in a 1.2-mum CMOS technology and its different characteristics are measured. Design examples of realizing fully balanced variable gain amplifiers (VGAs) and a bandpass filter based on the proposed FBCCII are given. Experimental results of the proposed circuits are included., QC 20100525

A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm(2) in a 0.5-mum chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54),89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA., QC 20100525

This paper presents design and implementation of a CMOS fully balanced realization of the four-terminal floating nullor (FTFN). The proposed fully balanced FTFN (FBFTFN) is an essential building block for implementing fully balanced architectures of both voltage and current-mode analog CMOS integrated circuits (ICs). A low-power class AB CMOS realization of the proposed circuit is fabricated in a 1.2-mum technology. The proposed circuit has numerous applications. Several applications including fully balanced amplifiers, filters, and sinusoidal oscillators are presented. All proposed design techniques and circuits are experimentally verified., QC 20100525

QC 20100525

This brief presents the fully balanced version of the differential difference amplifier (DDA) as an essential building block for implementing fully differential architectures of analog CMOS integrated circuits (ICs). We demonstrate that the fully balanced differential difference amplifier (FBDDA) provides the solution for systematically developing fully differential versions of any single-ended op-amp based circuit. We also show that, unlike the DDA, the FBDDA exhibits a wide input range without demanding complex circuitry. A low-power class AB CMOS realization of the proposed circuit has been designed and fabricated in a 1.2-mum technology. All proposed design techniques and circuits were experimentally verified., QC 20100525

A new technique for designing digitally tuned frequency selective analogue integrated circuits is proposed. The technique incorporates the R-2R ladder as a circuit element into the circuit design to provide precise frequency characteristics that can be tuned over a wide range. Two filters are described to illustrate the proposed approach. The proposed filters are used to implement the channel-select filter of a multi-standard direct conversion wireless receiver and the bandpass filter of a low IF frequency-hopping receiver., QC 20100525

A technique for designing digitally programmable CMOS integrated filters for multi-standard wireless receivers is presented. The technique exhibits the wide frequency range of the transconductance amplifier filters while offering improved linearity. It utilises digitally controlled current followers to provide precise frequency characteristics that can be tuned over a wide range. A digitally tuned lowpass filter is designed for implementing the channel-select filter in the baseband chain of a multi-standard CMOS wireless receiver. Simulation and experimental results obtained from a 1.2 mu m chip show a programmable frequency response covering the IS-54, GSM, IS-95 and WCDMA wireless standards., QC 20100525

The design of a CMOS fully differential second generation current conveyor is presented. The proposed circuit was designed to incorporate the current sensing technique into a fully differential version of a differential difference amplifier (DDA). A low power class AB circuit realisation has been implemented in 1.2 mu m CMOS technology. A variable gain amplifier (VGA) designed to incorporate the circuit has been shown to exhibit constant, low power consumption and constant, wide bandwidth at different gain settings. Experimental results of the proposed circuits are presented., QC 20100525

A new second-order lowpass filter based on a single CMOS fully differential current conveyor is presented. Developed from the Sallen-Key highpass filter, the proposed filter is AC coupled and provides programmable gain. Moreover, the filter exhibits low noise, high linearity and low power, making it suitable for implementing the baseband filter of a WCDMA direct-conversion wireless receiver. A WCDMA filter having a programmable bandwidth around 2.1 MHz, a variable gain rang of 50dB and a DC notch below 2kHz using passive components below 5kW for resistors and 20pF for capacitors is implemented. Experimental and simulation results obtained from fabricated chips are included., QC 20100525