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In order to avoid water scarcity issues and to promote kitchen grading, hydrogel a super absorbent polymer is incorporated in soil for planting vegetables both chilly and ladies finger in agro bags. The main objective of this study is to identify the effect of hydrogel on growth and yield of both chilly and ladies finger. The various properties of the plant like the height of the plant, the number of leaves, yield, root structure etc. were analyzed for 0.2% of hydrogel by weight of soil. Study showed that hydrogel improves the vegetative growth of plants by retaining more moisture and nutrients within the soil. It modifies the plant-soil interaction resulting in the better use of absorption of water and nutrient from the soil. The comparison between plants cultivated in normal soil and 0.2% hydrogel mixed soil were done. It was found that even for minimum requirement of 0.2% of hydrogel can reduce the water consumption up to 50% as that of the normal plants without comprising the yield.

The implementation of a “superjunction” collector design in a silicon–germanium heterojunction bipolar transistor technology is explored for enhancing breakdown performance. The superjunction collector is formed via the placement of a series of alternating the p/xn-doped layers in the collector-base space charge region and is used to reduce avalanche generation leading to breakdown. An overview of the physics underlying superjunction collector operation is presented, together with TCAD simulations, and a parameterization methodology is developed to explore the limits of the superjunction collector performance. Measured data demonstrate the limitations explored in simulation.

The doping profile of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) is modified to enhance inverse-mode (IM) device operation. Device improvements are presented in this paper, along with the impact the alterations have on the radiation effects response. This investigation represents the first published occurrence of a radiation-hardening-by-process approach in a SiGe HBT technology. Results show that improving IM performance can degrade the radiation tolerance of the structure. Total ionizing dose and single-event transient (SET) results are provided along with an analysis that utilizes TCAD simulation. An additional profile modification using an implanted vertical superjunction is included in this paper to expand upon how nonradiation specific device modifications can impact SETs.

In this paper, significant improvement in cascode LNA performance is demonstrated by using a new high self gain (HSG) common gate (CG) transistor. Emphasis has been on making the output conductance $g_{ds}$ lower and flatter with drain bias. A prototype cascode LNA is designed and fabricated using the developed HSG device in state-of-the-art 0.13 RF SOI technology. Thanks to the HSG device, more than +5 dBm input inter-modulation product (IIP3) improvement is seen in measurements. Very high gain of 19.5 dB at 2.5 GHz with IIP3 value of +1.5 dBm are seen in measurements. Due to optimized transistor sizing, the designed LNA operates at low power of 6.25 mW where 5.2 mA of current is drawn from 1.2 V supply. With integrated high quality factor inductors on high resistivity SOI substrate, the LNA also demonstrates very low noise figure of 0.85 dB. Furthermore, excellent correlation between model simulations and measurements is demonstrated.

Advanced BiCMOS technology is a cost-effective candidate for wide-range of applications, including Radar (automotive radars, high-speed industrial sensors), high-speed wireless and wireline communication, high-speed instrumentation, and mmWave THz imaging and sensing that require high performance SiGe HBTs with high cut-off frequencies fT and high maximum frequencies fMAX. Development of SiGe HBTs in BiCMOS technology with both high fT and fMAX faces significant challenges. Vertical scaling is employed to increase fT in advanced SiGe HBTs including reduction in base and collector thickness or by increasing the collector doping. All these approaches reduce the carrier transit times, but result in an increase in the base resistance and the collector-base capacitance, which degrade fMAX. To overcome these limits, lateral scaling is necessary to reduce the base resistance and the collector-base capacitance. Reduction in emitter width reduces the intrinsic base resistance and Ccb, self-aligned emitter-base integration schemes reduce the extrinsic base link resistance, and raised extrinsic base helps with lower Rb and Ccb. In short, these scaling rules and approaches would need to reduce both base resistance and collector-base capacitance simultaneously for improved fMAX and fT In this paper, results from two experimental studies are presented in a 90nm SiGe BiCMOS technology. Compared with the baseline, one experiment shows more reduction in collector-base capacitance, while the other shows more reduction in base resistance. Both experiments achieved 300GHz fT and met or exceeded the 360GHz fMAX goal of the technology. In addition to straight vertical and lateral scaling, a series of experiments employing other process techniques and structure innovation have also been studied and are reviewed in this paper, including millisecond anneal techniques, low temperature silicide and low temperature contact processes, and secondary trench isolation, achieving fT around 300GHz and fMAX toward half THz.

45nm RFSOI NFET has similar F T /F max as high performance 130nm SiGe NPN and they are both potentially suitable for Ka Band FEM applications. In this paper, we evaluated the Ka band LNA, SPDT, and PA based on both processes. A 28GHz LNA designed with 45nm RFSOI does present a lower noise figure advantage of about 1.4dB compared to ~2dB noise figure of a LNA designed with SiGe NPN. For SPDT, due to low parasitic capacitance in SOI process, based on traditional stack solution, RFSOI process shows about 1dB IL advantage compared with SPDT designed with a bulk SiGe BiCMOS process. While in the high performance SiGe process, a transmission line based SPDT or other advanced topology can get better performance than traditional stack solution with larger area. For PA’s, the SiGe device has higher breakdown voltage than a single FET in 45nm CMOS process, so from power density point of view, SiGe has higher power density. But the SOI process provides the stack solution, so the RFSOI overall output power of a single PA without power combination is similar to one designed with the SiGe NPN.

Integration of high performance switch with Low Noise Amplifier (LNA) devices results in state of the art performance for 5G Front End Module applications. Here we review switch+ LNA performance metrics and its evolution over the last 10 years and highlight directions for the future.

Over the last few decades, SiGe BiCMOS has survived the continued onslaught of RF-CMOS technologies. SiGe HBT invented in late 1980's and later introduced as a BiCMOS technology served as a sweet spot in the emerging RF market, thanks to the SiGe HBT's higher power and better noise characteristics. It did not take very long for RFCMOS scaling roadmap to catch up to SiGe HBT performance levels and displace it from high-volume market segment like RF cellular transceivers. Now with the advent of 5G millimeter-wave (mmWave) applications demanding higher power and lower noise for the front-end, will SiGe BiCMOS once again come back to the forefront to address this market? In this paper we will take a closer look at some of the key aspects of a 130 / 90nm SiGe BiCMOS relative to a 28nm bulk RFCMOS technology for addressing mmWave front-end as well as potential opportunities that lie ahead with scaling.

We present performance and ruggedness trade-offs for the different emitter widths of SiGe HBTs using GLOBALFOUNDRIES 1K5PAXE technology for power amplifier (PA) applications. The technology offers HBTs with low intrinsic base resistance (R BI ) and low emitter-base capacitance $(\mathbf{C}_{\mathbf{BE}})$ which allows for wide emitter devices essential for high power density PA designs through improved emitter utilization. Load-pull measurements of HBTs with $\mathbf{W}_{\mathbf{E}}=1.2\mu m$ show ~1.5dB higher gain at 5.8GHz for a ~17% smaller footprint compared to $\text{W}_{\text{E}}=0.8\mu m$ HBT (for a fixed emitter area). However, smaller footprint increases thermal resistance which degrades ruggedness. Simulations show that the ruggedness can be recovered through power cell layout optimization or by using emitter ballasting techniques. This paper also shows the importance of good mutual heating model between devices for first pass design success and reduced design cycle time.

In this paper, we first introduce the RF performance of Globalfoundries 45RFSOI process. NFET F t > 290GHz and F max >380GHz. Then we present several mm-Wave circuit block designs, i.e., Switch, Power Amplifier, and LNA, based on 45RFSOI process for 5G Front End Module (FEM) applications. For the SPDT switch, insertion loss (IL) 25dBm P max . For the PA, with a 2.9V power supply, the PA achieves 13.1dB power gain and a saturated output power (P sat ) of 16.2dBm with maximum power-added efficiency (PAE) of 41.5% at 24Ghz continuous-wave (CW). With 960Mb/s 64QAM signal, 22.5% average PAE, −29.6dB EVM, and −30.5dBc ACLR are achieved with 9.5dBm average output power.

This paper presents a 3-FET stacked K/Ka-band class-AB power amplifier (PA) implemented in the GLOBALFOUNDRIES 45nm SOI process that is particularly optimized for future high-performance energy-efficient 5G mm-Wave transceiver front-ends. With a 2.9V power supply, the PA achieves 13.1dB power gain and a saturated output power (P sat ) of 16.2dBm with a maximum power-added efficiency (PAE) of 41.5% at 24GHz continuous-wave (CW). The output 1dB compression point (P1dB) is 14.2dBm with 37.4% PAE. The Psat 1dB frequency range is 18GHz–29GHz. With a 9Gb/s 64-QAM modulated signal, 22.4% average PAE and −25.1dB EVM are achieved with 9.9dBm average output power. With a 960Mb/s 64-QAM signal, 22.5% average PAE, −29.6dB EVM, and −30.5dBc ACLR are achieved with 9.5dBm average output power. No digital pre-distortion is employed in both modulation tests. The total PA area is only 550μm × 750μm.

This paper discusses concurrent design and analysis of the first 8.5 kV electrostatic discharge (ESD) protected single-pole ten-throw (SP10T) transmit/receive (T/R) switch for quad-band (0.85/0.9/1.8/1.9 GHz) GSM and multiple-band WCDMA smartphones. Implemented in a 0.18 μm SOI CMOS, this SP10T employs a series-shunt topology for the time-division duplex (TDD) transmitting (Tx) and receiving (Rx), and frequency-division duplex (FDD) transmitting/receiving (TRx) branches to handle the high GSM transmitter power. The measured P 0.1 dB , insertion loss and Tx-Rx isolation in the lower/upper bands are 36.4/34.2 dBm, 0.48/0.81 dB and 43/40 dB, respectively, comparable to commercial products with no/little ESD protection in high-cost SOS and GaAs technologies. Feed-forward capacitor (FFC) and AC-floating bias techniques are used to further improve the linearity. An ESD-switch co-design technique is developed that enables simultaneous whole-chip design optimization for both ESD protection and SP10T circuits.

In this paper, we first analyze an LNA core, cascode structure cut off frequency and power gain relationship with device parameters. Then we discuss the LNA design differences between FET LNA and SiGe LNA during design optimization. SOI floating body FETs have advantages in higher Ft in the optimized current biased region and can offer more design flexibility, while SiGe NPNs need much less trade off room. With this design methodology, we design 5GHz LNAs based on 120nm SOI FET and 0.12um SiGe NPN with 5mA current limitation. The SOI NFET LNA achieves 16dB gain and 1.2dB NF, while SiGe achieves 20dB gain and

The implementation of a “superjunction” collector design in a silicon-germanium heterojunction bipolar transistor is explored for enhancing breakdown performance. The superjunction collector is formed through the placement of a series of alternating pn-junction layers in the collector-base space charge region to modify the carrier energy profile and reduce avalanche generation. An overview of the physics underlying superjunction collector operation is presented with TCAD simulations, and practical superjunction design techniques are discussed. The first measured data on a superjunction collector is also presented and shows a 57% improvement in breakdown performance.

Breakdown voltage and RF characteristics relevant for RF power amplifiers (PA) are presented in this paper. Typically, DC collector-to-emitter breakdown voltage with base open (BV CEO ) or DC collector-to-base breakdown with emitter open (BV CBO ) has been presented as the metric for voltage limit of PA devices. In practical PA circuits, the RF envelope voltage can swing well beyond BV CEO without causing a failure. An analysis of output power swing limitations and DC breakdown is presented with attention to biasing and temperature.

Technology computer-aided design (TCAD) feasibility studies for for scaling a SiGe-based NPN with cutoff frequencies, fT/fMAX of 200/250GHz were conducted, in which the critical process and device design components were self-consistently addressed. The calibrated 200/250GHz calibration was verified by utilization for scaling to a 300GHz performance level, which was subsequently used as the baseline for scaling to a 500 and 630GHz fT performance level. Comparison of the transit time components reveal the base and collector-base transit times as being the predominant electron delay components for performance levels less than 500GHz. At 630GHz the device was observed to be limited primarily by the collector-base transit time.

The goal of achieving terahertz (THz) transistors within the silicon material system has generated significant recent interest. In this paper, we use operating temperature as an effective way of gaining a better understanding of the performance limits of SiGe HBTs and their ultimate capabilities for achieving THz speeds. Different approaches for vertical profile scaling and reduction of parasitics are addressed, and three prototype fourth-generation SiGe HBTs are compared and evaluated down to deep cryogenic temperatures, using both dc and ac measurements. A record peak fT/fmax of 463/618 GHz was achieved at 4.5 K using 130-nm lithography (309/343 GHz at 300 K), demonstrating the feasibility of reaching half-THz fT and fmax simultaneously in a silicon-based transistor. The BVCEO of this cooled SiGe HBT was 1.6 V at 4.5 K (BVCBO = 5.6 V), yielding a record fT times BVCEO product of 750 GHzldrV (510 GHzldrV at 300 K). These remarkable levels of transistor performance and the associated interesting device physics observed at cryogenic temperatures in these devices provide important insights into further device scaling for THz speeds at room temperature. It is predicted in a new scaling roadmap that fT/fmax of room-temperature SiGe HBTs could potentially achieve 782/910 GHz at a BVCEO of 1.1 V at the 32-nm lithographic node.

We feature a 0.35-µm SiGe BiCMOS technology (SiGe 5PAe) that is optimized for power amplifier (PA) applications. The key feature of this technology is a novel low-inductance ground to the package using through-silicon vias (TSVs) that results in a competitive solution for future multiband and multimode PA integration. The tungsten-filled, multifinger, bar-shaped TSV delivers more than a 75% reduction in inductance compared to a traditional wirebond. This enables higher frequency applications with a roughly 20% reduction in die area without compromising the technology reliability for use conditions in a low-cost plastic QFN (quad flat no leads) package. In this paper we demonstrate the commercial feasibility of the TSV, its RF performance, its reliability, and its usefulness in a demanding WiMAX® (Worldwide Interoperability for Microwave Access) PA application.

We describe a 0.35 micron SiGe BiCMOS technology that is optimized for power amplifier (PA) applications. The key feature of this technology is a novel low inductance ground to the package by method of through-silicon-via (TSV), offering a competitive solution for future multi-band / multi-mode PA integration. The tungsten filled, multi-finger, bar shaped TSV delivers over 75% reduction in inductance compared to a traditional wire bond, enabling higher frequency applications with roughly 20% die area reduction, and without compromising the technology reliability for use conditions in a low-cost plastic QFN package. In this paper we demonstrate the commercial feasibility of the TSV, its RF performance, and its usefulness in a demanding WiMAX PA application.

This paper presents a detailed investigation of the key device-level factors that contribute to the bias-dependent features observed in common-base (CB) dc instability characteristics of advanced SiGe HBTs. Parameters that are relevant to CB avalanche instabilities are identified, extracted from measured data, and carefully analyzed to yield improved physical insight, a straightforward estimation methodology, and a practical approach to quantify and compare CB avalanche instabilities. The results presented support our simple theory and show that CB-instability characteristics are strongly correlated with the parasitic base and emitter resistances. The influence of weak quasi-pinch-in effects are shown to contribute additional complexity to the bias dependence of the CB-instability threshold. Measured data from several technology nodes, including next-generation (300-GHz) SiGe HBTs, are presented and compared. Experimental analysis comparing different device geometries and layouts shows that while device size plays an important role in CB avalanche instabilities across bias, these parameters are not sensitive to standard transistor layout variations. However, novel measurements on emitter-ring tetrode transistor structures demonstrate the influence of perimeter-to-area ratio on CB stability and highlight opportunities for novel transistor layouts to increase .

This paper presents a comprehensive picture of operating-voltage constraints in SiGe heterojunction bipolar transistors, addressing breakdown-related issues as they relate to technology generation, bias configuration, and operating-current density. New definitions for breakdown voltage, adopted from standard measurements, are presented. Practical design implications and physical origins of breakdown are explored using calibrated 2-D simulations and quasi-3-D compact models. Device-level analysis of ac instabilities and power performance, which is relevant to mixed-signal circuit design, is presented, and implications of the relaxed voltage constraints for common-base operation are explored.

The inverse-mode operational regime of silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) has to date been largely ignored and is typically dismissed as a viable possibility for circuit applications due to the general perception of its limited dc and ac performance capabilities. In this paper, the inverse-mode performance of four distinct generations of SiGe HBTs is investigated and is found to improve impressively with generational scaling. The physics behind these scaling-induced improvements is examined in detail using a combination of measurements and calibrated simulations. A novel lateral dependence of the inverse-mode base current is identified and is shown to potentially present new opportunities for even larger improvements in inverse-mode performance in SiGe HBTs. A record peak fT in inverse mode of 25 GHz is reported for a prototype fourth-generation device

In this paper, we present 2.4/5.5 GHz LNAs with SPDT Switch for WiFi Front-End Modulate Integrated Circuit (FEM IC) based on high resistivity substrate 0.35um SiGe BiCMOS process. For the 2.4GHz LNA, the bias circuit's effect on the nonlinearity is analyzed and measured, and then a new bias circuit is proposed. With 2.7V supply, it consumes 4.2mA current. The measured Gain is about 14.6dB with input and output return loss better than −10dB. The Noise Figure (NF) is 1.16dB, output 1dB compression point is ∼8dBm, and OIP3 is about 20dBm. For the 5.5GHz LNA with proposed new bias circuit and SPDT switch operating at 7.3mA current with 2.7V power supply, 2.1dB NF and 19dBm OIP3 are achieved in the post layout simulation.

Profile optimization techniques are investigated for silicon-germanium heterojunction bipolar transistors (SiGe HBTs) intended for inverse-mode (IM) operation. IM device operation, also known as inverse active, involves electrically swapping the emitter and collector terminals and has been shown to improve the radiation tolerance of SiGe HBTs to single event transients (SETs). Multiple profile design variations are explored and trade-offs are analyzed with support of TCAD simulation. Modest design variations show marked improvement on IM performance while having minor impact on forward-mode (normal active) operation.

An integrated p-i-n diode for use in SiGe BiCMOS technology applications has been developed. The device may be used into the MMW frequency range

This paper establishes the viability and suitability of silicon germanium (SiGe8HP) technology, enablement tools and circuits to millimetre-wave applications today and a roadmap to the future. Key elements discussed include SiGe technology and design enablement advancements leading to the world's most highly integrated, lowest power 60 GHz transmitter/receiver ICs.

The thermodynamic stability of device-relevant epitaxial SiGe strained layers under proton irradiation is investigated using X-ray diffraction techniques, and compared with its stability constrain under high-temperature annealing. Irradiation with 63 MeV protons is found to introduce no significant microdefects into the SiGe thin films, regardless of starting stability condition of the SiGe film, and thus does not appear to be an issue for the use of SiGe HBT technology in emerging space systems. The strain relaxation of SiGe thin film under thermal annealing, however, is sensitive to the composition and thickness of the as-grown samples, as expected, with the subsequent lattice relaxation of the unstable samples occurring at a much higher rate than that of metastable samples.

A group of novel device phenomena are reported in state-of-the-art SiGe HBTs operating at cryogenic temperatures. Both negative-differential-resistance (NDR) and an unusual “hysteresis” behavior are observed in the forced- I B output characteristics of 350 GHz SiGe HBTs at cryogenic temperatures. Unlike the NDR effects in resonance-tunneling-diodes and III–V HBTs, the phenomena demonstrated in this paper are correlated to SiGe HBT high-injection effects and modulated by bias level. This unusual cryogenic behavior have been systematically investigated, and the results are compared to 50 GHz, 120 GHz, and 200 GHz SiGe HBT technology generations. An advanced Shockley–Read–Hall (SRH) recombination model including tunneling effects is introduced and used to explain the underlying NDR and “hysteresis” mechanisms in these cooled SiGe HBTs. Implications for potential novel device and circuit designs are suggested.

We present the advances in Silicon Germanium Heterojunction Bipolar Transistor (SiGe HBT) and BiCMOS technology capabilities to address the emerging millimetre-wave (mmWave) applications. SiGe HBTs with fMAX performance reaching 350 GHz that are integrated with advanced CMOS and high-frequency passives is envisioned to allow better integration capability for mmWave applications. This capability of SiGe HBT BiCMOS technology is discussed relative to an InP HBT technology. (© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The effect of proton irradiation on operating voltage constraints in SiGe HBTs is investigated for the first time in 120 GHz and 200 GHz SiGe HBTs. A variety of operating bias conditions was examined during irradiation, including terminals grounded, terminals floating, and forward active (FA) bias operation. The excess base current degradation at 5.0/spl times/10/sup 13/ p/cm/sup 2/ was similar in all cases. BV/sub CEO/ and BV/sub CBO/ showed no significant signs of degradation with irradiation. We also investigated for the first time the impact of radiation on SiGe HBTs biased under so-called "unstable" conditions (i.e., operating point instabilities). In the case of unstable bias conditions, device degradation under proton exposure is significantly different than for stable bias, and bias conditions can play a significant role in the damage process, potentially raising issues from a hardness assurance perspective.

We present the results of gamma irradiation on third-generation, 200 GHz SiGe HBTs. Pre- and post-radiation dc figures-of-merit are used to quantify the tolerance of the raised extrinsic base structure to Co-60 gamma rays for varying device geometries. Additionally, the impact of technology scaling on the observed radiation response is addressed through comparisons to second generation, 120 GHz SiGe HBTs. Comparisons to previous proton-induced degradation results in these 200 GHz SiGe HBTs are also made, and indicate that the STI isolation oxide of the device shows increased degradation following Co-60 irradiation. The EB spacer oxide, on the other hand, demonstrates increased susceptibility to proton damage. Low dose rate proton testing was also performed and indicate that although there is a proton dose rate effect present in these devices, it cannot fully explain the observed trends. Similar trends have previously been observed for buried oxides and isolation oxides in several MOS technologies and have been attributed to increased charge yield in these oxides for 1.2 MeV Co-60 gamma rays when compared to 63 MeV protons.

We present the status and direction of silicon semiconductor technologies targeted for applications such as wireless, networking, instrumentation, and storage markets. Various technological aspects for multiple branches of RF foundry technologies that are based on the standard foundry compatible CMOS node are discussed - SiGe BiCMOS HP ("high performance") tailored to high-frequency applications, SiGe BiCMOS WL ("cost performance") tailored to wireless/storage applications, and RF-CMOS optimized for low-cost consumer applications. Future opportunities and challenges for advancement in RF technologies are described in light of CMOS and SiGe heterojunction bipolar transistor scaling. In addition, we discuss the maturity of SiGe BiCMOS by looking at the levels of integration and manufacturability.

This work presents the results of the effects of mechanical planar biaxial tensile strain applied, post-fabrication, to Si/SiGe HBT BiCMOS technology. Planar biaxial tensile strain was applied to the samples, which included both standard Si CMOS, SiGe HBTs, and an epitaxial-base Si BJT control, for both first and second generation SiGe technologies. Device characterization was performed before and after strain, under identical conditions. At a strain level of 0.123%, increases in the saturated drain current as well as effective mobility are observed for the nFETs. The Si BJT/SiGe HBTs showed a consistent decrease in collector current and hence current gain after strain.

A robust, time-dependent methodology is used to investigate impact-ionization-induced mixed-mode reliability stress (the simultaneous application of high J/sub E/ and high V/sub CB/) in advanced SiGe HBTs. We present comprehensive stress data on second-generation 120-GHz SiGe HBTs, and use specially designed test structures with variable emitter-to-shallow trench spacing to shed light on the resultant damage mechanisms. We also explore the impact of mixed-mode stress on low frequency noise, ac performance, high-temperature device characteristics, and employ two-dimensional calibrated MEDICI simulations using the hot carrier injection current technique to better understand the physical damage locations.

A 21 GHz inductorless differential quadrature ring oscillator suitable for use in clock and data recovery circuits in optical network receivers is presented. Implemented using a commercially available 0.18 μm 120 GHz SiGe HBT technology, the circuit consists of only 22 SiGe HBTs and 4 resistors, and occupies an active area of less than 120×150 μm 2 . The circuit operates on a −3.0 V power supply and dissipates at most 152 mW of power. The oscillation frequency is tunable from 18.33 to 21.19 GHz while the output power varies from −13.5 to −9.0 dBm. A phase noise of −83.33 dBc/Hz at 1 MHz offset from the carrier frequency of 21.19 GHz is achieved. This results in an oscillator figure-of-merit of −148.03, which is comparable to other ring oscillators published in literature operating in similar frequency range.

This paper examines the impact of SiGe HBT scaling on 1/f noise and phase noise of oscillators and frequency synthesizers. The increase of transistor speed with scaling is shown to significantly increase the sensitivity of oscillation frequency to 1/f noise and, thus, degrade close-in phase noise, but decrease the sensitivity of oscillation frequency to base current shot noise and base resistance thermal noises. The results show that corner offset frequency defined by the intersect of the 1/f3 and 1/f2 phase noise has little to do with the traditional 1/f corner frequency. The relative importance of individual noise sources in determining phase noise is examined as a function of technology scaling, device sizing, and oscillation frequency. The collector current shot noise and base resistance noise are shown to set the fundamental limits of phase noise reduction. A methodology to identify the maximum tolerable 1/f K factor is established and demonstrated for the HBTs used