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Inverse Lithography Technology (ILT) has become one of the key computational lithography solutions, which may produce mask output that results in better process latitude and CD control on wafer than the one using conventional OPC. However, the curvilinear inverse lithography recipe parameter tuning is a non-trivial task, which involves optimization for various common objectives such as common DOF, NILS, and pvband (process variability band) [1]. It is known that test patterns used for recipe development play a critical role in achieving optimized ILT masks in terms of mask-friendliness, OPC convergence or multi-structure common focus range. The traditional way of test pattern selection is usually a clip-level manual search by taking into account of design rules, which inevitably may cause lack of critical design representations. In this paper, we introduce Mentor Graphic’s Calibre SONR[2], a Machine Learning (ML) method to implement design layouts clustering and automatic pattern selections for ILT recipe tuning on a full-chip level. Calibre SONR leverages design layouts and process models to create necessary features as input and then combine with a proprietary clustering algorithm to fully analyze and cluster a full layout in feature vector space. The degree of pattern reduction is controlled by an adjustable similarity metric[2]. The paper has four parts: the first part is on the feature generation and data collection based on the design layout, the lithography and etch process models. A wide range of over 100 features are extracted to represent the layout and process etc. The second is on the SONR model building and pattern selection from the full-chip; the third on the ILT recipe creation process with patterns selected from SONR and the traditional method; the fourth on the pattern coverage analysis and verification by evaluating the recipe quality through OPCV checks, and compare the results between SONR-based and traditional pattern selection methods.

Inverse lithography technology (ILT) optical proximity correction is going to play a critical role in addressing challenges of optical and EUV lithography as the industry pushes toward advanced nodes. One major barrier in adoption of ILT has been the mask writer’s inability to efficiently write curvilinear patterns. With the introduction of multibeam mask writers, this barrier has been removed and widespread adoption of ILT is imminent. Traditionally, mask writers have accepted only trapezoidal inputs to the tool, though recent trends show that mask writers are adopting newer formats that already reduce file size. However, as the ILT shape complexity and data volume increases further for 5 nm nodes and beyond, the explosion of mask pattern data file size becomes a major concern. Therefore, there is a need for the industry to look toward other compact formats of data representation that will be capable of serving well for multiple generations of mask making. We compare various curvilinear data representation schemes and their value in the curvilinear ILT-based mask manufacturing flow. We demonstrate that given the nature of curvilinear data, representing it using native curve formats has significant value to reduce file size for future mask making flows. The same format may not be applicable for all types of features in the input mask. These options will be discussed. We will compare the value of such exotic representations with regular simplification approaches that reduce data volume using standard methods and discuss the extents and limits of all these techniques. To evaluate practical use of curvilinear representation in place of conventional piecewise linear representation, we manufacture and measure a photomask to evaluate the accuracy of curvilinear representations. Finally, we use EUV AIMS to assess the impact of curvilinear representation on wafer process window.

The patterning requirements of next generation lithographic processes and the desire to keep manufacturing costs down have pushed the lithographers to explore the advantages of the curvilinear masks. Multiple studies backed by the experimental results have demonstrated the lithographic advantage of the curvilinear (CL) photomasks over the rectilinear (RL) approximations by showing improved MEEF, depth of focus (DoF) and common DoF (CDoF) for variety of patterns on the same mask, ILS and, as a result, process window (PW) of the CL masks over its close RL siblings [1,2]. Manufacturability of the CL masks has been limited due to the architecture of the Variable Shaped Beam (VSB) writers, which made it prohibitive from both mask data preparation (MDP) and mask writing perspective. The availability of Multi Beam Mask Writers (MBMW) has removed these roadblocks and brought introduction of the curvilinear masks much closer to reality. The development of novel approaches for MDP and Mask Proximity Correction (MPC) as it is demonstrated by Bork et al in [3] brought further advances in availability of the CL masks for high volume manufacturing (HVM). Traditionally the Inverse Lithography Technology (ILT) has offered the most potential to achieve significant lithographic advantage over RL masks but has suffered from very long data preparation runtimes which presented an additional hurdle for broad deployment in manufacturing. While various speed up options such as machine learning-based acceleration, and GPU processing [4,5] are being explored, the full chip ILT run time still represents significant challenge in the HVM world. This paper will concentrate on two OPC approaches that allow CL mask generation without run time penalties associated with full chip ILT processing. The first is based on a hybrid methodology that allows for generation of the CL mask shapes by using fast ILT-based algorithms for SRAF generation while the main features are controlled to allow for full chip processing within the reasonable time. The second approach is more appropriate for the memory applications where patterns are highly repetitive. Due to high level of repetition, it is acceptable to use full ILT correction carried over a small area of the chip and to utilize pattern matching (PM) methodologies to propagate both SRAFs and OPC-corrected features from unique to non-unique pattern placements. Such a methodology allows for the full ILT advantages in the highly critical memory array areas.

In the last decade, Photonics Technology has been an emerging technology for optical telecommunications and for optical interconnects in microelectronics. As a result, a large diversity of Photonics design methodologies has merged with very challenging scales and shapes. Manufacturing such curvy and critical photonics shapes requires advanced Resolution Enhancement Techniques (RET) including Inverse Lithography Techniques (ILT) with 193nm immersion lithography. In this paper, we investigate the manufacturing challenges of several Photonics devices using advanced ILT solutions and the SRAF insertion impact on delivering good litho quality including EPE, PVband and LER. We will demonstrate how our Calibre ILT solutions enable the manufacturing of the most challenging Photonics designs.

Inverse Lithography Technology OPC (ILT) is going to play a critical role in addressing challenges of optical and EUV lithography as industry pushes towards advanced nodes. One major barrier in adoption of ILT was mask writer’s inability to efficiently write curvilinear patterns. With the introduction of multi-beam mask writers [1] [2], this barrier has been removed and widespread adoption of ILT is imminent. Traditionally, mask writers have accepted only trapezoidal inputs to the tool, though recent trends show that mask writers are adopting to newer formats which already reduce file size. However, as the ILT shape complexity and data volume increases further for 5nm nodes and beyond, the explosion of mask pattern data file size becomes a major concern. Therefore, there is a need for the industry to look towards other compact formats of data representation that will be capable of serving well for multiple generations of mask making. In this paper we will be comparing various curvilinear data representation schemes and their value in the curvilinear ILT based mask manufacturing flow. We will demonstrate that given the nature of curvilinear data, representing it using native curve formats has lot of value in terms of file size reduction for futuristic mask making flows. Same format may not be applicable for all type of features in the input mask. These options will be discussed. There is also a need to compare the value of such exotic representations with regular simplification approaches that reduce data volume using standard methods. We will make that comparison in the paper and discuss the extents/limits of all these techniques. Comparison of changes in simulated mask contours and wafer contours will also be made.

Generating curvilinear mask shapes in OPC instead of pure rectangular shapes is becoming more and more realistic as a method for improving wafer lithography performance. The main benefit of using curvilinear shapes is an improved process window, meaning that the wafer image is less sensitive to dose and focus conditions during the exposure. With the increased compute power of latest High-Performance-Clusters (HPC) and the availability of Multi-Beam-Mask-Writers (MBMW) those wafer lithography benefits can be realized at technology nodes currently being developed. A very practical challenge for putting masks with curvilinear shapes in production is the availability of reliable Mask- Rule-Checks (MRC). The OPC engine not only needs to generate shapes which are manufacturable, the mask shop also needs a method of verifying that incoming mask data is manufacturable. For curvilinear mask shapes this is more challenging than for rectangular mask shapes, since simple width and space checks as used for rectangular masks are not sufficient anymore. In this paper, a comprehensive set of MRC limits is being discussed and the effectiveness of an MRC engine operating on curvilinear input data is demonstrated. Rules used here include minimum width of exposed features, minimum space between exposed features, minimum curvature of convex and concave shapes, as well as minimum area of exposed features.

As the technology node gets smaller and smaller, the benefit from Sub-Resolution Assist Features (SRAF) becomes significant in EUV lithography which makes SRAFs a must-have tool for next generation beyond 7nm technology. When considering EUV specific effects, the metrics that need to be accounted for include Image Log-Slope (ILS), Process Variability (PV Band), common Depth of Focus (cDOF), and Image Shift (ImS) through focus. When these critical factors are accounted for during the EUV mask generation the optimization become much more complicated and challenging and necessitates the need for SRAFs beyond 7nm. SRAF helps enhance not only the PV Band, but more importantly helps boost the ILS, which is one of the key factors for improving stochastic effect in EUV. However, ILS is just one of the important image quality metric that we should focus on. For metal layers, Image Shift is another key factor which can have a big impact on overlay. ImS at the nominal condition could be compensated by Optical Proximity Correction (OPC), but image shift through focus can hardly be tuned by the main feature correction. The image shift through focus can be mitigated by SRAF insertion. Strong 3D mask effects can cause best focuses of different patterns to be far apart in EUV, which can cause an unusable cDOF even when the individual depth of focus values of all the patterns are not bad. SRAFs can be inserted to improve the individual depth of focus and align the best focuses together to help enhance the common process window. When taking account of various different EUV specific metrics mentioned above, then the most critical question for the next generation beyond 7nm is “How to define the cost function for mask optimization with SRAFs?” (Figure 1, EUV mask optimization flow for next generation beyond 7nm). In this study the image quality metrics including ILS, PVBand, cDOF, and ImS are evaluated. For each optimization schema using different cost functions, we examine the cost function metric and its impact on the other image quality metrics. We also present the potential trade-offs together with the analysis. Furthermore, multiple cross cost functions are defined for SRAF optimization and the results are analyzed accordingly. Both contact and metal layer patterns representing next generation beyond 7nm design rules are investigated. In our testing, symmetric standard sources from ASML NXE3400 is examined and the results are compared and analyzed.

As the EUV lithography is extending beyond 7nm technology, design to mask strategy becomes more complex. New challenges including advanced OPC and ILT in mask optimization, curvilinear masks, shrinking Mask Rule Checking (MRC), Sub-Resolution Assist Features (SRAF) generation and formation, and other complex mask geometries drive the needs to study this synergy from different stages of the flow from Optical Proximity Correction (OPC), Mask Process Correction (MPC), fracturing, to mask writing and inspection. In this study, different OPC and SRAF mask formations including curvilinear masks, controlled Manhattanized approximations of curvilinear masks, and conventional masks are generated. We illustrate whether curvilinear masks have any demonstrable lithographic benefits. A quantitative comparison of how the Manhattanization impacts mask formation. The image quality metrics such as Image Log Slope (ILS), Process Viability (PV) Band, and Depth of Focus (DOF) from various OPC mask flavors including different MRC settings and different mask forms are compared and discussed. The mask manufacturability study is conducted to identify any major challenges and approaches to minimize, including assessing the value and need for native curvilinear write tool support on a MultiBeam Mask Writer (MBMW) or a single beam Vector Shaped Beam (VSB) mask writer.

Inverse lithography is most commonly utilized to guide optimizing RET (Resolution Enhancement Technology) solution such as SRAF (Sub-resolution Assist Feature) placement and OPC (Optical Proximity Correction) edge dissection and fragmentation. Inverse lithography recipe often features an array of user-controlled parameters, which allow refined tuning of inverse solution maximizing for various common objectives such as common DOF, NILS, and pvband (process variability band). In practice, some test case shows that the inverse lithography engine can be perturbed to produce novel solution maximizing other unconventional objectives such as OPC solution’s mask-friendliness, OPC convergence at extreme dense-to-iso transition, and multi-structure common focus range. However, the parameter tuning process can be time-consuming and requires expert knowledge of the tool. Also, parameters correlation to those objectives is often highly non-linear. All these reasons make inverse lithography recipe parameter tuning for unconventional objective a non-trivial task. Genetic Algorithm (GA) has been demonstrated to be effective at solving non-trivial optimization tasks such as SRAF rule optimization [1], OPC recipe optimization [2,3] and source mask optimization [4-6], and. Here we propose to use modified GA based engine for inverse lithography recipe optimization. We will show experimental results and discuss the benefits and challenges. We will demonstrate with three real test cases that this flow has a reasonable TAT and improved inverse lithography solutions.

An approach of solving the inverse lithography problem as a nonlinear, constrained minimization problem over a domain of mask pixels was suggested in the paper by Yu. Granik "Fast pixel-based mask optimization for inverse lithography'' in 2006. This idea was advanced to account for pinching and bridging print contour constraints in the paper "Controlling Bridging and Pinching with Pixel-based Mask for Inverse Lithograph'' by S. Kobelkov and others in 2015. The present paper extends this approach further for solving the enclosure print image constraints, getting maximum common depth of focus, and obtaining uniform PV-bands. Namely, we suggest several objective functions that express penalty for constraint violations. Their minimization with gradient descent methods is considered. A number of applications have been tested with ILTbased pxOPC tool for DUV metal, contacts, and EUV metal layouts; results are discussed showing benefits of each approach.

The next generation beyond 7nm node potentially requires the implementation of Sub-Resolution Assist Features (SRAF) with EUV lithography. This paper aims at providing a clear SRAF strategy for the next generation beyond 7nm node designs through a series of experiments. Various factors are considered, including: stochastic effects, 3D mask effects, through-slit effects, aberrations, and pixelated SMO sources. EUV has 13.5nm as its wavelength, which is much smaller than the wavelength used in ArF lithography, and this gives very different imaging challenges compared to the ArF case. Due to the small wavelength and numerical aperture (NA) of the current EUV tools, depth of focus is not as significant of a concern as in DUV. Instead, EUV lithography is severely challenged by stochastic effects, which are directly linked to the slope of the intensity curve. DUV SRAF has been shown to be a powerful tool for improving NILS/ILS, as well as DOF, and here we explore how that translates into EUV imaging. In this paper, we consider Process Variability (PV) Bands with a variety of process conditions including focus/dose/mask bias changes and also the NILS/ILS as our objective functions, to determine what the best SRAF solution is for a set of test patterns. We have full investigations on both symmetric SRAF and asymmetric SRAF. SRAF can potentially mitigate image shift through focus, i.e. non-telecentricity, caused by EUV 3D shadowing effect. This shadowing effect is pattern dependent and contributes to the overlay variation. As we approach the next generation beyond 7nm node, this image shift can be more significant relative to the overlay budget, hence we further investigate the impact of SRAF placement to the image shift. Moreover, the Center of Focus shift due to the large 3D mask absorber thickness can be potentially mitigated by SRAF implementation. The common process window is significantly impacted by both the center of focus shift and the individual depth of focus. We study the change by adding SRAF using both a symmetric source (standard source) and an asymmetric source (SMO source). Once SRAF is inserted for the test patterns, the common process window is plotted to compare the solutions with and without SRAF. Finally, we understand the importance of using full flare map and full through slit model (including aberration variation through slit) in the main feature correction, but in this paper, we will further evaluate the need of using full models in SRAF insertion. This is a necessary step to determine the strategy of SRAF implementation for the next generation beyond 7nm node.

Si-Photonics is the technology in which data is transferred by photons (i. e. light). On a Photonic Integrated Circuit (PIC), light is processed and routed on a chip by means of optical waveguides. The Si-Photonics waveguides functionality is determined by its geometrical design which is commonly curved, skew and non-Manhattan. That is why printing fidelity is very challenging on photonics patterns. In this paper, we present two different Optical Proximity Correction (OPC) flows for Si-Photonics patterning. The first flow is regular model based OPC and the second one is based on Inverse Lithography Technology (ILT). The first OPC flow needs first to retarget the input layout while the ILT flow does support skew edges input by tool design and does not need any retargeting step before OPC. We will compare these two flows on various Si- Photonics waveguides from lithography quality, run time and MRC compliance of mask output. We will observe that ILT flow gives the best Edge Placement Error (EPE) and the lowest ripples along the devices. The ILT flow also takes into account the mask rules so that the generated mask is mask rule compliant (MRC). We will also discuss the silicon wafer data where Si-Photonics devices are printed within the two different OPC flows at process window conditions. Finally, for both OPC flows, we will present the total OPC run time which is acceptable in an industrial environment.

Inverse Lithography Technology (ILT) is gaining acceptance as part of a comprehensive OPC solution especially as a repair technique to locally improve process window where conventional OPC does not have enough degrees of freedom to produce acceptable results. [1] Since ILT is significantly more computationally intensive than conventional OPC, a localized application of ILT does not significantly increase OPC cycle time. As ILT methods mature and become more efficient, combined with the availability of huge compute clusters for post tape out data processing, the possibility of full-field ILT OPC could soon become reality. Full-field ILT OPC may provide improved process window and greater layout flexibility as long as multi-patterning methods with 193 nm exposure wavelength remain the primary lithography strategy for advanced technology nodes. Due to limitations of photomask lithography tools that prevent efficient exposure of non-Manhattan shapes, ILT OPC output is typically post-processed to conform to mask MRC rules, rendering the raw all-angle features to a Manhattanized equivalent. Previous comparisons of raw vs Manhattan ILT OPC at earlier nodes have shown that a Manhattanized output can be made to print on wafer with equivalent process window while conforming to mask manufacturing rules.[2,3,4] In this paper we use wafer-level lithography simulation to compare raw vs Manhattanized ILT output based on current advanced nodes and MRC rules. We expand this study to include a mask model to ensure that mask corner rounding effects are considered.

Inverse Lithography Technology (ILT) has become a viable computational lithography candidate in recent years as it can produce mask output that results in process latitude and CD control in the fab that is hard to match with conventional OPC/SRAF insertion approaches. An approach to solving the inverse lithography problem as a nonlinear, constrained minimization problem over a domain mask pixels was suggested in the paper by Y. Granik “Fast pixel-based mask optimization for inverse lithography” in 2006. The present paper extends this method to satisfy bridging and pinching constraints imposed on print contours. Namely, there are suggested objective functions expressing penalty for constraints violations, and their minimization with gradient descent methods is considered. This approach has been tested with an ILT-based Local Printability Enhancement (LPTM) tool in an automated flow to eliminate hotspots that can be present on the full chip after conventional SRAF placement/OPC and has been applied in 14nm, 10nm node production, single and multiple-patterning flows.

As feature sizes become smaller and smaller, the complexity and the cost of using multiple patterning with 193i becomes a significant issue in lithography. Hence, EUV starts to play an important role for 7nm node and beyond. Industry is now investigating solutions on all major EUV components – source, resist mask technology, as well as resolution enhancement techniques (RET), including sub-resolution assist features (SRAFs). Unlike ArF lithography, the non-telecentricity of the EUV optical system coupled with the relatively thick mask stack causes shadowing effects. This asymmetric imaging may in turn have an impact on assist feature placement, requiring different SRAF rules for different directions at the edges and corners. In this work, simulation studies were conducted using Calibre on 20x20 nm contact patterns through pitch to investigate the impact of assist features. Assist features were varied as a function of horizontal / vertical positions independently and the image quality parameters such as depth of focus (DOF), MEEF, best focus (BF) shift and overlapping process window were monitored with and without SRAFs. Both rules-based and model based assist feature placements were implemented for selected patterns. Results indicate that inclusion of assist features for contact arrays improve individual and overlapping process windows with minimal effect on best focus shift. Wafer data collected from these patterns confirmed the improvement in overlapping process window with the inclusion of assist features.

The printing of contact holes using positive tone development typically requires the interference of more than the 0th and 1st diffracted orders. In the 2d case and cQuad illumination in a positive tone process, if (0,0), (±1,0), and (0,±1) are exclusively present, the relevant contrast for imaging can in the best case not rise above 0.33, which is typically insufficient for a good process window. And this maximum value can only be achieved if the (0,0) and (±1,0) orders are matched to give a perfect sine wave of perfect contrast in y while the (0,0) and (0,±1) orders yield perfect contrast in x . In reality, the contrast is quite a bit lower. On the other hand, for negative tone development we are interested in the minima of the intensity–the dark locations in the image–and if we can manage to reduce the intensity in the minima we can achieve a high contrast image. Through a choice of RET and illumination, we manage to achieve a resolution for contact holes in 2d at k 1 values that can otherwise be achieved only for 1d imaging. Earlier work has been done on double exposures that exposed in the same resist a horizontal grating with x-dipoles and subsequently a vertical grating with y dipoles, without intermediate process steps. This yielded a high contrast image in resist at k 1 1 We show that an equivalent result can be achieved in a single exposure with a single mask, at admittedly high dose. We investigate the process parameters and the related mask tolerances, and find a non-intuitive result for the mask pattern that yields an optimized image at given mask specifications. Finally, we investigate the extension of this technique to EUV through simulations and experiments.

The next-generation beyond 7-nm node potentially requires the implementation of subresolution assist features (SRAF) with extreme ultraviolet (EUV) lithography. This paper aims at providing a clear SRAF strategy for the next-generation beyond 7-nm node designs through a series of experiments. Various factors are considered, including stochastic effects, three-dimensional (3-D) mask effects, through-slit effects, aberrations, and pixelated source mask optimization (SMO) sources. We consider process variability bands with a variety of process conditions, including focus/dose/mask bias changes and also the normalized image log-slope/image log-slope as our objective functions, to determine what the best SRAF solution is for a set of test patterns. Inverse lithography technology is implemented to optimize both the main feature (MF) mask and SRAF placement, in particular, asymmetric SRAF placement to balance the 3-D mask effects. SRAF can potentially mitigate image shift through-focus, i.e., nontelecentricity, caused by EUV 3-D shadowing effect. This shadowing effect is pattern-dependent and contributes to the overlay variation. As we approach the next-generation beyond 7-nm node, this image shift can be more significant relative to the overlay budget, hence, we further investigate the impact of SRAF placement to the image shift. Moreover, the center of focus shift due to the large 3-D mask absorber thickness can be potentially mitigated by SRAF implementation. The common process window is significantly impacted by both the center of focus shift and the individual depth of focus and is evaluated using both metal and contact layer test cases. We study the source impact to SRAF insertion by experimenting with both a symmetric source (standard source) and an asymmetric source (SMO source). Finally, we understand the importance of using full flare map and full through-slit model (including aberration variation through-slit) in the MF correction. Furthermore, we evaluate the need of using full models in SRAF insertion. This is a necessary step to determine the strategy of SRAF implementation for the next-generation beyond 7-nm node.

The 14nm node designs is getting more sophisticated, and printability issues become more critical which need more advanced techniques to fix. One of the most critical processes is the contact patterning due to the very aggressive design rules and the process window which becomes quickly limited. Despite the large number of RET applied, some hotspot configurations remain challenging. It becomes increasingly challenging to achieve sufficient process windows around the hot spots just using conventional process such as OPC and rule-based SRAF insertion. Although, it might be desirable to apply Inverse Lithography Technique (ILT) on all hot spots to guarantee ideal mask quality. However, because of the high number of hot spots to repair in the design, that solution might be much time consuming in term of OPC and mask processing. In this paper we present a hybrid OPC solution based on local ILT usage around hot spots. It is named as Local Printability Enhancement (LPE) flow. First, conventional OPC and SRAF placement is applied on the whole design. Then, we apply LPE solution only on the remaining problematic hot spots of the design. The LPE flow also takes into account the mask rules so that it maintains the mask rule check (MRC) compliance through the borders of the repaired hot spot’s areas. We will demonstrate that the LPE flow enlarges the process window around hot spots and gives better lithography quality than baseline. The simulation results are confirmed on silicon wafer where all the hot spots are printed. We will demonstrate that LPE flow enlarges the depth of focus of the most challenging hot spot by 30nm compared to POR conventional solution. Because the proposed flow applies ILT solution on very local hot spot areas, the total OPC run time remains acceptable from manufacturing side.

In this paper, we present an optimization methodology for the template designs of sub-resolution contacts using directed self-assembly (DSA) with grapho-epitaxy and immersion lithography. We demonstrate the flow using a 60nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of Template Error Enhancement Factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity, and evaluate optimized template designs with TEEF metrics. Our data shows that SMO is critical to achieve sub-80nm non- L0 pitches for DSA patterns using 193i.

In this paper we study the trade-offs and benefits of using ILT-based SRAF placement/OPC over conventional SRAF placement/OPC for various front-end and back-end design configurations on a full chip. We explore the use models and benefits of using ILT-based Local Printability Enhancement (LPE) in an automated flow to eliminate hot spots that can be present on the full chip after conventional SRAF placement/OPC. We study the impact on process-window, performance, and mask manufacturability.

This paper explores the concept of a variable threshold resist model (VTRM) where the model is trained with data from a specific resist process, and may be applied to lithography simulation for that resist process with a wide variety of optical exposure conditions. This type of simulation is based on aerial image simulation and the application of a simple algebraic formula. It is therefore, very fast and applicable to a wide variety of simulation applications. We have trained the model with the 248nm resists TOK TDUR022 and Shipley UV6. In both cases the model does a good job of capturing most resist dynamics over a wide range of dose, critical dimension (CD), pitch, focus, and partial coherence conditions.

Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.

Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.

Resolution Enhancement Techniques have continuously improved over the last decade, driven by the ever growing constraints of lithography process. Despite the large number of RET applied, some hotspot configurations remain challenging for advanced nodes due to aggressive design rules. Inverse Lithography Technique (ILT) is evaluated here as a substitute to the dense OPC baseline. Indeed ILT has been known for several years for its near-to-ideal mask quality, while also being potentially more time consuming in terms of OPC run and mask processing. We chose to evaluate Mentor Graphics’ ILT engine “pxOPCTM” on both lines and via hotspot configurations. These hotspots were extracted from real 28nm test cases where the dense OPC solution is not satisfactory. For both layer types, the reference OPC consists of a dense OPC engine coupled to rule-based and/or model-based assist generation method. The same CM1 model is used for the reference and the ILT OPC. ILT quality improvement is presented through Optical Rule Check (ORC) results with various adequate detectors. Several mask manufacturing rule constraints (MRC) are considered for the ILT solution and their impact on process ability is checked after mask processing. A hybrid OPC approach allowing localized ILT usage is presented in order to optimize both quality and runtime. A real mask is prepared and fabricated with this method. Finally, results analyzed on silicon are presented to compare localized ILT to reference dense OPC.

Source-mask optimization (SMO) in optical lithography has in recent years been the subject of increased exploration as an enabler of 22/20nm and beyond technology nodes [1-6]. It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the source and mask, which yields improved lithographic performance. This paper will demonstrate the value of SMO software in resolution enhancement techniques (RETs). Major benefits of SMO include improved through-pitch performance, the possibility of avoiding double exposure, and superior performance on two dimensional (2D) features. The benefits from only optimized source, only optimized mask, and both source and mask optimized together will be demonstrated. Furthermore, we leverage the benefits from intensively optimized masks to solve large array problems in memory use models (MUMs). Mask synthesis and data prep flows were developed to incorporate the usage of SMO, including both RETs and MUMs, in several critical layers during 22/20nm technology node development. Experimental assessment will be presented to demonstrate the benefits achieved by using SMO during 22/20nm node development.

In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography has been explored and documented in the literature.1-5 It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, which leads to improved lithographic performance. These efforts have driven the need for improved controllability in illumination5-7 and have pushed the required optimization performance of mask design.8, 9 This paper will present recent experimental evidence of the performance advantage gained by intensive optimization, and enabling technologies like pixelated illumination. Controllable pixelated illumination opens up new regimes in control of proximity effects,1, 6, 7 and we will show corresponding examples of improved through-pitch performance in 22nm Resolution Enhancement Technique (RET). Simulation results will back-up the experimental results and detail the ability of SMO to drive exposure-count reduction, as well as a reduction in process variation due to critical factors such as Line Edge Roughness (LER), Mask Error Enhancement Factor (MEEF), and the Electromagnetic Field (EMF) effect. The benefits of running intensive optimization with both source and mask variables jointly has been previously discussed.1-3 This paper will build on these results by demonstrating large-scale jointly-optimized source/mask solutions and their impact on design-rule enumerated designs.

Traditional OPC is essentially an iterated feedback process, in which the position of each target edge is corrected by adjusting a controlling mask edge. However, true optimization adjusts the mask variables collectively, and in so-called SMO approaches (for Source Mask Optimization) the source variables are adjusted as well. Optimized masks often have high edge density if synthesis methods are used in an effort to obtain a more global solution, and the correspondence between individual mask edges and printed target edges becomes less clearcut than in traditionally OPC'd masks. Restrictions on phase shift and MEEF tend to reduce this departure from traditional solutions, but they trade off the theoretical performance advantage in dose and focus latitude that phase shift provides for a reduced sensitivity to thick mask topography and to manufacturing error. Mask variables couple across long distances only in the indirect sense of stitched connection across chains of neighbor-to-neighbor interactions, but source variables interact directly across entire masks. Source+mask optimization of large areas therefore involves long-range communication across the parts of the calculation, though the number of source variables involved is small. Tradeoffs between source structure and pattern diversity are illustrated, taking into account the limited (but unknown) number of binding features in a large layout. SMO's exploitation of complex source designs is shown to provide superior solutions to those obtained by mask optimization alone. Moreover, in development work the ability to adjust the source opens up new options in process engineering, and these will become particularly valuable when future exposure tools provide greater flexibility in programmable source control. Such capabilities can be explored in a preliminary way by using programmed multi-scans to compose optimized compound sources with e.g. multiple poles or annular elements.

A Pixel-based sub-resolution assist feature (SRAF) insertion technique has been considered as one of the promising solutions by maximizing the common process window. However, process window improvement of the pixel-based SRAF technique is limited by the simplification of SRAFs for mask manufacturability. Mask simplification and mask rule check (MRC) constraints parameters for pixel-based SRAF technique are the critical factors for mask production without a big loss of its benefit. In this study, correlation of MRC control was analyzed in terms of the robustness to process variation for a contact layer of 32nm device node. An optimum condition of MRC constraints was selected by balancing the process window and mask manufacturability. In addition, a novel and practical methodology for 32nm device node development was proposed to keep the mask complexity low and to take full advantage of process window improvement using pixel-base SRAF insertion.

Double patterning (DP) technology is one of the main candidates for RET of critical layers at 32nm hp. DP technology is a strong RET technique that must be considered throughout the IC design and post tapeout flows. We present a complete DP technology strategy including a DRC/DFM component, physical synthesis support and mask synthesis. In particular, the methodology contains: - A DRC-like layout DP compliance and design verification functions; - A parameterization scheme that codifies manufacturing knowledge and capability; - Judicious use of physical effect simulation to improve double-patterning quality; - An efficient, high capacity mask synthesis function for post-tapeout processing; - A verification function to determine the correctness and qualify of a DP solution; Double patterning technology requires decomposition of the design to relax the pitch and effectively allows processing with k1 factors smaller than the theoretical Rayleigh limit of 0.25. The traditional DP processes Litho-Etch-Litho- Etch (LELE) [1] requires an additional develop and etch step, which eliminates the resolution degradation which occurs in multiple exposure processed in the same resist layer. The theoretical k1 for a double-patterning technology applied to a 32nm half-pitch design using a 1.35NA 193nm imaging system is 0.44, whereas the k1 for a single-patterning of this same design would be 0.22 [2], which is sub-resolution. This paper demonstrates the methods developed at Mentor Graphics for double patterning design compliance and decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. It also demonstrates verification solution implementation in the chip design flow and post-tapeout flow.

SRAF insertion through inverse microlithography methodologies has been explored at length in recent years as one of the most promising approaches to determining the right placements of Model-based SRAF (MBSRAF) for complex two dimensional geometrical configurations for advanced nodes. This work will discuss the latest development of MBSRAF insertion software at Mentor Graphics. The software system operates on the principles of inverse methods of microlithography or pixel inversion. The ability to examine the image of every pixel in the work region as well as the mathematical solution to synthesize the mask shapes as a cost minimization problem make it possible to reliably deal with SRAF insertion for advanced illumination schemes such as quasar, dipole and cross-quad. Pixel inversion involving high transmission attenuated PSM as well as hard PSM will be also discussed. We will also report on the MRC capability to make the pixel inversion mask shapes manufacturable.

The imaging of Contact Hole (CH) layouts is one of the most challenging tasks in hyper-NA lithography. Contact Hole layouts can be printed using different illumination conditions, but an illumination condition that provides good imaging at dense pitches (such as Quasar or Quadrupole illumination), will usually suffer from poor image contrast and Depth of Focus (DOF) towards the more isolated pitches. Assist Features (AF) can be used to improve the imaging of more isolated contact holes, but for a random CH layout, an AF placement rule would have to be developed for every CH configuration in the design. This makes optimal AF placement an almost impossible task for random layouts when using rule-based AF placement. We have used an inverse lithography technique by Mentor Graphics, to treat a random contact hole layout (drawn at minimal pitch 115nm) for imaging at NA 1.35. The combination of the dense 115nm pitch and available NA of 1.35 makes the use of Quasar illumination necessary, and the treatment of the clip with inverse lithography automatically generated optimal (model-based) AF for all geometries in the design. Because the inverse lithography solution consists of smooth shapes rather than rectangles, mask manufacturability becomes a concern. The algorithm allows simplification of the smooth shapes into rectangles and greatly improves mask write time. Wafer prints of clips treated with inverse lithography at NA 1.35 confirm the benefit of the assist features.

Sub-resolution Assist Feature (SRAF) insertion is one of the most important Resolution Enhancement Techniques (RET) for the 65 nm, 45 nm nodes and beyond. In this paper, we are proposing a novel approach for the optimum placement of 2D SRAF structures using state of the art Calibre RET flow. In this approach, the optimal SRAF shapes are achieved simultaneously during the OPC step. The SRAF and main features are optimized to account for their edge placement and process window metrics (aerial image slope/contrast, out of focus/dose EPE, etc...). The resulting mask shapes deliver some of the properties that can be obtained using the Inverse Lithography Techniques (ILT), such as excellent Process Window Performance, while there is almost no impact on the runtime. The implemented model-based optimization flow remains compatible with the current OPC production flows.

The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k1 for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k1 for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

This paper presents the application of double exposure alternating phase shift mask (APSM) lithography to the 65nm node gate layer. An integrated approach involving optimization of the layout design rules, APSM synthesis, Optical Proximity Correction (OPC), mask manufacturing process, and wafer patterning process has been employed to scale gate layer critical dimensions from the 90nm node to the 65 nm node with no loss in focus or exposure process window. The paper focuses on some of challenges for achieving a production-worthy APSM solution, including discussions of APSM flow development along with aspects of OPC model calibration, OPC performance, CD control, and OPC validation. Patterning results from the application of APSM to the gate level of a state-of-the-art 65nm node random logic technology are presented.

Selective strong phase shift mask techniques, whereby a phase-shift mask exposure is followed by a binary mask exposure to define a single pattern, present unique capabilities and problems. First, there is the proper exposure balance and alignment of the two masks. Second, there is the challenge of performing optical proximity correction that will account for two overlaying exposure models and masks. This is further complicated by the need to perform multiple biasing and adjustments that are often required for development processes. In this paper, we present results for applying a new OPC correction technique to a dual exposure binary and phase-shift mask that have been used for development of 100 nm CMOS processes. The correction recipe encompasses two models that were anchored to optimized processes (exposure, NA, and ?). The correction to the masks also utilized boolean techniques to perform selective biasing without destroying the original hierarchical structure. CMOS technology utilizes isolation with pitches of active device regions below 0.4 ?m. The effective gate length on silicon is in the range of 0.08 to 0.18 ?m. Patterning of trench openings and gate regions are accomplished using deep-UV lithography.

In this paper we analyze selective alternating PSM synthesis and OPC modeling parameters, taking into account lithographic constraints to PSM conformance. The results shown include phase and trim regions size and shape impact on the images printed on wafers at optimum conditions and through focus, at ideal as well as in the presence of errors in phase and transmission due to mask manufacturing.

The critical dimension (CD) tolerance specifications for masks have not only been required to keep up with the unrelenting drive of downscaling and a shift from 5X to 4X reticles, but will soon have to deal with lithographic magnification of mask CD errors. Nonlinearities in both the imaging system and resist response will exacerbate CD errors in the mask. A pupil filtering technique has been proposed to reduce the optical component of mask error magnification, but this is only effective for dense features. This paper describes a possible method of reducing the effect of mask CD errors for isolated features. Sub-resolution assisting features or outriggers are used to reduce proximity effects and to improve the depth of focus of isolated lines. We have demonstrated that correlated errors in lines and associated outriggers can reduce the impact of mask CD errors. The experiments used to verify this effect in 248 nm lithography also demonstrated nonlinearity in the resist that increased the mask error magnification.

We study the optical proximity effect and its correction using empirically derived models for DUV lithography taking into account random process variations. The sensitivity of corrected configurations to different sources of process variation (exposure dose, defocus) is evaluated. For correction at a centered condition (optimum dose, zero defocus), problems may arise in ill-conditioned areas (inside corners of T-shape features, butting line-ends, etc.), when going away from the best focus and/or exposure dose, within the exposure/defocus window. Correction for sharp corners (aggressive correction) shows a stronger sensitivity to defocus than less corner sharpening (conservative correction). Furthermore, we study what types of design configurations tend to print poorly with process variations and investigate alternative correction optimization schemes that stabilize the printing performance in such areas. Various optimization alternatives to improve performance within the process window are evaluated.

Optical proximity effects (OPE) are narrowing the process window in the 0.25micrometers - 0.18micrometers CD range. Hence optical proximity correction (OPC) might be required. These proximity effects and correction strategies are studied in detail in this work. First, an evaluation methodology is derived for the three types of OPE (linewidth differences with pitch, end-of-line effects and corner rounding). Hence, the influence of various parameters on OPE is investigated for negative tone and positive tone resists, since clear differences exist in OPE for dark field and bright field masks. Linewidth differences with pitch are small for negative tone resists, end-of-line effects are less pronounced for positive tone materials. Obviously, optical parameters have an important influence on OPE. Also, loading effects during etch processes deserve attention. Aerial image based proximity correction is evaluated. With respect to CD variations with pitch, important improvements are obtained for some resists, but not for all materials. End-of-line effects and corner rounding are improved by the use of OPC in all our experiments. Superior proximity correction results are expected with the expansion of aerial image based OPC by implementation of resist models.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We present a description of a software tool and a methodology for easily creating photoresist development rate parameters in lithography simulation. The tool optimizes parameters using the modified simplex method. The methodology uses the tool to provide insight into the effects of the development rate parameters and to find usable parameters quickly. The reasoning behind the methodology are discussed as well as advantages and disadvantages. Results from three different lithography simulators are shown to agree well with experimental cross-section SEM data.

In the recent past, scaling of semiconductor fabrication systems has been dominated by wavelength and numerical aperture modifications. This is now no longer the case for 193-nm immersion projection lithography (193i) systems as there are no technical paths for continued benefit from the in these areas. Instead, a range of techniques including patterning processes and system optimization are being used to push the limits of the system. This paper will review the elements that are now driving scaling for a system of fixed wavelength and numerical aperture.

Inverse lithography technology (ILT) is a procedure that optimizes the mask layout to produce an image at the wafer with the targeted aerial image. For an illumination condition optimized for dense pitches, ILT inserts model-based subresolution assist features (AF) to improve the imaging of isolated features. ILT is ideal for random contact hole patterns, in which the AF are not at intuitive locations. The raw output of ILT consists of very complex smooth shapes that must be simplified for an acceptable mask write time. It is challenging for ILT to quickly converge to the ideal pattern as well as to simplify the pattern to one that can be manufactured quickly. ILT has many parameters that effect process latitude, background suppression, conversion run time, and mask write time. In this work, an optimization procedure is introduced to find the best tradeoff between image quality and run time or write time. A conversion run time reduction of 4.7× is realized with the outcome of this optimization procedure. Simulations of mask write time quantify the ability of ILT to be used for full chip applications. The optimization procedure is also applied to alternate mask technologies to reveal their advantages over commonly used 6% attenuated phase shift masks.

One form of optical proximity effect that further complicates lithography is the unexpected response of the printed image to small perturbations [critical dimension (CD) errors] in the reticle. In this way mask CD errors are actually magnified (they are reduced by less than the reduction factor of the optics) during the optical transfer to the wafer. This effect will require even tighter specifications for mask CD control when the error magnification factor is significantly above unity. The effect is particularly pronounced for tight pitches of small features, but can also impact the printing of small isolated lines. Both resist and optical nonideal responses are involved in this mask error factor (MEF). This article discussed the optical effects that produce the MEF. This article will show where the MEF due to optical effects can be ignored and where they cannot when using 248 nm lithography with a high numerical aperture (NA) tool. We will demonstrate how the NA, partial coherence, and variations in foc...

We present the characterization of optical proximity effects and their correction for 0.18 μm deep-ultraviolet (UV) lithography processes using a semiempirically derived “behavior” model. Since critical dimension (CD) measurement data for deriving the model are taken after resist pattern transfer into the underlying layer (α-Si), the model incorporates all of the different proximity effect contributors: optics, mask, resist bake, etching, etc. The modeling technology we use allows for user defined model forms. It was empirically determined that the CD behavior could be adequately described by the diffusion of the aerial image with one Gaussian, and an adjustment to the signal threshold based on signal slope. The validity of the model for random geometry was confirmed by comparing contours drawn on Prospector™ with two-dimensional configurations of the uncorrected and corrected parts of a 0.18 μm test circuit. The model is then used for proximity effects correction of the gate level of a 0.18 μm test desig...

This paper describes the performance of various optical proximity correction (OPC) software packages in terms of correction accuracy and effectiveness. Although parts of these software packages have been made commercially available couple of years ago, their performance keeps improving by the new features and capabilities added continuously in time by the software vendors. In this study we address mainly the lithographic performance of the OPC techniques implemented in the software packages, including many of the new features which are still in a development phase. Corrections using one of these software packages were carried out for an advanced sub-0.3 µm i-line process after poly-Si etching. Corrections for an advanced 0.2 µm deep-UV process were carried out using two other OPC software packages, representing two different OPC techniques. Exposures were carried out on state-of-the-art i-line and deep-UV steppers equipped with high numerical aperture lenses and illuminators allowing the user to vary the coherence factor by keyboard control. Optimized optical settings towards reducing optical proximity effects have been used. Results on the effectiveness of reducing linewidth variation and line-end shortening for various pitches using these OPC techniques are reported.

We present the characterization of optical proximity effects and their correction in deep‐UV lithography using an empirically derived model for calculating feature sizes in resist. The model is based on convolution of the mask pattern with a set of kernels determined from measuring the printed test structures in resist. The fit of the model to the measurement data is reviewed. The model is then used for proximity correction using commercially available proximity correction software. Corrections based on this model is effective in restoring resist linearity and in reducing line‐end shortening. It is also more effective in reducing optical proximity effects than corrections based only on aerial image calculations.

This article describes the performance of available deep‐ultraviolet (UV) resists for electron‐beam direct‐write lithography applications. Shipley XP9402, JSR KRF‐K2G, and JSR KRF‐L7 positive resists were evaluated for dark‐field layers and Shipley XP90166 negative resist for clear‐field layers. We investigate in detail the resolution capability, sensitivity, exposure latitudes and proximity, and postexposure delay (PED) time stability for isolated and dense features, as well as for contact holes. The influence of baking conditions on resolution and stability will be described. PED time effect in air and vacuum is measured for features with dimensions down to 0.2 μm. No linewidth variations are observed down to 200 nm feature size with XP9402 for delay time of 1 h in air if the postexposure bake (PEB) is done at low pressure in He ambience. Feature sizes down to 0.25 μm are kept within ±10% of the coded size, for a PED in air of 90 min if the PEB is done using a conventional hot plate in air. A process fo...

Optical lithography is still the preferred technology for semiconductor volume production. The wavelength reduction cannot keep up with the pace of decreasing feature sizes. As a result, printing occurs closer and closer to the resolution limit of the projection tools, inducing severe proximity effects. In this paper, an overview of three automated optical proximity correction packages is given. Correction accuracy as well as mask making feasibility are touched upon. An attempt is made to predict the need for OPC in the optical lithography roadmap. It is expected that OPC will be needed to push the 248 nm lithography down to 0.18 micrometer, while it can then further be used to push 193 nm lithography down to 0.13 micrometer.