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Process flows for memory stacking or other heterogeneous integration schemes benefit from die bonding on a thinned silicon wafer 100 μm or less. In scenarios where a thinned device wafer contains features such as microbumps or Cu pillars, a carrier and temporary bonding material (TBM) facilitate the support of the fragile landing wafer during thermocompression bonding (TCB). The landing wafer in this case is vulnerable to deformations including loss of die planarity, Si bulging, Si or low k dielectric cracking, and damage to the underlying device wafer topography. In this paper, a dual layer system for temporary bonding is presented that maintains the integrity of a thinned device wafer during and after TCB. This is achieved with TBM materials which do not reflow at typical TCB conditions. The approach is to simulate TCB conditions which demonstrate the performance between different underlying TBM materials. A method which tracks the bond head z-axis over time during a TCB cycle is described which in turn yields information on the degree of temporary substrate deformation due to TCB force and temperature. The experiments include a worst-case scenario of multiple TCB cycles in the same position to mimic multi-die stacking. Finally, the impact of process conditions on Cu pillars with solder caps embedded in a thinned wafer bond line will be discussed.

For die-to-wafer (D2W) stacking of high-density interconnects and fine-pitch microbumps, underfill serves to fill the spaces in-between microbumps for protection and reliability. Among the different types of underfill, nonconductive film (NCF) has the advantages of fillet and volume control. However, one of the challenges is the solder joint wetting. An NCF must have good embedded-flux activation to mitigate Cu UBM pad oxidation due to the repeated TCB cycles that accelerate oxidation on neighboring dice. The flux in the NCF also helps in wetting the solder bumps. To realize efficient solder wetting, one must also understand the NCF deformation quality, which is a function of its viscosity. This parameter has direct impact on the deformation of solder bumps. High-viscosity NCF would be difficult to deform, thus preventing solder contact to pad during TCB reflow temperature. High bond force is required and could lead to reduced alignment accuracy. For a low viscous NCF, it requires low bond force. Solder joint wetting is a challenge with excessive squeezeout due to fast and instantaneous deformation. We seek to demonstrate in this article a creative methodology for NCF material characterization, considering the factors of NCF viscosity, deformation, and solder squeezeout. We use TCB tool position-tracking data to define the deformation curve of the NCF as a function of temperature and time at very fast profile of TCB. We use the NCF viscosity curve as reference in relation to the actual deformation, and predict dynamic deformation in three different configurations. Deformation test configurations were performed on chips with and without microbumps bonded with a rigid flat glass surface and with a bottom Cu UBM pad. The experiments were performed with different heating ramp rates at target above Sn reflow of ~250°C interface temperature. As validation, we applied the optimized TCB process (force, temperature, and ramp rate) on a test vehicle with 20 and 40 μm pitch daisy chains and obtained very good connectivity with good joint and IMC formation.

Direct wafer bonding is getting a standard and essential process in high density 3D integration devices. In this study, we investigated impact of direct bonding interface and extremely thinned Si on dicing and thinning processes. By comparing single wafer and direct bonded wafer having extreme thinned Si on top, bigger frontside chippings are observed after dicing for the case of direct bonded wafer. However, cross-sectional images unveil that the initiated point of the chipping is at the interface between SiCN and SiO2, not at the bonding interface. It indicates that direct bonding interface and 5 μm Si are not the root-cause of the chippings. For the backside thinning process, comprehensive analysis including atomic scale vacancy measurement/observation and macro level roughness/morphology analysis are executed. The major impact on die strength was given by macro level roughness. Despite having bigger chipping on bonded wafer, higher die strength is obtained from bonded wafer. It might be due to the stress buffering caused by bonding interface.

Three-dimensional circuit integration in vertical stacking attracts significant attention as a promising technique to fabricate higher performance and multifunctional chips without current 2D scaling limitation. Generally, the 3D integration using micro bumps consisted of solder joints hold the major integration scheme. However, micro bumps using solders joints confront stacking issues in the case of finer pitch (> 2µm) due to misalignment during thermal compression bonding. The wafer-to-wafer (W2W) hybrid bonding system can be then introduced as one of the state-of-the-art techniques in the 3D integration scheme. In this bonding scheme, two different bonding combinations are established simultaneously, which are Cu-to-Cu and dielectric-to-dielectric, respectively. For these bonding structures, dielectric material adjacent to Cu is required as not only an insulator but also a mechanical factor to withstand the grinding process for further 3D integration. Silicon carbon nitride (SiCN) compound has aroused great interest for bonding dielectrics due to high thermal stability and strong bond strength for direct bonding as well as Cu diffusion barrier ability. Recently back-to-face W2W hybrid bonding using backside SiCN deposition are also challenging to DRAM applications. However, in the case of DRAMs stacking, SiCN W2W direct bonding must be processed at lower temperature (350°C). In the past, we have reported that low temperature bonding using SiCN film deposited at 370°C obtained more than 2.0 J/m2 of adhesion energy at 250°C of post annealing temperature. However, W2W direct bonding using SiCN film deposited at lower temperature ( In this study, properties of W2W direct bonding with SiCN deposited at varied temperature are evaluated. Chemical and mechanical properties of SiCN film linked to the bonding quality are fundamentally studied by using specific measurements. The SiCN films were deposited by plasma enhanced chemical vapor deposition (PECVD) at specific temperature 200°C and 370°C. After deposition, these wafers were annealed in a 10% H2/N2 atmosphere at a temperature of 200°C. CMP with typical barrier metal slurry and pad was employed to flatten SiCN surface. Subsequently, the wafer surface was activated by using N2 plasma and rinsed in deionized water. Wafers were finally bonded at room temperature in the EVG GEMINI system. Different characterization techniques have been used to understand the layer quality of the SiCN film deposited at 200°C (which indicated as SiCN 200°C in the text) in comparison with the optimized SiCN deposited at 370°C (indicated as SiCN 370°C). Bond energies for the different wafer pairs have been calculated by using the blade insertion method. The highest bond energy ~ 2.3 J/m2 was obtained in the case of SiCN 370°C, while the bond energy for SiCN 200°C was ~ 1.4 J/m2. ERD observed the elemental composition in bulk for SiCN 370°C and 200°C, respectively (Table 1). It is found that SiCN 200°C is not pure SiCN as SiCN 370°C but it is characterized by the presence of oxygen into the bulk. Oxygen could come from absorbed moisture since deposition and annealing steps are including no oxygen resources. FTIR and XPS were carried out to clarify the chemical components of SiCN 370°C and SiCN 200°C (Figure 1). FTIR spectra of SiCN 200°C is compared with the spectra of SiCN 370°C in Figure 1(a). The broad peak 3100 – 3500cm-1 is assigned to N-H and O-H components, the last one due to moisture absorption from air ambient. A peak at ~1160 cm-1 can be assigned to NH3. This assignment is confirmed through XPS measurements where NH3 peak is detectable in the N1s peak (Figure 1 (c) right) while no NH3 peaks can be detected from the as-deposited SiCN 370°C (Figure 1(b) right). Such observation is suggesting the presence of residue of deposition precursors in the SiCN 200°C. In the Si2p peak of XPS spectra of Figure 1(c), it is observed that SiCN 200°C is characterized by less Si-C bonds compared to the SiCN 370°C as-deposited film. mainly Si-O bonds can be observed in the case of SiCN 200°C after N2 plasma while main peaks didn’t change from CMP for SiCN 370°C (Figure 2). The fact that in the as-deposited SiCN 200°C we do not have Si-C bonds is pointing to a missing desired property for the material since it was demonstrated that Si and C dangling bonds are essential in the process of enhancing bond energies. Figure 1

For die to wafer bonding of high-density interconnects and fine pitch microbumps developing and characterizing suitable underfill materials are required. In general, underfill serve to fill the spaces in-between microbumps for protection and reliability. Among the different types of underfill, Non-Conductive Film (NCF) has the advantages of fillet and volume control, and a built-in flux to aid wetting. However, challenges arise for thin dies and microbumps with fine pitches on film lamination, voiding, transparency, filler percentage, dicing compatibility and most importantly, deformation behavior and possibility to improve solder joint wetting. In a Die-to-Wafer D2W stacking with a Sn solder bump interconnect to Cu UBM, concern is high on the Cu pad oxidation due to the repeated TCB cycles that accelerate oxidation on neighboring dies. Process mitigation is needed to help reducing the oxidation. But even so, an NCF must have good embedded flux activation. Another main factor for an NCF to have efficient TCB process with good solder joint wetting, is the NCF deformation quality in which is a function of its viscosity. This parameter has direct impact on the deformation of solder bumps. High viscosity NCF would be difficult to deform, thus preventing solder contact to pad during TCB reflow temperature. High bond force is required and could lead to reduced alignment accuracy. Filler entrapment is also a subsequent concern for high filler loading, high viscosity NCF. For a low viscous NCF, careful attention in process characterization is needed in TCB with low bond force. Solder joint wetting is a problem with excessive squeeze-out due to fast and instantaneous deformation. With low viscosity, not only the bond force applied should be low, but the deformation behavior should also be understood to enable an effective NCF. We seek to demonstrate in this paper a creative methodology for Non-Conductive Film (NCF) material characterization, considering the factors of NCF viscosity, deformation, and solder squeeze-out. Characterizing NCF viscosity at fast TCB profiles is challenging considering deformation behavior of both the NCF itself and the solder bumps that shaped the solder squeeze-out and wetting. Furthermore, in this paper we use TCB tool position tracking to define the deformation curve of NCF film as a function of temperature and time at very fast profile of TCB. We use material viscosity curve as reference in relation to the actual deformation, and predict dynamic deformation based on Reynold’s equation within TCB profile duration. The experiments were performed with different heating ramp rates at target above Sn reflow of ~250C interface temperature. The deformation analysis is not limited to thin film sandwiched between parallel plates. Deformation test was performed on chips with and without microbumps and with rigid flat glass surface and its combinations. Deformation of underfill is recorded in the readout of TCB tool. As validation, we applied the optimized TCB process (force, temperature, and ramp rate) on a test vehicle with 20 and 40um pitch daisy chains and obtained close to 95% electrical yield with good joint and IMC formation. The cross-section SEM images show good wetting, revealing good activation of built-in flux when the optimized TCB profile was used.

Direct Cu-SiCN hybrid bonding is successfully realized by using a thermal budget of 250 °C. The excellent results should be attributed to the tight control on the different processing steps but also to the properties of the SiCN dielectric used as bonding material.

Laser debonding is assessed as an alternative to mechanical peel debonding in a collective hybrid bonding flow. Potential risks associated with the laser, such as the UV-photon energy, thermal energy and mechanical/acoustic energy are evaluated both on dummy wafers as on electrically yielding device wafers. It is shown that the laser ablation of a so called laser release layer generates an acoustic shock wave that in the case of ultra-thin dies can lead to die damage and thus a lower transfer yield. A model is proposed and based on it and an ‘acoustic layer’ is added to the flow which is successful in preventing this type of damage. The influence of this additional layer on the established bonding process of reference is assessed in detail. A 100% die-transfer yield with an average sub 150 nm die-to-target-wafer alignment yield is achieved.

A key factor enabling the reduction of the thermal budget in W2W bonding integration flows is the activation sequence, consisting of cleaning and plasma treatment, used before bonding. For hybrid bonding such activation sequence needs to be selected to fulfill multiple functions: activation of the dielectric bonding surface to obtain a high bonding energy during room temperature bonding, minimize the dielectric bonding annealing temperature while avoiding exposed Cu oxidation and reducing the required annealing temperature for proper Cu-to-Cu bonding. In this paper we discuss the effect of different wafer clean methods (Deionized (DI) water and citric acid) and the effect of different plasma treatments on SiCN and Cu surfaces before bonding. The characterization techniques used include XPS, TEM, ellipsometry, SAM, OES and wafer-to-wafer bond strength testing. It is observed that Nitrogen plasma treatment can help in reducing the CuOx and a mild passivation effect of the surface is observed. Whereas on the Cu pads citric acid, used just before bonding, appears a good option, since clear effectiveness in reducing the CuOx is observed, on the dielectric it may leave some residues which can result sometimes in bonding defects. Moreover, a metric to evaluate efficient SiCN-SiCN bonding is proposed and further understanding of the physical mechanisms involved in SiCN-SiCN bonding are suggested.

In this paper, a collective hybrid bonding of a die to wafer integration using glass wafer is demonstrated. The key process steps such as thinning on glass, carrier preparation, CMP die population and wafer to wafer bonding are discussed. Die to wafer bonding yield of 90% is shown. Promising electrical yields of more than 80% are obtained on daisy chains (219 pads connections) on pitches ranging from $7\mu\mathrm{m}$ to $40\ \mu\mathrm{m}$ .

ispartof: ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY vol:8 issue:6 pages:P346-P350 ispartof: location:MEXICO, Cancun status: published

Double gated WS 2 transistors with gate length down to 18 nm are fabricated in a 300mm Si CMOS fab. By using large statistical data sets and mapping uniformity on full 300mm wafer, we built an integration vehicle where impact of each process step can be understood and developed accordingly to enhance device performance. In-depth analysis of V T variability reveals multiple possible sources at different length scales, with the most prominent one being the channel material. The work presented here paves the way towards industrial adoption of 2D materials.

Silicon carbon nitride (SiCN) compounds have aroused great interest as dielectric materials for direct bonding because of the high thermal stability and high bond strength, as well as its Cu diffusion barrier properties. While wafer-to-wafer direct bonding, including the dielectric deposition step, is generally performed at high temperature (>350 °C), applications such as heterogeneous chips and DRAMs would require wafer-to-wafer direct bonding at lower temperature (

Integration of 2D-materials brings a new set of challenges to a 300 mm Si CMOS fab. We have opted for double gated WS 2 transistors as test vehicle with transition metal dichalcogenides as channel. Moreover, we explore two different routes within a modified industry standard flow, differentiating in channel deposition method either by direct deposition or via layer transfer. The integration flow mitigates the constraints of high surface sensitivity and low adhesion for these materials. Device performance of I on /I off up to 107 is achieved and WIW mapping is obtained opening the route for further process understanding.

In this paper, a collective hybrid bonding of a die to wafer is demonstrated. The key integration steps such as CMP, wet etch, cleaning, defect metrology, alignment optimization in die to wafer and wafer to wafer bonding tools are discussed in detail. Finally void free Cu to Cu and SiCN-SiCN connection is shown in this paper. Promising electrical yield more than 85% is obtained for the daisy chains containing 219 pad connections.

In this paper, spacer bumps concept is introduced to increase the process window for TCB, lower the sensitivity of electrical yield to bump height variation, maintain the gap between two dies and to prevent too much solder deformation for a test vehicle having multi-diameter bumps from 40um down to 5um pitches. Adding spacer bumps improves the electrical yield dramatically to close to 100% and ensures having good solder joint and IMC formation for both face to face N=2 and back to face N=4 stacks.

Current roadblocks within the collective die-to-wafer bonding flow, limiting die-transfer yield and throughput, are identified and discussed. Based on the obtained assessment a new carrier system is introduced. The use of the ultra-soft and highly-UV-transparent BrewerBOND® C1301 material and its compatibility with BrewerBOND® 701 laser release material, which is coated on top of ultra-thin dies, allows for a room temperature, ultra-low force collective bonding with laser-assisted die transfer sequence.

Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5–2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in between grinding and dry etch it is possible to significantly reduce not only the roughness, but also the remaining vacancies at the subsurface. The surface of grinding + CMP + dry etching gives an equivalent mono vacancy result as to that of grinding + CMP. This combination of thinning processes allows development of extremely thin 3D integration devices with minimal roughness and vacancy surface.

The impact of the edge trimming process on permanently bonded wafers is described. The edge trimming process is a blade sawing process applied on the Si wafer edge and bevel, removing the fragile edge of the wafer prior to grinding. We investigated two routes for the integration on permanently bonded Si wafers, edge-trim before bonding and edge-trim after bonding. The impact on the subsequent processes for both integration routes is assessed. For the case of edge-trim before bonding, a combination of functional water cleaning such as ozone dissolved in water and ammoniac scrub cleaning shows a significant effect to remove Si residues, enabling void free dielectric bonding. For the case of edge-trim after bonding, utilizing a small grit diamond blade shows no mechanical failures into the dielectric bonding interface. These proposed processes are a very promising for the fabrication of extreme thinned Si without mechanical failure at wafer edge.

Thin substrate handling has become one of the cornerstone technologies that enabled the development of 3D stacked ICs over the past years. Temporary wafer bonding has continuously improved and reached the maturity level required by volume manufacturing of first-generation devices. Yet the need remains for further development and performance increases. Indeed, the continuous push for denser interconnects has brought new requirements for a through-silicon-via technology on one side but also pushed temporary adhesive and carrier technology into the space of wafer reconstruction and fan-out WLP. On the opposite side of the semiconductor spectrum, at the early steps of the front-end-of-line processing, transistor scaling becomes more and more challenging, including demanding the integration of higher numbers of novel materials. To further increase the options of materials, a growing number of exploratory devices are considering using a layer transfer approach. The advances in temporary bonding and debonding technology is bringing the packaging and nanoscale world together.

Blade dicing compatible particle protective layer is investigated for feasibility study of collective Die-to- Wafer (D2W) direct bonding. Having the compatibility to blade dicing, the protective layer needs to be insoluble for de-ionized water (DIW), because blade dicing requires cooling water to maintain the cutting performance. Therefore, polymers soluble in alkaline solutions (e.g. TMAH, NH 4 OH), however, insoluble in DIW are tested for collective die to wafer direct bonding. With the dicing particle protective layer technology, successful collective die to wafer direct bonding with current die assembly tools are achieved. The alternative protective layer ensures high yield and cost of ownership for collective die to wafer integration

Next-generation temporary bonding adhesive material is introduced into imec's high interconnect density flip chip on fan-out wafer-level package (FC FOWLP) concept [1], [2]. After molding on silicon substrates, an ultralow die shift with an average of $ die-to-carrier mismatch and warpage of $ were achieved in a full 300-mm wafer. These values are orders of magnitude improvement over results reported in literature and has major implications on the processing of overmolded substrates. The combination of this low warp and ultralow distortion opens the possibility for fine-pitch RDL combined with a chip-first approach, which was impossible until now. The evolution of warpage and die shift through multiple processing steps will also be discussed in this paper.

In this paper a novel solder-based die-to-die or wafer-to-wafer interconnect approach is introduced. This technique allows for microbump interconnects with different diameters on a single die and allows for pitch scaling down to 5μm A metal damascene process is used to create the metal pad layers for soldering. Solder μm bumps are created by semiadditive electroplating. After embedding the solder u bumps in a partially cured polymer, the wafer surface is planarized and the solder surface is exposed. This results in flat die surfaces of the die before bonding. Using a thermo-compression bonding process these flat surfaces can be aligned, the solder reacts with the metal pad to form a solder joint and the polymer can bond and cure to ensure a void less underfill layer for mechanical strength and increased reliability. The selection of suitable metals and polymers as well as the different process steps together with reliability data will be discussed in detail. Electrical yield and quality of bonding is demonstrated using imec 5μm pitch PTCU/W test vehicle for die to wafer bonding.

The recent developments of wafer-to-wafer bonding technology based on direct assembly of inorganic dielectric materials is offering a path for the continuous need for higher integration density and lower interconnect pitches. However, numerous applications could benefit of a higher degree of design flexibility offered by a die-to-wafer approach. The achievement of high yielding die-to-wafer bonding with micron range die overlay is an essential element to unlock the potential of heterogeneous integration.

Nowadays, the direct bonding process is embedded in a BEOL manufacturing process where the maximum temperature is 400C. For certain applications there is the need to lower such thermal budget. One of the first process steps which will be modified will be the bonding layer deposition step as well as the densification step. It is known that by lowering the deposition temperature the quality of the dielectric will be decreased as well. This change will have a direct consequence on the bonding process which relies on the quality of the dielectric. It is found that if we use a post bond anneal temperature which exceeds the densification temperature voids originate at the bonding interface. By means of FTIR studies and ERD analysis the origin of the voids is tentatively ascribed to H or H related species. These findings provide a basic understanding on how to tune the deposition condition to select a proper low temperature dielectric which will enable us to obtain a good bonding uniformity and a good bond strength for the described application.

As the need for higher degrees of function integration on chips continues to rise, chip-to-chip connection density exponentially increases. The continuous push for denser interconnects has brought conventional FO-WLP to its limit. A novel FO-WLP concept has been proposed to enable 20-µm pitch interconnect chip-to-chip. To achieve this density and to further scale it down, a critical element is ultra-precise die-to-die positioning in the micron range. Advances in temporary bonding materials and carrier systems are required to enable such applications.

Feasibility study of alternative dicing technologies for collective die to wafer direct bonding combined with wafer to wafer direct bonded dies has been performed. Several dicing technologies such as blade dicing, laser grooving + plasma dicing, laser grooving + stealth dicing and laser grooving from backside were evaluated for this integration scheme. For the case of blade diced dies, the collective die to wafer direct bonding are not succeeded. This was due to particle interruption, caused by remaining particles from dicing. For the case of laser grooving + plasma dicing and laser grooving from backside, successful die to wafer direct bonding were observed. However, the die edge was not bonded for the case of laser grooving + stealth dicing. This was attributed to the occurrence of the laser recast caused during laser grooving. Based on the characterization of dicing techniques for this approach, we have achieved successful integration of collective die to wafer bonding combined with wafer to wafer bonded dies.

Wafer warpage is a big challenge during wafer process in Fan-Out Wafer-Level-Packaging (FOWLP). It is crucial to keep warpage low as much as possible for successful process integration. The warpage is mainly due to the Coefficient of Thermal Expansion (CTE) mismatch between the involved materials during temperature changes. Furthermore, warpage of molded wafers depends on material properties. Therefore, accurate material characterization has great importance. In this paper, thermal-mechanical properties of the used polymeric materials were measured using nanoindentation and Stereo-Digital Image Correlation (SDIC). In this study, warpage of molded wafers with and without Temporary Bonding Adhesive (TBA) is investigated during heating to 200°C and cooling down to room temperature. SDIC technique was used to measure the warpage of molded wafers. Finally, Finite Element (FE) simulations were carried out using as input the measured thermal-mechanical properties. A comparison between warpage measurements and FE simulation at different temperatures showed a good agreement.

To keep Moore's law alive, 2D materials are considered as a replacement for Si in advanced nodes due to their atomic thickness, which offers superior performance at nm dimensions. In addition, 2D materials are natural candidates for monolithic integration which opens the door for density scaling along the 3rd dimension at reasonable cost. This paper highlights the obstacles and paths to a scaled 2D CMOS solution. The baseline requirements to challenge the advanced Si nodes are defined both with a physical compact model and TCAD analysis, which allows us to identify the most promising 2D material and device design. For different key challenges, possible integrated solutions are benchmarked and discussed. Finally we report on the learning from our first lab to fab vehicle designed to bridge the lab and IMEC's 300mm pilot line.

Results are presented of recent studies in material exploration for W2W bonding and advanced W2W alignment carried out as a holistic approach to enable a robust ultra-fine pitch interconnect for 3Dsystem-on-chip (SoC) technology. Various characterization methods have been employed, including electron-spin-resonance (ESR) monitoring of dangling-bond-type defects, invoked to compare SiCN-SiCN and SiO 2 -SiO 2 bonding bonding strength in terms of the the evolution of chemical bond densities at the interface. Furthermore, sub-200 nm W2W overlay performance has been demonstrated to cope with 3D interconnect scaling and stringent contact requirements. State-of-the-art overlay performance is achieved by the enabling features of the W2W aligner while the incoming wafer characteristics are monitored. The study provides a positive outlook to 3D SoC technological realization and sub-µm pitch scaling solutions.

The diamond abrasive process which is applied onto the silicon wafer edge, the so called “edge trimming,” is an important step in three-dimensional microelectronics processing technology, due to the significant thickness reduction of the wafer after thinning. Nevertheless, the wafer edge defects caused by edge trimming have often been overlooked. Although the mechanisms of the formation of the defects in Si due to trimming may be similar to the ones caused by grinding, an in-depth study and risk assessment have not been done yet. In addition, the variety of stress relief processing options can give different morphology and defect removal behavior on the edge trimmed Si sidewall. In a first study, we used transmission electron microscopy and Raman spectroscopy to analyze the defects caused by edge trimming. We show the presence of a continuous layer of amorphous Si and of different phases of Si, caused by edge trimming. A comparison of the damage induced in the Si by two different integration schemes is also discussed. When polishing is used for stress release, the observed sidewall defects stay, since the polishing force is only applied on the top surface of the wafer. On the other hand, the damage is completely removed for the case of wet and dry etching. The surface chemical reactions occurring at the surface during these processes are also acting on the Si sidewall. These findings provide a workable edge trimming and stress relief method for permanently bonded wafers, with many industrial applications.

Thin substrate handling has become one of the cornerstone technologies that enabled the development of 3D stacked ICs over the past years. Temporary wafer bonding has continuously improved and reached the maturity level required by volume manufacturing of first generation devices. Yet the need for further development and performance increases remains. Indeed, the continuous push for denser interconnects has brought new requirements for a through-silicon-via technology on one side but also pushed temporary adhesive and carrier technology into the space of wafer reconstruction and fan-out WLP.

The rapid growth of data bandwidth required between logic and memory chips for next generation device nodes is progressively pushing low I/O count serial busses to their limits. To further satisfy this increasing need for high data rates, wider I/O count busses are now being developed and established. Over the past years, various Fan-Out Wafer-Level-Packaging (FOWLP) approaches have been developed to answer the needs mentioned above and the increasingly demanding function integration on package. Imec has been working on a novel 300mm Fan-Out Wafer-Level-Packaging concept that enables 20µm pitch interconnect density. Results from experiments demonstrates wafer bow below 500µm after molding on silicon substrate with ultra-low die shift with maximum die to carrier mismatch below 10µm on full 300mm wafers. Further warpage and die shift evolution are expected depending on the process steps the wafers must go through and will be further discussed.

Extreme thinned wafer transfer technologies have been demonstrated by combining a selected set of temporary and permanent bonding materials. The extreme thinning was performed on the backside of a top wafer bonded on carrier wafer with the temporary glue material, subsequently followed by grinding, polishing and plasma dry etching to a final thickness of 5 µm. The properties of the temporary adhesive have been selected to be compatible with a permanent thermocompression bond of the extreme thin wafer to a final target substrate. Thus, the high thermal deformation resistance of the temporary adhesive is key. As we are dealing with extremely thin substrate, the required process uniformity and total thickness variation of each material are crucial. Hence after the spin-coating, the permanent bond polymer was planarized by a surface planer process. The performance benefit brought by this process and the final transfer steps will also be discussed.

This paper presents a novel approach to face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination with direct Cu-Cu bonding using Cu pads of unequal size and surface topography for the top and bottom wafers. The use of SiCN dielectrics allows to obtain a high W2W bonding energy (> 2 J/m2) at low annealing temperature (250 °C). Excellent Cu-Cu bonding is obtained after annealing at 350 °C. A novel CMP process, resulting in a slightly protruding Cu top pad and a slightly recessed Cu bottom pad, is introduced. The difference in pad sizes, allows for the necessary W2W overlay bonding tolerances. Excellent resistivity and yield results are obtained across bonded 300 mm Si wafers for scaled 360 nm top pads bonded to 720 nm bottom pads at 1.44 μm pitch (25% bottom Cu density). Feasibility of smaller pitches has been demonstrated by successfully bonding 180 nm top pads to 540 nm bottom pads at 0.72 μm pitch.

Among the technological developments pushed by the adoption of Through Silicon Vias and 3D Stacked IC technologies, wafer thinning on a temporary carrier has become a critical element in device processing over the past years. First generation of adhesive materials enabled the integration of the first devices at the expense of capping the thermal budget. Hence new generation materials are being explored to overcome this limitation and further bring the process complexity down.

The reduction of post annealing temperature for plasma activated dielectric bonding was achieved by using SiCN as dielectrics layer. The SiCN-SiCN bonding shows higher bond energy at 250 °C as compared to conventional SiOi-SiOi bonding. The surface and interface of the SiCN bonding dielectric layers were characterized by various quantitative and qualitative methodologies. This alternative bonding dielectric allows development of extremely thin 3D integration devices with minimal thermal budget at bonding step.