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Dynamic random access memory (DRAM) is a volatile random access memory and the memory cell consists of a cell transistor and a capacitor [1–3], as shown in Fig. 5.1. The cell transistor is used to connect a storage node (N) and a data-line (DL) by activating a word-line (WL), while the capacitor, connected between N and the plate (PL), stores information. The signal charge stored in the capacitor is reduced by the leakage currents of the memory cell, and this reduction causes data loss. To avoid this, a refresh operation that will be explained later is periodically required and the refresh interval is determined by storage node capacitance (C S). The signal voltage developing on the floating DL after WL is activated is also determined by C S. Therefore, higher capacitance (>20 fF) is crucial to achieving low standby power and stable sensing operation [4].

Some solutions are proposed and evaluated by simulation after the challenges facing the creation of 0.5-V nanoscale SoCs are clarified. First, the repair techniques and nanoscale FD-MOSFETs are discussed in terms of their V t -variation. Second, 0.5-V dual-V DD dual-V t logic circuits with gate-source reverse-biasing schemes are proposed. Third, a boosted word-voltage six-transistor (6-T) SRAM cell is evaluated with a 25-nm planar FD-SOI MOSFET and then a FinFET, revealing that the FinFET drastically improves the voltage margin and speed of the 6-T cell. Finally, the feasibility of a 0.5-V 25-nm SoC comprising a 1-Gb SRAM and 160-Mgate logic block is studied. We conclude that an SoC like this with a competitive speed while reducing the power to about one-tenth that of a conventional 1-V 32-nm CMOS LSI is possible, if the above-described devices and circuits are used and the within-wafer V t -variations are stringently controlled and/or compensated for.

A novel DRAM architecture with an ultra-high bandwidth is proposed for high throughput computing. The proposed architecture employs three techniques: 1) five-stage pipelined 16-DRAM cores, 2) an early bar write scheme for an 8-ns cycle array operation, and 3) a 16-Gbit/s I/O circuit on each of 32 through-silicon-via pairs/DRAM core. We conducted a circuit simulation assuming a 45-nm 1-Gbit chip and confirmed that the proposed architecture achieved a 1-Tbyte/s bandwidth with 19.5-W power consumption.

A novel CMOS low-V T preamplifier suitable for low-voltage and high-speed mid-point sensing was developed for gigabit DRAM. This preamplifier consists of a low-V T NMOS cross couple, a low-V T PMOS cross couple and a high-V T CMOS latch. The sensing speed of the proposed preamplifier at dataline voltage of 0.5 V is 62% higher than that of a conventional preamplifier. By activating the low-V T NMOS and PMOS cross couples temporarily during write operation, writing time is 72% shorter compared to the case with the high-V T CMOS latch only. Data-line charging current of a memory cell array with the proposed preamplifier is reduced by 26% by decreasing dataline voltage from 0.8 to 0.5V.

We have fabricated a phase change memory using doped In-Ge-Te to improve the data retention required for industrial and automotive use. This chalcogenide features higher thermal stability as well as denser texture and improved adhesion. The memory cell using doped In-Ge-Te provided a larger read margin and better data retention than conventional Ge2Sb2Tes, and we demonstrated 10-year retention at temperatures above 150degC, which is the highest temperature ever reported.

Random telegraph signals (RTS) in fluctuations of threshold voltage are analyzed using massive readout data in scaled flash memories. A novel quantitative analytical method is proposed to evaluate parameters of the RTS, such as amplitudes and mean time spent in individual states. This evaluation gives us a statistical view of parameters of the RTS as well as their correlations. All of the parameters were found to follow log-normal distribution and to show weak mutual dependences. Possible origins of the distributions are discussed. We also studied evolution of RTS during program/erase operations of flash memories and point out its potential similarity with breakdown phenomena in gate oxide

A threshold voltage fluctuation (DeltaVth) due to random telegraph signal (RTS) in a floating-gate (FG) flash memory was investigated. From statistical analysis of the DeltaVth, we found an anomalously large DeltaVth at high percentage region of the DeltaVth distribution, which is caused by a complex RTS. Since the ratio of the complex RTS among the RTS is increased by charge injection to tunnel oxide, the dispersion of the DeltaVth distribution increases after program/erase (P/E) cycle. Since the DeltaVth due to the complex RTS is much larger than the simple RTS, the complex RTS become one of the reliability issues in larger capacity flash memory, especially after P/E cycle

This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory. We acquired large-scale data of Vth fluctuation and confirm the existence of the tail bits generated by RTS. The amount of Vth broadening due to the tail bits becomes larger as the scaling advances, and reaches to more than 0.3 V in 45-nm node. Thus the RTS becomes prominent issue for the design of multilevel flash memory in 45-nm node and beyond

We developed a four-transistor SRAM cell with a vertically stacked poly-silicon MOS. Its size-fabricated by using 0.13-/spl mu/m technology - is 0.78 /spl mu/m/sup 2/, that is, only 38% of that of a six-transistor SRAM cell. By optimizing the threshold voltages and the gate-oxide thicknesses of the cell transistors, and developing a modified electric-field-relaxation scheme, an estimated cell leakage current of 88.7 fA/cell was achieved. We also developed a dual-word-voltage scheme to achieve stable operation of the cell during a read operation without affecting a write operation.