1. Thermal-Aware Floorplanning Using Genetic Algorithms
- Author
-
Hung, W. L., Xie, Y., Vijaykrishnan, N., Addo-Quaye, C., Theocharides, Theocharis, Irwin, M. J., and Theocharides, Theocharis [0000-0001-7222-9152]
- Subjects
Very-large-scale integration ,Engineering ,business.industry ,Hardware_PERFORMANCEANDRELIABILITY ,Parallel computing ,Dissipation ,Chip ,Integrated circuit layout ,Floorplan ,Thermal aware ,Genetic algorithm ,Hardware_INTEGRATEDCIRCUITS ,business ,Face detection - Abstract
In this work, we present a genetic algorithm based thermal-aware floorplanning framework that aims at reducing hot spots and distributing temperature evenly across a chip while optimizing the traditional design metric, chip area. The floorplanning problem is formulated as a genetic algorithm problem, and a tool called HotSpot is used to calculate floorplanning temperature based on the power dissipation, the physical dimension, and the location of modules. Area and/or temperature optimizations guide the genetic algorithm to generate the final fittest solution. The experimental results using MCNC benchmarks and a face detection chip show that our combined area and thermal optimization technique decreases the peak temperature sufficiently while providing floorplans that are as compact as the traditional area-oriented techniques.
- Published
- 2005