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Envelope tracking is widely used to raise the efficiency of PAs. An envelope tracking supply modulator (ETSM) modulates PA's supply voltage to tracks the RF waveform's envelope, so that the PA will operate in saturation all the time. A hybrid amplifier is commonly used to realize the ETSM, which, in effect, partitions the envelope bandwidth into a low and high subband. An efficient switching buck converter tracks the low band. In parallel with it, an op-amp supplies the current in the high band. In prior arts, the hybrid amplifier is realized with feedback using a hysteresis comparator, whose output actuates the buck converter to respond to the changing envelope; the continuous-time op-amp makes up for the error. But a comparator-driven buck converter produces a slew-rate limited current that always lags the envelope waveform. This forces the op-amp to produce a larger current to correct the error, and the arrangement cannot guarantee that the buck converter switches no often than is absolutely necessary. We replace the hysteresis comparator with a novel trellis-search that, first, finds the optimal sequence to switch the buck converter to minimize the RMS current that the op-amp must deliver; second, to lower the loss from switching the capacitance of FETs, it penalizes a large number of switching events in the buck converter. Meanwhile, with a conventional on-chip hysteresis comparator, we can demonstrate ETSM operation up to 160 MHz modulation bandwidth. This is the widest bandwidth reported so far for any ETSM.

Frequency-division duplexing (FDD) radios are widely used in wireless communication standards and multi-radio coexistence. It requires that the duplexer prevent both TX signal and noise from entering the receiver front-end, while operating under full TX power. It also requires the receiver front-end circuits to be highly linear when the TX leakage channel is adjacent to the receive channel.This work describes the design of a dual-band electrical balance duplexer (EBD). The electrical balance duplexer supports dual-band TX-RX isolation for FDD operation at 5-7GHz. A network in the EBD can balance the antenna impedance (ZANT) in the TX channel and RX channel independently. The EBD provides >40dB isolation in an 80MHz channel bandwidth in the TX band (5-6GHz), for any ZANT(fTX) with VSWR≤2, and independently in the RX band (6-7GHz) when QANT≤4.3. The EBD is designed for ≤4dB RX IL and ≤3.8dB TX IL. Second, the properties of finite-Q LCR networks are derived. Simple results and derivations provide performance limits and design guidelines for the on-chip filter (two-port) and impedance synthesizer (one-port). General properties are given for the design of multi-band on-chip N-port LCR networks. Third, second-order baseband filter circuits for mixer-first receivers are designed for adjacent channel blocker tolerance. The design guidelines are given in simple expressions. The independent poles control by circuit elements is achieved. The prototype measurements verify the design. It can tolerate the maximum TX leakage from the dual-band EBD without gain compression and noise degradation. Finally, the mixer switch nonlinearity is analyzed. Expressions for IIP3 and B1dB are given, showing the impact of supply voltage, FET size, clock waveform, operating frequency and baseband load. The analysis matches the simulation very well. The dual-band EBD and the mixer-first receiver with second-order baseband filters are fabricated in 65nm RF-SOI CMOS technology. They support the F

In a wide-band RF system, the RF channel is located within 50 MHz to 9 GHz. A high-frequency resolution phase-locked loop (PLL) with 100$\%$ tuning range oscillator is the core to generate the RF carrier frequency which covers such a wide range. The phase noise and spurs of the PLL are required to be low to avoid degrading RF system performance. A PLL applies $\Sigma \Delta$ modulation to increases its resolution and is known as a fractional-N PLL, but $\Sigma \Delta$ modulation introduces considerable quantization noise into the loop. The nonlinearity of the PLL also converts part of the noise into fractional-N spurs. Noise cancellation is usually applied to eliminate this quantization noise. Calibration, often with long settling time, is necessary to maintain cancellation efficiency. Power intensive calibration is also required to notch spurious tones. In this thesis, we first investigate the delay-locked loop (DLL) and attempt to use DLL to replace PLL as an RF frequency synthesizer. An LTI model of DLL is established, which indicates the limitation of DLL as a high-performance synthesizer. Then, the thesis focuses on PLL again. A calibration-free triple-loop PLL is introduced. The merits of heterodyne PLL are rediscovered, which applies a mixer in the loop to translate the VCO frequency to a low-frequency feedback signal. By implementing the harmonic mixing concept, the designed prototype effectively reduces the pulling risk of a traditional heterodyne PLL, allowing it to be integrated on a single chip. This PLL provides higher-order noise filtering and can naturally reduce fractional-N PLL noise and spurs. An analytical model for this PLL is also presented, which allows us to fully appreciate this PLL and optimize the loop design. After this, a sub-sampling PLL-based low-noise frequency extender is introduced, which increases the tuning range of an oscillator from 30$\%$ to 100$\%$, and requires only a small chip area. By combining the triple-loop PLL and the f

Cognitive radios (CRs) use “white spaces” in spectrum for communication. This requires front-end circuits that are highly linear when the white space is adjacent to a strong blocker. For example, in the TV spectrum (54 MHz-862 MHz) broadcast transmissions are the blockers.This work describes the design of a wideband blocker tolerant receiver. First EKV based MOSFET model is used to analyze RF transconductor distortion. Expressions for its IIP3 and P1dB are also given. Derivative superposition based linearization scheme for the RF transconductor is also explained.Second mixer switch nonlinearity is analyzed using EKV. Simple expressions for receiver IIP3 and P1dB are given that provide design insights for linearity optimization. Low phase noise LO design is also described to lower receiver noise figure in the presence of large blockers.Finally, transimpedance amplifier (TIA) large-signal operation is studied using EKV. It is shown that source follower inverter-based TIA transconductor results in higher receiver P1dB.A prototype receiver based on these ideas was designed in 16nm FinFET CMOS. Measured results show that receiver can operate from 100 MHz to 6 GHz and it can tolerate up to +12 dBm blockers. Furthermore, its noise figure is only 8.9 dB in the presence of +10 dBm blocker located at 80 MHz offset.

In this work, a general theory of coupled resonators is proposed. On one hand, it provides a design-oriented analysis while also preserving rigorousness throughout the derivation; on the other hand, it uses graphical methods to offer an intuitive understanding. Using an impedance loci analysis, it then ties the above to aspects together to render an integrated body of theory.Guided by the developed theory, a robust wireless power transfer system using an oscillator driver is designed, capable of providing more than 90mW of power to a brain implant. Its maximum operating range spans 4.2cm and handles up to 40x load variations. It achieves a peak efficiency of more than 80%.Building upon this wireless power system, a novel data modulation, Load-Induced Resonance-Shift Keying (L-RSK) is implemented to transmit reverse data simultaneously with the forward regulated power, at high rate and low power, through the same pair of coils. It can support up to 5Mb/s data rate and burns negligible power (at most 0.395mW) compared with the total delivered amount.The milli-Watt level wireless power for biomedical implants can be extended to Watt level so that it can be used for charging portable consumer electronics. The scaled system can provide up to 11W power with 85% peak efficiency.Lastly, second harmonics in LC oscillators are analyzed. Analysis on the second harmonics at the output and at the tail current source of current-mode LC oscillators provides useful insights on how to improve power-conversion efficiency. Anslysis on the second harmonics in oscillators with mismatch in threshold voltages of FETs shows that flicker noise at switching FETs of an LC oscillator can be up-converted to become phase noise at the output of the oscillation.

In the past decade, there has been a great interest in bionic and neural implantable electronics to investigate the human body's working, to understand different physiological conditions, and to cure disease. Among them, neuromodulation systems have been found by the neuroscience community as a promising tool to decode the functioning of the brain, and an alternative strategy for diagnosis and treatment of neuropsychiatric disorders. Today's clinical neuromodulation systems, however, may suffer from many serious constraints. For instance, many are wired refrigerator-size electronic setups, which immobilize the patient, increase the risk of infections, and have a limited duration of operation. The next generation of neuromodulation systems should contain a robust, energy-efficient solution to deliver wireless data and power.In this work, first, we present an implantable distance-immune ultra low-power data link which would be used in a biomedical implant that most of the time relays monitoring data to a unit outside the human body. The near-field data link is based on a free-running oscillator tuned by coupled resonators. We have studied the properties of the inductively-coupled link and derive its key features and constraints. After understanding the design space, we have designed and built transceiver chips in 40 nm CMOS technology which enable a bidirectional wireless connectivity. Data can be transferred in half-duplex at up to 4 Mbps in a Load Shift Keyed (LSK) uplink, and up to 2 Mbps in an ASK downlink. With one automatic adjustment, the link can maintain a reasonable error rate of less than 10−6 (BER< 10−6) over coil separations of up to 4.5 cm.In monitoring body/brain activities, with an air data rate of 4 Mbps, this wireless link can multiplex 16b-words acquired at 0.5 kS/s from each of up to 500 neural probes. Typically, the implant will transmit data on the uplink most of the time; the circuit reported here is optimized for this function, consuming les

Mixed signal circuit design often involves circuits that are time-varying or highly non-linear, which further results in systems that are difficult to characterize using established methodologies for linear time-invariant systems, thus designers are more than often forced to rely on intensive simulations for design. This dissertation explores design optimization for comparators, phase locked loops and ADC from three different perspectives.First, a complete analysis for regenerative comparators is presented including noise, offsets and speed for the first time. Despite the fact that the comparators are time-varying and regenerative with infinite gain, simple equivalent circuits still accurately capture their operation. Design guideline are provided for different comparator architectures.Second, a linearized analysis for phase locked loops using bang-bang phase detectors is presented. The high non-linear bang-bang phase detector is ascribed to an effective gain, whose physical meaning is interpreted in signal space. Closed form expressions for loop gain, output jitter and phase noise profile are obtained using transfer functions for the first time. Design guidelines are also provided.Last, a 2.5GS/s 10bit 65mW ADC in 28nm CMOS FD-SOI without active amplifier and intensive digital calibration is presented. This highlights the potential of circuit design based on complete understandings. The fabricated ADC with considerably less complexity achieves comparable performance with state-of-arts. Different imperfections are quantitatively studied and compared with measurement.

Neuromodulation is the alternation of nerve activity through targeted delivery of a stimulus, such as electrical stimulation, to specific sites in the body. Deep brain stimulation (DBS) is a commonly-used neuromodulation treatment for neurological ailments when traditional methods, such as surgery, medication or psychotherapy, fail. DBS is performed by sending controlled electrical pulses into the brain to evoke the desired response. However, existing DBS systems can only administer open-loop stimulation over a limited number of channels. Future neuromodulation systems require a multi-channel closed-loop platform that can provide high spatial precision, and automatically adjust stimulation parameters based on feedback from recorded neural signals. This multi-channel, closed-loop system poses new challenges for brain-sensing circuit and system design. To enable closed-loop operation, the sensing circuit needs to work with concurrent stimulation. Therefore, it needs to provide a large input range to prevent saturation under stimulation artifacts. In addition, the sensing circuit should simultaneously meet device/patient safety constraints. Current state-of-the-art neural sensing circuits, however, do not meet these requirements. This work presents an implantable VCO-based neural-sensing front-end design intended for multi-channel, closed-loop neuromodulation applications. Specifically, it converts the input voltage into the phase domain, and performs direct digitization without any voltage-domain amplification, thus preventing saturation. The phase-domain processing allows a large input range that can comprise both stimulation artifacts and the neural signals. Four techniques have been implemented to overcome design challenges: (1) in the high-pass filter, we utilize a multi-rate duty-cycled resistor as a reliable solution to attenuate electrode-offsets; (2) inside of the VCO, chopping is applied to lower circuit noise; (3) at the analog-digital interface, we employ a