Analog front-end architectures for high-speed PRML magnetic read channels

IC front-end architectures for a CMOS partial - response maximum likelihood magnetic read channel are re-examined. By organizing the front-end system components properly, several properties may be optimized; clock-recovery acquisition time can be minimized, sensitivity to ADC quantization noise may be reduced, and overall power and complexity may be minimized. Channel simulation reveals that efficient equalization may be carded out with an adaptive, continuous-time equalizer with only 4-poles, which increases drive packing densities over conventionally equalized channels. 1-[[micro]meter] CMOS circuits necessary for realization of the desired 200MHz front-end are designed, partially realized, and tested.