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The multiplier is a pervasive critical component today. However, most of them are difficult to be integrated into an integrated circuit. In this study, we proposed a novel analog multiplier for AC power application, using CMOS process to realize the analog voltage multiplication function of double-ended input and single-ended output. Under the working voltage of 3.3 V, the multiplier can operate with a wide input voltage range of 0–1.6 V (about 48.8% of the working voltage) and a wide output voltage range of 0–2.56 V (about 77.5% of the working voltage). The multiplier is implemented through the current difference between two NMOSs operating in the linear region and the saturation region, respectively. Compared with the existing technique, the proposed analog multiplier has a wider input and output range, and better linearity. It is suitable for AC power signal tracking and modulation. Finally, the United Microelectronics Corporation 0.18 μm 1P4M CMOS standard process was used for physical implementation. Moreover, there is not any BJT or special device used. It was measured that the analog multiplier circuit consumes about 0.56 mW at a working voltage of 3.3 V. [ABSTRACT FROM AUTHOR]

A novel Gm-C structure of a second-order continuous-time filter is proposed that allows for the independent control of the filter's natural frequency (ω0) and quality factor (Q). The structure consists of two capacitors and four transconductors. Two transconductors together with the capacitors form a lossless second-order circuit with tunable ω0. The other two transconductors form a variable gain amplifier (VGA) which realizes an adjustable loss and thereby adjustable Q. The proposed solution can be used to implement low-voltage and low-power tunable front-end filter banks for fully integrated CMOS cochlear implants and edge intelligence accelerators. An example filter bank powered by 0.5 V and consuming 40 nW of power per single filter is designed and simulated using a 180 nm CMOS process. Circuitries for the adaptive control of transistor bias at a reduced supply voltage are proposed. The ω0 and Q control circuitries are also proposed: a delay-locked loop (DLL)-based system for fine ω0 tuning and a binary-weighted current mirror for Q adjustment. The proposed solution allows for the independent regulation of ω0 and Q within the ranges of 0.25–8 kHz and 1–14, respectively, with a relative tolerance of up to 5% across a filter bank. [ABSTRACT FROM AUTHOR]

Analog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the gm/ID$$ {g}_m/{I}_D $$ method, it still requires iterations and test assignment of device gm/ID$$ {g}_m/{I}_D $$ values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a two‐step method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have. [ABSTRACT FROM AUTHOR]

In the realm of analog integrated circuit (IC) design, due to the intricate nonlinear relationships between circuit performance metrics and design variables, as well as the complex interdependencies and trade‐offs between various performance criteria, it is difficult to determine the appropriate geometric width and length of the circuit components to meet all performance specifications. This difficulty makes the task of designing analog IC challenging. To address the challenge of analog IC design, this paper introduces a machine learning methodology—specifically employing the genetic algorithm (GA)—to automate the selection of circuit components' geometrical parameters, aiding the work of analog circuit designers in determining the appropriate dimensions for transistors within the charge‐pump circuit. The GA, implemented in Python and integrated with a script program written in the OCEAN language, synergistically collaborates in the GA‐OCEAN framework. The result, which ensures compliance with all specifications with remarkably low error margins, ranging as low as 0.03% and as high as 1.24%, highlights the proposed GA‐OCEAN framework's remarkable capacity to determine optimal dimensions for components inside the charge‐pump circuit. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

In this paper, a robust fault detection methodology for complex analog CMOS integrated filters is presented. It is based on combining the two types of testing methodologies, Oscillation-Based Testing (OBT) and IDDQ testing, i.e., measuring of the power-supply current ( I D D ). The proposed methodology is applied to the Bi-quad Sallen–Key band-pass (BP) filter cell with relatively complex, two-stage, class-AB-output, operational amplifier (opamp) topology. The filter is custom designed targeting the 180-nm CMOS technology. Hundreds of time-domain simulations and analyses of the circuit output signal are performed in order to obtain the fault dictionary. The presented results show that the proposed hybrid OBT–IDDQ methodology is significantly more efficient in the defects coverage than any of the particular test methodologies alone. Subsequently, the specific algorithm for the defects classification is proposed. Based on the classification, certain degree of diagnosis of the individual defect, or a group of defects, can be achieved. [ABSTRACT FROM AUTHOR]

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the I – V characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes. [ABSTRACT FROM AUTHOR]

The primary contribution of this paper is the extension of the gm/ID design methodology to two-stage operational amplifiers with class-AB output stages. First, the circuit is analyzed from the perspective of the gm/ID methodology, with a focus on its performance metrics and constraints. Second, to handle optimization targets and constraints automatically, the circuit sizing task is formulated as a single-objective optimization problem, and an optimizer is employed to obtain the temporary solution automatically. Benefiting from the gm/ID methodology, the gap between analytical equations and circuit simulation is highly reduced. Third, following the temporary solution, a guided fine-tuning method is introduced to further optimize the temporary solution. To demonstrate the effectiveness of this approach, we compared the equation-based method using the square-law model, two simulation-based methods and a commercial tool, Cadence ADE GXL, employing SMIC 55 nm and SMIC 180 nm CMOS technologies. The simulation results confirm the success of the proposed approach, showing that it not only reduces the gap between analytical equations and simulations, but also achieves the best performance metrics. [ABSTRACT FROM AUTHOR]

In this paper, the clamping effect introduced by several diode-based configurations used for the implementation of the high-value resistors in quasi-floating-gate circuits is analyzed and characterized. In contrast to previous approaches where a parasitic diode is treated as a simple high-value resistor reducing the circuit complexity, in this case the analysis considers the diode behavior which leads to a clamping circuit. This clamping circuit introduces an unwanted amplitude-dependent offset voltage, which affects the performance moving the quiescent point at the quasi-floating-gate transistors. A new anti-parallel diode configuration for quasi-floating-gate applications is proposed in this work, which eliminates this unwanted offset voltage. The proposed design is validated using simulations and experimental data in a CMOS 0.35- μ m technology. [ABSTRACT FROM AUTHOR]

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (Vbg) and threshold voltage (Vth) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model. [ABSTRACT FROM AUTHOR]

With the rapid development of next-generation wireless communications, there is a growing demand for high-quality integrated circuits (ICs), particularly analog ICs, which play a pivotal role for the full roll-out sixth-generation (6G) technology. So far, the IC design has been performed through manual approaches which sometimes results in time-consuming turnaround, especially the sizing phase of analog IC design. In order to make the IC design process much faster, recently automated methods for optimizing IC design has gained a lot of attention. From this perspective, this paper aims at providing a survey of the most recent works on optimization strategies for analog IC sizing, as well as a related categorization into two main categories: analytical methods and simulation-based methods. A further sub-classification within the realm of simulation-based methods is also provided by dividing the core mathematical principles into three major sub-methods: Bayesian-based, metaheuristic-based, and reinforcement-learning-based techniques. In addition, with the main aim of providing insights on the utilization of optimization algorithms for the IC sizing process, we present a case study involving the utilization of various metaheuristic algorithms in the design of a bandgap reference circuit - an essential analog IC component. The paper is concluded by highlighting potential future research directions in the field of analog IC design optimization and automation, which include exploration of multi-agent reinforcement learning, integration of quantum computing, and further development of full-flow automated tools for analog IC design. [ABSTRACT FROM AUTHOR]

A novel accuracy-aware modeling and solving approach of adopting a back-propagation neural network (BP-NN) targeting to a classical analog five-transistor operational transconductance amplifier (OTA) is proposed in this paper. Three complex BP-NN algorithms are described amply in performance model training between multiple design factors and performance metrics, where genetic algorithm (GA), particle swarm optimization (PSO) and mind evolutionary algorithm (MEA) are introduced to further speed up the searching process for global solutions. Effectiveness comparison is performed by running simulations using SMIC 180 nm/1.8 V CMOS technology, three complex algorithms with longer time-consuming of 10 h, 30 m and 28 m demonstrate significantly superior features in solving accuracy, which show lower mean square errors (MSEs) by improvements of 82.7%, 99.7% and 99.9%, respectively. The results show that the proposed BP-NN modeling approach can be effectively aided in accelerating the global design solution of a long-cycle, nonlinear and multivariable-solved analog circuit. [ABSTRACT FROM AUTHOR]

This paper presents the use of an artificial intelligence (AI) tool based on ant colony behavior to design an operational amplifier circuit. The ant colony optimization (ACO) is implemented in a hybrid evolutionary sizing method to automate analog circuit design. This new meta-heuristic approach that combines the artificial intelligence of an ant colony and the 3D matrix method is developed to determine the optimal dimensions and the main influencing performances of fundamental analog circuits and, including operational amplifiers (op-amps). The proposed methodology uses ACO and Cadence Spectre as dimensioning techniques and implementation platform, respectively. The Three Dimensions (3D) ACO algorithm is successfully used for analog circuit sizing, and the obtained results demonstrate its effectiveness in sizing basic and more complicated analog circuits. [ABSTRACT FROM AUTHOR]

As a pivotal integral component within electronic systems, analog circuits are of paramount importance for the timely detection and precise diagnosis of their faults. However, the objective reality of limited fault samples in operational devices with analog circuitry poses challenges to the direct applicability of existing diagnostic methods. This study proposes an innovative approach for fault diagnosis in analog circuits by integrating deep convolutional generative adversarial networks (DCGANs) with the Transformer architecture, addressing the problem of insufficient fault samples affecting diagnostic performance. Firstly, the employment of the continuous wavelet transform in combination with Morlet wavelet basis functions serves as a means to derive time–frequency images, enhancing fault feature recognition while converting time-domain signals into time–frequency representations. Furthermore, the augmentation of datasets utilizing deep convolutional GANs is employed to generate synthetic time–frequency signals from existing fault data. The Transformer-based fault diagnosis model was trained using a mixture of original signals and generated signals, and the model was subsequently tested. Through experiments involving single and multiple fault scenarios in three simulated circuits, a comparative analysis of the proposed approach was conducted with a number of established benchmark methods, and its effectiveness in various scenarios was evaluated. In addition, the ability of the proposed fault diagnosis technique was investigated in the presence of limited fault data samples. The outcome reveals that the proposed diagnostic method exhibits a consistently high overall accuracy of over 96% in diverse test scenarios. Moreover, it delivers satisfactory performance even when real sample sizes are as small as 150 instances in various fault categories. [ABSTRACT FROM AUTHOR]

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC's parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage V I N _ O F F of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the V I N _ O F F of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage V D D = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations. [ABSTRACT FROM AUTHOR]

Summary: Operational amplifier (Op Amp) is a special class of analog integrated circuits. Multiple‐stage Op Amp design is of particular interest recently. However, analysis of this class of circuits has to be done manually and requires advanced skills. Automatic analysis of this class of circuits is studied in this paper, which takes a novel approach by circuit recognition and symbolic generation. Circuit recognition is deterministic, implemented by deterministic circuit partitioning and functional block extraction methods. Symbolic analysis of extracted circuit blocks can subsequently be performed with greatly reduced complexity while generated models and equations bear more useful information for circuit design. Symbolic results so generated can be applied in design space exploration, including tasks like finding the limitation in circuit topology, conducting initial sizing, and determining performance tradeoffs. This paper proposes the key algorithms for realizing the recognition of a few well‐known functional blocks frequently used in CMOS Op Amp circuits and further explores the possibility of using the recognized circuit cells in combination with the gm/ID method for circuit sizing. Preliminary tests show that this approach is a potential candidate for locating the performance boundaries of multiple‐stage Op Amps. [ABSTRACT FROM AUTHOR]

The presented paper introduces an accurate approach for detecting and classifying parametric or soft faults that affect analog integrated circuits. This technique is based on the use of machine learning algorithm to improve the accuracy and the performance of fault classification process. To achieve this, the real and imaginary frequency responses of output voltage and supply current of the circuits under test (CUT) are used to extract features for both normal and faulty cases. These features are then exploited to train machine learning classifiers, from which the selected one among its equivalents is the quadratic discriminant classifier since it allowed the highest average accuracy score. The faults to be investigated are parametric ones affecting resistors and capacitors values. The proposed approach is validated using three filters circuits that are Sallen-Key band-pass filter, four op-amp biquad high-pass filter, and a leapfrog filter circuit. Obtained results indicate a high classification average accuracy for all circuits that are undergone testing. The proposed approach has provided a highest classification accuracy level comparing to other research works.

The presented paper introduces an accurate approach for detecting and classifying parametric or soft faults that affect analog integrated circuits. This technique is based on the use of machine learning algorithm to improve the accuracy and the performance of fault classification process. To achieve this, the real and imaginary frequency responses of output voltage and supply current of the circuits under test (CUT) are used to extract features for both normal and faulty cases. These features are then exploited to train machine learning classifiers, from which the selected one among its equivalents is the quadratic discriminant classifier since it allowed the highest average accuracy score. The faults to be investigated are parametric ones affecting resistors and capacitors values. The proposed approach is validated using three filters circuits that are Sallen-Key band-pass filter, four op-amp biquad high-pass filter, and a leapfrog filter circuit. Obtained results indicate a high classification average accuracy for all circuits that are undergone testing. The proposed approach has provided a highest classification accuracy level comparing to other research works. [ABSTRACT FROM AUTHOR]

In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor's dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 Vp. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal's feasibility. [ABSTRACT FROM AUTHOR]

Recently, design methods based on g m / I d parameters have attracted attention in analog integrated circuit design and have been automated with computer assistance. However, the look-up tables (LUTs) in the g m / I d method have the problem of high hardware resource overhead. To address this issue, this paper proposes a multi-output deep neural network (DNN) structure for modeling the direct-current parameters of transistors and replacing LUTs for circuit design. The proposed DNN models' performance is verified using mainstream design technologies such as TSMC 40 nm (T40), TSMC 65 nm (T65), TSMC 180 nm (T180), and SMIC 180 nm (S180). Compared with LUTs, the proposed DNN models are able to reduce at least 99.9% storage space occupation and 95.62% prediction time overhead with a mean absolute percentage error of less than 0.2%. In addition, we propose an automated circuit migration design method using DNN models in different technologies, combined with g m / I d parameters. The method generates circuit design databases in different technologies and obtains device design results according to performance requirements. The experimental results show that using DNN models can reduce the time overhead by more than 40% compared to using LUTs. The simulation results of circuit transplantation design show that the circuit performance of T40, T65, S180, and T180 meets the requirements, which verifies the proposed DNN-based automated circuit design method. [ABSTRACT FROM AUTHOR]

Feature extraction plays an important role in constructing artificial intelligence (AI) models of industrial control systems (ICSs). Three challenges in this field are learning effective representation from high-dimensional features, data heterogeneity, and data noise due to the diversity of data dimensions, formats and noise of sensors, controllers and actuators. Hence, a novel unsupervised learning autoencoder model is proposed for ICS data in this paper. Although traditional methods only capture the linear correlations of ICS features, our deep industrial representation learning model (DIRL) based on a convolutional neural network can mine high-order features, thus solving the problem of high-dimensional and heterogeneous ICS data. In addition, an unsupervised denoising autoencoder is introduced for noisy ICS data in DIRL. Training the denoising autoencoder allows the model to better mitigate the sensor noise problem. In this way, the representative features learned by DIRL could help to evaluate the safety state of ICSs more effectively. We tested our model with absolute and relative accuracy experiments on two large-scale ICS datasets. Compared with other popular methods, DIRL showed advantages in four common indicators of AI algorithms: accuracy, precision, recall, and F1-score. This study contributes to the effective analysis of large-scale ICS data, which promotes the stable operation of ICSs. [ABSTRACT FROM AUTHOR]

Second-generation voltage conveyor structures, based on the employment of flipped voltage follower stages, are investigated and proposed in this work. The proposed core has the feature of offering extremely low or electronically adjustable input resistance and programmable outputs, enhancing the achieved design flexibility and versatility of this active cell. Two design examples are presented in this work, including a multi-phase sinusoidal oscillator topology and an electronically adjustable first-order low-pass filter, both supported by simulation and experimental results. [ABSTRACT FROM AUTHOR]

An artful complex algorithm to achieve high-efficiency high-precision multiobjective synchronous modeling and optimal solving of an analog IC is proposed. The complete approach combines response surface methodology (RSM) with an improved support vector regression (SVR) machine, which shows obvious superiority in nonlinear modeling and global solution by reduced training datasets. Targeting an analog comparator circuit as the experimental object, 33 sets of optimal design parameters are solved first in the RSM preprocessing stage, and these high-quality sample data can be subsequently input to the SVR machine for model training. In the second SVR solving stage, a differential evolution (DE) algorithm is adopted to further auto-optimize the modeling factors of the SVR machine to improve the accuracy of the nonlinear model. Finally, an SVR model of the comparator circuit can be obtained to accurately describe the response relationships of performance metrics and the corresponding design parameters that are expected by designers. With the comparator design based on TSMC 65 nm/1.2 V standard CMOS technology, we compare the SVR model-based prediction value with the Cadence-based simulation result by design test-bench and observe error lower than 3%. This work proved that the proposed complex RSM-DE-SVR algorithm is significantly practical and effective to benefit the aided optimization design of analog ICs. [ABSTRACT FROM AUTHOR]

Summary: In the past, several new active elements have been employed to realize single‐resistance‐controlled oscillators (SRCO) of which the four‐terminal‐floating‐nullors (FTFN) have attracted considerable attention in the literature. In this paper, an ingenious methodology of deriving single‐FTFN‐based canonic grounded‐capacitor (GC) SRCOs has been presented. It is shown that such oscillators can be systematically evolved from a class of earlier known op‐amp‐based SRCOs through the application of two theorems pertaining to RC‐nullor oscillators published earlier. The presented methodology not only yields all the previously known (four) single‐FTFN‐based canonic GC SRCOs but also reveals a number of (12) new circuits, which have not been known in the open literature earlier. The viability of the evolved oscillator circuits has been confirmed through SPICE simulations, and some simulation results have been given. [ABSTRACT FROM AUTHOR]

The paper work aims to extract effectively the fault feature information of analog integrated circuits and to improve the performance of a fault classification process. Thus, a fault classification method based on principal component analysis (PCA) and adaptive neuro fuzzy inference system classifier (ANFIS) preprocessed by K-means clustering (KMC) is proposed. To effectively extract and select fault features the traditional signal processing based on sampling technique conducts to different signature parameters. A stimulus pulse signal applied to the circuit under test (CUT) allowed us to get a reference output response. Respecting both specific sampling interval and step, the fault free and the faulty output responses are sampled to create amplitude sample features that will serve the fault classification process. The PCA employed for data reduction has lessened the computational complexity and obtaining the optimal features. Thus more than 75% of data volume decreased without loss of original information. The principal components extracted by this reduction data method have been input into ANFIS aided by KMC to obtain the best fault diagnosis results. The experimental results show a score of 100% diagnostic accuracies for the CUTs. Therefore, our approach has achieved best fault classification precision comparing to other research works.

Photonic integrated circuits (PICs) have been a research hotspot in recent years. Programmable PICs that have the advantages of versatility and reconfigurability that can realize multiple functions through a common structure have been especially popular. Leveraging on-chip couplers and phase shifters, general-purpose waveguide meshes connected in different topologies can be manipulated at run-time and support a variety of applications. However, current waveguide meshes suffer from relatively a low cell amount and limited bandwidth. Here, we demonstrate a reconfigurable photonic integrated computing chip based on a quadrilateral topology network, where typical analog computing functions, including temporal differentiation, integration, and Hilbert transformation, are implemented with a processing bandwidth of up to 40 GHz. By configuring an optical path and changing the splitting ratio of the optical switches in the network, the functions can be switched and the operation order can be tuned. This approach enables wideband analog computing of large-scale PICs in a cost-effective, ultra-compact architecture. [ABSTRACT FROM AUTHOR]

Analog integrated circuit sizing is notoriously difficult to automate due to its complexity and scale; thus, it continues to heavily rely on human expert knowledge. This work presents a machine learning-based design automation methodology comprising pre-defined building blocks such as current mirrors or differential pairs and pre-computed look-up tables for electrical characteristics of primitive devices. Modeling the behavior of primitive devices around the operating point with neural networks combines the speed of equation-based methods with the accuracy of simulation-based approaches and, thereby, brings quality of life improvements for analog circuit designers using the g m / I d method. Extending this procedural automation method for human design experts, we present a fully autonomous sizing approach. Related work shows that the convergence properties of conventional optimization approaches improve significantly when acting in the electrical domain instead of the geometrical domain. We, therefore, formulate the circuit sizing task as a sequential decision-making problem in the alternative electrical design space. Our automation approach is based entirely on reinforcement learning, whereby abstract agents learn efficient design space navigation through interaction and without expert guidance. These agents' learning behavior and performance are evaluated on circuits of varying complexity and different technologies, showing both the feasibility and portability of the work presented here. [ABSTRACT FROM AUTHOR]

Manual design of Complementary Metal Oxide Semiconductor (CMOS) based analog circuit design becomes more challenging and tedious task due to very complex physical models and variation in the fabrication process as technology scale down. In this continuously changing era, the demand of mixed signal System on Chip (SoC) increasing day by day which digital and analog circuits integrated on same silicon chip. For the digital circuit design, many mature computer based automated tools have been established and limited research efforts made towards automization of the analog circuit design. This gap opens the ample research space for the researcher in the field of analog circuit design. Automization of analog circuit design makes the mixed signal SoC is the best approach to cope up with this problem, cost considerations and the time to market. This motivates the analog circuit designer to explore more automated computer aided tools in the field of analog circuit design. In this review paper, performance evaluation of various evolutionary algorithms is compared. The comparison includes most used Differential Evolution (DE) algorithm, Cuckoo Search (CS) algorithm, Particle Swarm Optimization (PSO) algorithm, hybrid CSPSO algorithm. The performance evaluations of these algorithms are compared with the different standard benchmark functions and the convergence graphs of these standard benchmark functions are compared to test number of runs with respect to number of iterations. [ABSTRACT FROM AUTHOR]

The Current Mirror (CM) technique is widely used in mixed-mode and analog integrated circuits for tasks such as current amplification, biasing, and active loading. The overall effectiveness of these circuits relies heavily on their efficient designs. Current mirrors are primarily employed to accurately replicate currents in a circuit, offering high stability, simplicity, and scalability. They have become indispensable building blocks in analog and mixed-signal circuits, with their significance growing along with the demand for high-performance and low-power designs. Numerous techniques have been proposed to improve the performance metrics of current mirrors, including accuracy, input resistance, output resistance, and bandwidth. This study compares the advantages and disadvantages of these different current mirror techniques on a unified platform. It includes a comprehensive analysis of various contemporary mirror topologies, and classifies them based on their distinct characteristics. The performances of different current mirrors, including the basic CM, Wilson CM, cascode CM, and folded cascode CM circuits, were thoroughly examined in this analysis. The objective of this study is to select an appropriate current mirror for specific applications. The circuits considered in this study accurately mirror a current of 100 µA with a ±2% error using the Cadence Virtuoso software and UMC 65 nm technology. Process, Voltage, and Temperature (PVT) analysis, along with Monte Carlo simulations, were conducted under similar conditions using a supply voltage of 1.2V to ensure a fair comparison across the various current mirror approaches. [ABSTRACT FROM AUTHOR]

Abstract In this letter, a new rail‐to‐rail two‐stage regenerative comparator for low supply voltage applications is presented. A rail‐to‐rail operation is achieved by utilizing an inverse inverter pre‐amplifier. The proposed comparator is post‐layout simulated within a standard 180‐nm CMOS technology. In the worst‐case scenario, the energy efficiency and the delay of the comparator are improved by more than 80% compared to the conventional single‐stage comparator.

Paper "BTI resilient TG-based high-performance ring oscillator for PUF design" by Shubhang Srivastava et al. [[6]] propose a new energy-efficient and aging resilient inverter and ring oscillator based on an aging resilient inverter design. Authors also designed ring oscillator from the proposed inverter shows nearly 1.5% higher frequency than the conventional aging resilient ring oscillator for the same number of inverter stages. The increasing versatility, performance, compactness and power efficiency of today's electronic systems is achieved by pushing technology to its physical limits; systems are increasing in size and complexity, comprising thousands of subsystems made of billions of devices. [Extracted from the article]

The developing optimization algorithms provide promising solutions for speeding up analog integrated circuit sizing. However, the optimization of complicated circuits whose solution regions are narrow remains to be a challenge. With a limited number of sampling points due to the restriction of computational resources, it is difficult for traditional algorithms to achieve satisfactory results for such circuits. To solve this problem, this article proposes a rule-guided genetic algorithm (RG-GA) for analog circuit optimization. Different from the random mutation approach in the traditional genetic algorithm (GA), the RG-GA introduces a design rule-guided mutation (RGM) mechanism which helps to find the solution region in a more straightforward fashion. Instead of handing over circuit optimization tasks to pure mathematical algorithms, the proposed method takes advantages of valuable design knowledge to improve searching efficiency. This novel algorithm is implemented and deployed to design a two-stage rail-to-rail operational amplifier (OPA), an LC voltage controlled oscillator (LC-VCO) and a four-stage OPA. Experimental results show that compared to the traditional GA method, the RG-GA achieves about 1.5 and 3.3 times speed enhancement for the two-stage rail-to-rail OPA and the LC-VCO, respectively. For the four-stage OPA, the RG-GA method can find an acceptable point within the given number of iterations while the traditional GA could not. [ABSTRACT FROM AUTHOR]

Coverage is a key indicator for verification progress, verification closure, and verification sign-off in an integrated circuit design. The notion of coverage management, namely, the use of coverage information across the design hierarchy to identify verification loopholes, is well understood in the digital context, but requires considerable disambiguation in the analog/mixed-signal (AMS) context. This article develops the core artifacts of AMS coverage and presents a comprehensive coverage management approach based on our tool, CoveRT. Our results, gleaned from live industrial designs, demonstrate the benefits of AMS coverage management across the design hierarchy, both in terms of identifying verification gaps, as well as in finding design bugs. [ABSTRACT FROM AUTHOR]

This article presents a novel deep-reinforcement-learning-based method for topology synthesis of analog-integrated circuits, especially operational amplifiers (OpAmps). It behaves like a human designer, who learns from trials, derives design knowledge and experience, and evolves gradually to finally figure out optimal manners to construct proper circuit topologies that meet design specifications. Essential design rules are defined and applied to set up the specialized environment for reinforcement learning in order to reasonably construct circuit topologies with building blocks as the basic components. Our proposed method can not only handle large-size circuit designs but also generate creative circuit topologies. The produced circuit topologies are verified by the simulation-in-loop sizing. In order to improve the evaluation efficiency, hash table and symbolic analysis techniques are utilized to significantly reduce the number of the produced topologies to be sized during the synthesis process. Compared with the state-of-the-art approaches, our proposed method significantly improves the synthesis efficiency by consuming only several hours on average to produce a trustworthy solution. Our experimental results demonstrate its sound efficiency, strong reliability, and wide applicability. [ABSTRACT FROM AUTHOR]

This paper focuses on experimented space projects run by universities, offering an effective design process to improve learning methods in space engineering. The approach used for the design of CubeSat Electrical Power System (EPS) will go through estimations, sizing, simulations, PCB design and end with an experimental test procedure for design validation. The main design criteria presented in this paper are low costs and effective reliability. To meet the first criterion, the Commercial-Off-The-Shelf (COTS) components are used during the design, which has become an effective path to put experimental payloads in orbit for minimal cost. In the second criterion, the function of some critical EPS components was replicated, such as circuits used for power maximization and battery charge regulation, by following a suitable algorithm embedded in MCU and hot/cold redundant analog integrated circuits. However, the choice was made on the state of the art of CubeSat components already tested. This approach of working will help new space engineers to think about optimal solutions for the design of the appropriate EPS for a CubeSat university project achievable on a limited budget. Finally, the necessary experiments of the designed EPS were carried out and the results were illustrated in the context below. [ABSTRACT FROM AUTHOR]

The layout design of analog integrated circuits has been defying all automation attempts, and it is still primarily a handcrafting process carried by circuit designers on traditional layout editing frameworks. This paper presents a toolbox based on deep learning techniques and a sturdy graphical user interface to assist designers during that process. The underlying mechanism of this toolbox relies on a simple pairwise device interaction circuit description, i.e., the circuits' topological constraints, to propose valid floorplan solutions for block-level structures, including topologies and deep nanometer technology nodes not used for its training, at push-button speed. Despite its automatic functionalities, the toolbox is focused on explainable artificial intelligence, involving the designer in the synthesis flow via filtering and editing options over the candidate floorplan solutions. This constant state of human-machine feedback environment turns the designer aware of the impact of each device's position change and inherent tradeoffs while suggesting subsequent moves, ultimately increasing the designers' productivity in this time-consuming and iterative task. Finally, the toolbox is shown to instantly generate floorplans with similar or better constraint fulfilment than human designed solutions for state-of-the-art analog circuit blocks. [ABSTRACT FROM AUTHOR]

The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer's experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance. [ABSTRACT FROM AUTHOR]

This study proposes a single-ended operational trans-conductance amplifier (SEOTA)-based triple inputs and single output high-input impedance voltage-mode (VM) universal second-order filter. The proposed universal VM SEOTA-based second-order filter can be realized for the non-inverting low-pass, non-inverting high-pass, non-inverting band-reject, non-inverting all-pass and inverting band-pass filtering functions by appropriately using different triple-input voltage signals. The high-input impedances of the proposed universal VM SEOTA-based configuration enable the second-order filter to be cascaded without additional buffers. The proposed configuration does not employ external resistors and accordingly is an active SEOTAs and capacitors (SEOTA-C) universal second-order filter. The proposed circuit using two grounded capacitors which is more apposite to further develop into an integrated circuit implementation. The resonance angular frequency and quality factor are orthogonal electronically adjustable. By slightly modifying the proposed universal VM SEOTA-based second-order filter configuration, the VM SEOTA-C quadrature sinusoidal oscillator is achieved. The oscillation frequency and the oscillation condition of the quadrature sinusoidal oscillator can be independently and electronically tuned by adjusting the bias currents of two SEOTAs. PSpice simulation results confirmed theoretic anticipation. The result of the experiment of the commercially available SEOTAs, LT1228s, are also used to verify the characteristics of the proposed universal VM SEOTA-based second-order filter and VM SEOTA-based quadrature sinusoidal oscillator. [ABSTRACT FROM AUTHOR]

Bayesian optimization (BO) is popular for a analog circuit sizing problem recently. However, BO can only work well in small-scale circuit. Scaling BO to common circuit optimization (typically dimension > 10) is difficult due to the curse of dimensionality. In this article, we proposed a new BO algorithm (cBO), which can scale BO to more larger scale circuit and improve the optimization result. First, according to the fact that a specification of the analog integrated circuit is mainly determined by a few transistors, dropout strategy is adopted in our algorithm. At each iteration, only a subset of selected variables to be optimized. A variables selection strategy based on mutual information analysis and a new fill-in strategy are proposed. Second, the $g_{m}/I_{D}$ methodology-based optimization strategy is proposed. Optimization variables are not width and the length of transistors, but $g_{m}/I_{D}$ , $I_{D}$ and length. $g_{m}$ , $I_{D}$ and $g_{m}/I_{D}$ have a direct relationship to circuit performance. This is equivalent to search in circuit feature space, which could achieve better performance and handle constraints more easily. Four commonly used circuits, including low dropout regulator, two stage amplifiers, Bandgap voltage reference (VR), and VR are used for validation. Compared with other high-dimensional BO, common BO, and commercial tools (Cadence ADE_GXL), the proposed algorithm is found to produce the best optimization result and best stability. And, the ablation study shows the effectiveness and efficiency of two ingredients of the proposed algorithm. [ABSTRACT FROM AUTHOR]

To overcome the nonlinear distortion inherent in analog ICs based on Si-MOSFETs, we report here the graphene-silicon hybrid analog amplifier ICs that integrate graphene field-effect transistor (GFET) and Si-MOSFET components. By fabricating homogeneous GFETs on a silicon wafer with prefabricated Si-MOSFETs, we obtained the hybrid ICs that neatly incorporate the high linearity of GFETs. The high-linearity analog amplifier ICs can thus be realized simply using basic MOSFET circuit configurations, without requiring complicated calibration designs. This hybrid integration principle may enable immediate practical applications of graphene electronics. [ABSTRACT FROM AUTHOR]

Summary: First‐order low pass and high pass inverse filter topologies, offering simplicity and independent adjustment of the gain and the characteristic frequency, are introduced in this work. These features are offered thanks to the terminals properties of the second generation voltage conveyor. In addition, possible applications of these types of filters are exploited. The behavior of a control system, where these filters are incorporated, is evaluated in both frequency and time‐domain using the Cadence IC design suite. [ABSTRACT FROM AUTHOR]

Achieving matching constraints between various components is important in analog integrated circuit (IC) layout design, as it can reduce the impact of layout parasitics on the performance of IC. When automating analog integrated circuit layout design, identifying accurate matching constraints is an essential step before placement and routing. The matching relationship between devices strongly depends on circuit's topology and design expertise. This work focuses on differential circuits with various topologies and proposes a supervised learning framework that incorporates symmetry analysis. The heterogeneous multi-relationship graph representation is proposed to capture circuit's topology and extract matching constraints. Additionally, a symmetry analysis algorithm and filtering method based on matching levels are investigated to enhance the model's performance. The experimental results demonstrate that this work maintains a low false alarm rate and outperforms other matching constraint detection algorithms in terms of F 1 score and accuracy. • A supervised learning framework is designed for constraint extraction. • A heterogeneous multi-relationship graph is proposed to represent the topologies of circuits. • Symmetry analysis algorithm can further optimize the constrain extraction. • Constraints are extracted more accurately using the method proposed in this work. [ABSTRACT FROM AUTHOR]