Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits.

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC's parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage V I N _ O F F of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the V I N _ O F F of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage V D D = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations. [ABSTRACT FROM AUTHOR]