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With the rise of on‐device artificial intelligence (AI) technology, the demand for in‐memory comptuing has surged for data‐intensive tasks on edge devices. However, on‐device AI requires high‐density, low‐power memory‐based computing to efficiently handle large data volumes. Here, this study proposes a reliable multilevel, high gate‐coupling ratio memory device with MoS2 channel tailored for high‐density 3D NAND Flash‐based in‐memory computing. The MoS2 channel, featured by its small bandgap and high‐mobility, facilitates reliable memory window of approximately 8 V thanks to erase operation through hole injection. This not only suppresses vertical charge loss but also alleviates the burden on voltage generator circuits, indicating the suitability of MoS2 as channel material for 3D NAND Flash architecture. Additionally, a low‐k (≈2.2) tunneling layer deposited via initiated chemical vapor deposition increases the gate‐coupling ratio, thereby reducing the operating voltage. Utilizing Au nanoparticles as the charge storage layer, MoS2 memory devices show synaptic plasticity with 6‐bit, endurance (104 cycles), read disturbance (105 cycles), and retention times (105 s). Furthermore, device‐to‐system simulations for neural networks based on MoS2‐memory devices have successfully achieved a fingerprint recognition of 95.8%. These results provide the foundation to develop multi‐bit MoS2‐memory devices for AI accelerators and 3D NAND Flash memory. [ABSTRACT FROM AUTHOR]

Self-organizing Map (SOM) neural network is a prominent algorithm in unsupervised machine learning, which is widely used for data clustering, high-dimensional visualization, and feature extraction. However, the hardware implementation of SOM is limited by the von Neumann bottleneck. Herein, a SOM neural network is implemented by the combination of 3D NAND flash memory arrays and in-memory Euclidean distance (ED) calculation. The weights in the SOM network are mapped to the conductance of the 3D NAND differential pair. It is experimentally demonstrated that the differential pair in 3D NAND flash array possesses superior characteristics for neuromorphic computing during increasing and decreasing synaptic weight. Using the 3D NAND-based SOM, a competitive learning neural network is established and used for the unsupervised classification of a set of Gaussian distribution data points. The experimental results illustrate the excellent performance and efficiency of the proposed architecture, highlighting the potential of 3D NAND-based in-memory computing for artificial intelligence applications.

The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction of program disturbance is that the operational Vpass during the program's performance cannot be too high or too low. For instance, the 3D NAND program's operation string needs a lower Vpass bias to suppress unselected WL Vpass bias-induced Fowler–Nordheim tunneling (FN tunneling), but for the inhibited string, the unselected WL needs a higher Vpass bias to suppress selected WL program bias (Vpgm)-induced FN tunneling. In this paper, a systematical insight into the relationship between the channel potential and channel electron density is given. Based on this intensive investigation, we studied a novel channel preparation scheme using "Gate-induced drain leakage (GIDL) pre-charge". Our methodology does not require the introduction of any new structures in 3D NAND, or changes in the operational Vpass bias. Instead, the potential on the unselected channel is enhanced by exploiting the holes generated by the GIDL operation effectively, leading to significantly suppressed program disturbance and a larger pass disturb window. To validate the effectiveness of the "GIDL pre-charge" method, TCAD simulation and real silicon data are used. [ABSTRACT FROM AUTHOR]

Herein, the impact of cross‐temperature on 3D NAND flash memory is modeled by considering adjacent cells using machine learning. The cells comprising NAND flash memory exhibit diverse states and connectivity patterns. To effectively capture this complexity, the 3D NAND flash is converted to graph structure and the graph neural network (GNN) is leveraged, known for its exceptional performance in handling graph data. To the best of the authors' knowledge, this is the first attempt to model 3D NAND flash memory using GNN. This method has good generalization performance across various retention times and temperatures, achieving a remarkable overlap of 95.28% between ground truth and predicted distributions. Moreover, two applications of this method are introduced that contribute to the NAND flash memory improvement. One is a GNN‐assist program, which leverages well‐trained GNN to suppress the Vth$V_{\text{th}}$ degradation affected by cross‐temperature, resulting in reduced Vth$V_{\text{th}}$ shift and narrower Vth$V_{\text{th}}$ distribution width. The other is the sensitivity decomposition to identify parameters influencing the cell at cross‐temperature. It is found that cross‐temperature impact extends beyond physically connected cells to adjacent cells at close distances. Overall, this work provides valuable insights into modeling 3D NAND flash memory using GNNs and offers practical methods for enhancing NAND flash memory reliability. [ABSTRACT FROM AUTHOR]

Herein, the impact of cross‐temperature on 3D NAND flash memory is modeled by considering adjacent cells using machine learning. The cells comprising NAND flash memory exhibit diverse states and connectivity patterns. To effectively capture this complexity, the 3D NAND flash is converted to graph structure and the graph neural network (GNN) is leveraged, known for its exceptional performance in handling graph data. To the best of the authors' knowledge, this is the first attempt to model 3D NAND flash memory using GNN. This method has good generalization performance across various retention times and temperatures, achieving a remarkable overlap of 95.28% between ground truth and predicted distributions. Moreover, two applications of this method are introduced that contribute to the NAND flash memory improvement. One is a GNN‐assist program, which leverages well‐trained GNN to suppress the Vth degradation affected by cross‐temperature, resulting in reduced Vth shift and narrower Vth distribution width. The other is the sensitivity decomposition to identify parameters influencing the cell at cross‐temperature. It is found that cross‐temperature impact extends beyond physically connected cells to adjacent cells at close distances. Overall, this work provides valuable insights into modeling 3D NAND flash memory using GNNs and offers practical methods for enhancing NAND flash memory reliability.

Solid-state drives represent the preferred backbone storage solution thanks to their low latency and high throughput capabilities compared to mechanical hard disk drives. The performance of a drive is intertwined with the reliability of the memories; hence, modeling their reliability is an important task to be performed as a support for storage system designers. In the literature, storage developers devise dedicated parametric statistical approaches to model the evolution of the memory's error distribution through well-known statistical frameworks. Some of these well-founded reliability models have a deep connection with the 3D NAND flash technology. In fact, the more precise and accurate the model, the less the probability of incurring storage performance slowdowns. In this work, to avoid some limitations of the parametric methods, a non-parametric approach to test the model goodness-of-fit based on combined permutation tests is carried out. The results show that the electrical characterization of different memory blocks and pages tested provides an FBC feature that can be well-modeled using a multiple regression analysis. [ABSTRACT FROM AUTHOR]

A machine learning (ML) method was used to optimize the trap distribution of the charge trap nitride (CTN) to simultaneously improve its performance/reliability (P/R) characteristics, which are tradeoffs in 3-D NAND flash memories. Using an artificial neural network (ANN), we modeled the relationship between trap distributions and P/R characteristics. The ANN was trained using a large experimentally-calibrated technology computer-aided design (TCAD) simulation dataset. The gradient descent method was adapted to optimize the trap distribution, achieving the best P/R characteristics based on the well-trained ANN. Eventually, we found the best trap profile distributed in both space and energy. In particular, the energetic trap distribution had a larger impact on the P/R characteristics than that of the spatial trap distribution. Furthermore, in terms of the P/R characteristics, it was generally preferable to increase all inputs of the energetic trap distribution. However, the acceptor-like trap energy level ( $E_{TA}$ ) and its standard deviation ( $\sigma _{EA}$ ) caused a tradeoff between P/R characteristics; therefore, ML was used to determine their optimal points. The proposed ML method allows the optimization of trap distribution to obtain the best P/R characteristics rapidly and quantitatively. Our findings could be used as a guideline for determining the physical properties of CTN in 3-D NAND flash cells.

The incremental step pulse programming slope (ISPP) with random variation was investigated by measuring numerous three−dimensional (3D) NAND flash memory cells with a vertical nanowire channel. We stored multiple bits in a cell with the ISPP scheme and read each cell pulse by pulse. The excessive tunneling from the channel to the storage layer determines the program efficiency overshoot. Then, a broadening of the threshold voltage distribution was observed due to the abnormal program cells. To analyze the randomly varying abnormal program behavior itself, we distinguished between the read variation and over−programming in measurements. Using a 3D Monte−Carlo simulation, which is a probabilistic approach to solve randomness, we clarified the physical origins of over−programming that strongly influence the abnormal program cells in program step voltage, and randomly distributed the trap site in the nitride of a nanoscale 3D NAND string. These causes have concurrent effects, but we divided and analyzed them quantitatively. Our results reveal the origins of the variation and the overshoot in the ISPP, widening the threshold voltage distribution with traps randomly located at the nanoscale. The findings can enhance understanding of random over−programming and help mitigate the most problematic programming obstacles for multiple−bit techniques. [ABSTRACT FROM AUTHOR]

Garbage collection (GC) plays a pivotal role in the performance of 3D NAND flash memory, where Copyback has been widely used to accelerate valid page migration during GC. Unfortunately, copyback is constrained by the parity symmetry issue: data read from an odd/even page must be written to an odd/even page. After migrating two odd/even consecutive pages, a free page between the two migrated pages will be wasted. Such wasted pages noticeably lower free space on flash memory and cause extra GCs, thereby degrading solid-state-disk (SSD) performance. To address this problem, we propose a page-state-aware cache scheme called PSA-Cache, which prevents page waste to boost the performance of NAND Flash-based SSDs. To facilitate making write-back scheduling decisions, PSA-Cache regulates write-back priorities for cached pages according to the state of pages in victim blocks. With high write-back-priority pages written back to flash chips, PSA-Cache effectively fends off page waste by breaking odd/even consecutive pages in subsequent garbage collections. We quantitatively evaluate the performance of PSA-Cache in terms of the number of wasted pages, the number of GCs, and response time. We compare PSA-Cache with two state-of-the-art schemes, GCaR and TTflash, in addition to a baseline scheme LRU. The experimental results unveil that PSA-Cache outperforms the existing schemes. In particular, PSA-Cache curtails the number of wasted pages of GCaR and TTflash by 25.7% and 62.1%, respectively. PSA-Cache immensely cuts back the number of GC counts by up to 78.7% with an average of 49.6%. Furthermore, PSA-Cache slashes the average write response time by up to 85.4% with an average of 30.05%. [ABSTRACT FROM AUTHOR]

The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (Vdb) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of Vdb (Vdb_max), combined with the increased drain-to-gate potential, which enhances the GIDL current and further boosts channel potential to reach the same value at different positions of the NAND string. We proposed a method based on the correlation between the duration of Vdb_max and the number of layers to obtain the limited layers of the GIDL erase. The limited layers allowed are more than four times the number of layers used in the current simulation. Combining the novel method of dividing the channel into multi-regions with the asynchronous GIDL erase method will be useful for further stacking more layers in 3D NAND Flash. [ABSTRACT FROM AUTHOR]

The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction of program disturbance is that the operational Vpass during the program’s performance cannot be too high or too low. For instance, the 3D NAND program’s operation string needs a lower Vpass bias to suppress unselected WL Vpass bias-induced Fowler–Nordheim tunneling (FN tunneling), but for the inhibited string, the unselected WL needs a higher Vpass bias to suppress selected WL program bias (Vpgm)-induced FN tunneling. In this paper, a systematical insight into the relationship between the channel potential and channel electron density is given. Based on this intensive investigation, we studied a novel channel preparation scheme using “Gate-induced drain leakage (GIDL) pre-charge”. Our methodology does not require the introduction of any new structures in 3D NAND, or changes in the operational Vpass bias. Instead, the potential on the unselected channel is enhanced by exploiting the holes generated by the GIDL operation effectively, leading to significantly suppressed program disturbance and a larger pass disturb window. To validate the effectiveness of the “GIDL pre-charge” method, TCAD simulation and real silicon data are used.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry. [ABSTRACT FROM AUTHOR]

In this letter, the word line (WL) interference behavior in 3D NAND cell and the impact on program sequence of 3D NAND array operation are discussed. The WL interference induced by source-side neighboring cell is always smaller than that induced by drain-side neighboring cell. Due to this asymmetric characteristic, program sequence from top to bottom will have the advantage of suffering less operation window loss resulting from WL interference, over the traditional program sequence from bottom to top. This advantage can be clearly validated by the experimental results. However, at some specific WL’s of the array, the trend is reversed. The root cause of the reverse trend is then clarified to result from the unexpected undercut of sacrificial nitride film occurring during the imperfect vertical channel etching process for 3D NAND array formation. [ABSTRACT FROM AUTHOR]

Solid-state drives represent the preferred backbone storage solution thanks to their low latency and high throughput capabilities compared to mechanical hard disk drives. The performance of a drive is intertwined with the reliability of the memories; hence, modeling their reliability is an important task to be performed as a support for storage system designers. In the literature, storage developers devise dedicated parametric statistical approaches to model the evolution of the memory’s error distribution through well-known statistical frameworks. Some of these well-founded reliability models have a deep connection with the 3D NAND flash technology. In fact, the more precise and accurate the model, the less the probability of incurring storage performance slowdowns. In this work, to avoid some limitations of the parametric methods, a non-parametric approach to test the model goodness-of-fit based on combined permutation tests is carried out. The results show that the electrical characterization of different memory blocks and pages tested provides an FBC feature that can be well-modeled using a multiple regression analysis.

This publication describes the detection of buried defects in 3D NAND flash. It will first explain and motivate the use of negative mode voltage contrast electron beam inspection and then present recent use cases. Negative mode is able to generate a higher electrical field compared to conventional positive mode. A first use case shows that this high field can damage devices during inspection. Careful recipe development is necessary to find the correct dose that allows detection without damaging the device. In the second use case the electric breakthrough is necessary to detect certain defects. Although not electrically active, they are a reliability risk and therefore detection is very important for process improvement. Negative mode electron beam inspection must be used to activate and detect these defects. The higher electrical field, sufficient to break through the damaged insulator makes the defects electrically active and detectable. It also makes the defects visible to electrical test, which is not the case when positive mode inspection is used. Further investigation shows that the breakthrough in this case activates only pre-existing defects and does not affect healthy devices. [ABSTRACT FROM AUTHOR]

Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated. In order to reasonably predict those challenges, a TCAD (technology computer-aided design) simulation for 3D NAND structure in mass production has been run. By aggressively stacking-up and scaling-down bit cells in a string, the structure of channel hole was varied from a macaroni to nanowire. This causes the threshold voltage difference (ΔVth) between the top cell and bottom cell in the same string. In detail, ΔVth between the top cell and bottom cell mostly depends on the xy-scaling, but the way how ΔVth is affected is not very dependent on the stack height. [ABSTRACT FROM AUTHOR]

A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation. The energetic-trap distribution is a critical material property of the CTN that affects the Vth window between the erase and program Vth. An artificial neural network (ANN) was used to model the relationship between the energetic-trap distributions as an input parameter and the Vth window as an output parameter. A well-trained ANN was used with the gradient-descent method to determine the specific inputs that maximize the outputs. The trap densities (NTD and NTA) and their standard deviations (σTD and σTA) were found to most strongly impact the Vth window. As they increased, the Vth window increased because of the availability of a larger number of trap sites. Finally, when the ML-optimized energetic-trap distributions were simulated, the Vth window increased by 49% compared with the experimental value under the same bias condition. Therefore, the developed ML technique can be applied to optimize cell transistor processes by determining the material properties of the CTN in 3D NAND Flash. [ABSTRACT FROM AUTHOR]

The detection of temporal correlations among event-driven data streams is widely demanded in data-intensive applications such as edge computing. In this work, temporal correlation detection is enabled by the combination of 3D NAND flash and in-memory computing. Different from mathematical scheme by covariance matrix calculation, here the detection is implemented by exploiting the physical process of charge tunneling and accumulation. Thus the intrinsic charge-trapping dynamics in 3D NAND flash can be leveraged to perform in-memory computing. The computing results are stored and imprinted in the threshold voltages of the 3D NAND device array, enabling co-existence of computation and storage in the same devices. On this basis, the validation of temporal correlation detection further paves the way for 3D NAND application in high-level non-von Neumann computing. [ABSTRACT FROM AUTHOR]

• Neural networks (NNs) were proposed for predicting V T of NAND flash memories at cross-temperature. • Two different types of NNs were used for accurate prediction. • Quantitative and visual evaluations performed to verify the performance of the trained NNs. • Application of NNs can contribute to improving the reliability of NAND flash memory by capturing the V T distribution at cross-temperature. In this study, a neural network (NN) was proposed for predicting the V T characteristics of NAND flash memories under cross-temperature conditions. The training data were obtained from commercial NAND flash memory chip measurements at various temperatures. The V T distribution shift caused by cross-temperature was accurately predicted by investigating the optimum data dimensions while minimizing the data generation process. Two types of NNs were used to achieve an accurate V T distribution prediction, and each network was optimized using specific parameters based on the data characteristics at various program verify levels. Finally, quantitative and visual evaluations were conducted to verify the performance of the trained NNs. When the program-measured temperature varied from low to high, the NNs achieved mean errors of 1.87%, 1.41% at low and 0.34%, 0.77% at high for the average and width of the V T distribution, respectively. Similarly, when the temperature varied from high to low, the corresponding mean errors were 2.01%, 0.74% at high and 0.23%, 1.59% at low. These findings demonstrate that NNs can minimize the procedures for detecting the V T distribution shift caused by cross-temperature, thereby offering a promising approach to enhance reliability in the presence of such effects. [ABSTRACT FROM AUTHOR]

GLS (Gate line split) filling is a very important process in 3D NAND flash memory (3D NAND) fabrication. Filling materials in the GLS should have threefold properties, such as warpage tunability, leakage-free and low resistance. In this paper, the effects of different GLS filling materials (SiO 2 , W, amorphous silicon: A-Si) on F-attack, warpage and resistance were studied. GLS filled with A-Si shows best performance on warpage and F-attack. For 3D NAND, the number of stacked layers is predicted as a function of the wafer warpage, and the wafer warpage difference between GLS filled with A-Si and W was compared. With the same number of stacking layers, the wafer warpage post GLS filled with A-Si is smaller than that filled with W. Meanwhile, A-Si is produced by the decomposition of SiH 4 by low pressure chemical vapor deposition (LPCVD) process, F-related by-product in the GLS filling material and consequent ACS (array common source) to WL (Word line) leakage by F-attack are avoided. A-Si is the best choice for GLS filling. This work provides an efficient method to solve the warpage and leakage problem in 3D NAND flash memory fabrication. [ABSTRACT FROM AUTHOR]

• The causes of improved program efficiency in 3D NAND Flash memory were investigated. • As deposition temperature of tungsten decreases, the mechanical stress in polysilicon channel and tunneling oxide increases. • The barrier height and the effective mass decrease, and electric field increases when mechanical stress increases. • As Fowler-Nordheim tunneling increases based on decreasing deposition temperature of W, the program efficiency increases. • As program voltage decreases, the program efficiency increases, which means improved ISPP. This study investigated the relationship between mechanical stress and program efficiency in three-dimensional (3D) NAND flash memory devices. A stacked memory array transistor (SMArT) 3D NAND flash structure was modeled using a technology computer-aided design (TCAD) simulation. The mechanical stress distribution in the device depended on the deposition temperature (T D) of the constituent material. In particular, the T D of tungsten (T D,W) dominated the mechanical stress. The tensile stress on the polycrystalline silicon (poly-Si) channel increased as the T D,W decreased, and the compressive stress on the tunneling oxide (T ox) decreased. Consequently, the barrier height between T ox and poly-Si, and the effective electron mass decreased as the electric field in the T ox increased. These changes significantly increased the Fowler-Nordheim (FN) tunneling process and program efficiency, indicating the crucial performance of 3D NAND flash. Moreover, the mechanical stress caused by the differences in T D,W improved the program efficiency at a lower program voltage (V PGM). Therefore, a change in the mechanical stress based on decreasing T D,W improved the program efficiency through a higher FN tunneling process. [ABSTRACT FROM AUTHOR]

The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (Vdb) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of Vdb (Vdb_max), combined with the increased drain-to-gate potential, which enhances the GIDL current and further boosts channel potential to reach the same value at different positions of the NAND string. We proposed a method based on the correlation between the duration of Vdb_max and the number of layers to obtain the limited layers of the GIDL erase. The limited layers allowed are more than four times the number of layers used in the current simulation. Combining the novel method of dividing the channel into multi-regions with the asynchronous GIDL erase method will be useful for further stacking more layers in 3D NAND Flash.

Experimental demonstration of unsupervised learning is realized with charge-trapping 3D NAND flash device array. The charge-trapping characteristic of the memory cell is leveraged so that the devices perform not only as non-volatile memory but also synaptic cells in hardware neural network. Experiments reveal that the 3D NAND flash devices hold good potential for neuromorphic computing because of its delicately modulated synaptic weight. Furthermore, differential pair scheme is employed to enable larger dynamic range and finer weight tunability as compared with previous works. And based on the 3D NAND array, unsupervised learning is implemented by experiments with a winner-takes-all neural network, which can achieve perfect clustering of stylized letters within tens of training epochs. Beyond that, the 3D NAND devices also exhibit highly robust reliability against various disturb during synaptic weight update. The excellent synaptic device performance and reliability altogether make solid foundation for the winner-takes-all update rule in unsupervised learning neural network. [ABSTRACT FROM AUTHOR]

Reading data at a temperature which different from writing can cause a large number of failed bits in 3D NAND Flash memory. In this work, the threshold voltage (Vth) temperature effect of 3D NAND flash memory cell was investigated and a method was proposed to optimize its temperature coefficient (Tco). The results suggested that the Tco of low temperature programmed high temperature read is larger than high temperature programmed low temperature read and this difference is about 2-3mv/°C, which makes against the temperature compensation of reading voltage and lead to irreparable data errors even there is error correction codes. Furthermore, the critical factor of this difference was demonstrated that is the charge loss during low temperature programmed high temperature read and the Vth shift caused by charge loss is up to 30 percent. Based on this, we proposed to optimize the Tco consistency by shortening the interval time of erase to program in endurance cycling stage and confirmed that this method is effective by experiment. As the time interval becomes smaller, the difference of the Tco decreases as well, which have great reference signification for improving the reliability of 3D NAND flash memory.

Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND (Shibata et al., 2007, Lee et al., 2018, Shibata et al., 2019, and Khakifirooz et al., 2021), and the IVS improvement by re-program scheme was reported. In this work, it is found that re-program can suppress ~81% of IVS in 3D NAND, which is much more significant than that of 2D NAND ~50% (Chen et al., 2010). The mechanisms of IVS improvement by re-program scheme in 3D NAND are investigated. Both vertical de-trapping in the BE-tunneling oxide and charge lateral migration (LM) in the charge-trap layer are suppressed in re-program. Re-program is effective in vertical de-trapping suppression both in checker-board pattern (C/P) and solid-board pattern (S/P) cases, and is effective in LM suppression only in C/P case. Furthermore, the LM improvement by re-program scheme is more pronounced with gate length (Lg) and inter-gate space (Ls) scaling down, showing potential in the reliability improvement of advanced 3D NAND technologies.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry.

3D charge-trap (CT) NAND flash-based SSD has been used widely for its large capacity, low cost per bit, and high endurance. One-shot program (OSP) scheme, as a variation of incremental step pulse programming (ISPP) scheme, has been employed to program data for CT flash, whose program unit is the Word-Line (WL) instead of the page. The existing program optimization schemes either make trade-offs among program latency and reliability by adjusting the program step voltage ΔVpp on demand; or remap the most error-prone cell states to others by re-encoding programmed data. However, the data pattern, which represents the ratio of 1s in data values, has not been thoroughly studied. In this paper, we observe that most small files do not contain uniform 1s and 0s among these common file types (i.e., image, audio, text, executable file), leading to programming WL cells in different states unevenly. Some cell states dominate over the WL, while others are not. Based on this observation, we propose a flexible reliability enhancement scheme based on the OSP scheme. This scheme programs the cells into different states with varied ΔVpp , i.e., these cells in one state, whose number is the largest in one WL, are programmed with a fine-grained ΔVpp (namely slow write). In contrast, the minority are programmed with a coarse-grained ΔVpp (namely fast write). So the reliability is improved due to averaging the major enhanced cells with the minor degraded cells without program latency overhead. A series of experiments have been conducted, and the results indicate that the proposed scheme achieves 34% read performance improvement and 16% lifetime elongation on average. [ABSTRACT FROM AUTHOR]

Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated. In order to reasonably predict those challenges, a TCAD (technology computer-aided design) simulation for 3D NAND structure in mass production has been run. By aggressively stacking-up and scaling-down bit cells in a string, the structure of channel hole was varied from a macaroni to nanowire. This causes the threshold voltage difference (ΔVth) between the top cell and bottom cell in the same string. In detail, ΔVth between the top cell and bottom cell mostly depends on the xy-scaling, but the way how ΔVth is affected is not very dependent on the stack height.

A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation. The energetic-trap distribution is a critical material property of the CTN that affects the Vth window between the erase and program Vth. An artificial neural network (ANN) was used to model the relationship between the energetic-trap distributions as an input parameter and the Vth window as an output parameter. A well-trained ANN was used with the gradient-descent method to determine the specific inputs that maximize the outputs. The trap densities (NTD and NTA) and their standard deviations (σTD and σTA) were found to most strongly impact the Vth window. As they increased, the Vth window increased because of the availability of a larger number of trap sites. Finally, when the ML-optimized energetic-trap distributions were simulated, the Vth window increased by 49% compared with the experimental value under the same bias condition. Therefore, the developed ML technique can be applied to optimize cell transistor processes by determining the material properties of the CTN in 3D NAND Flash.

In this work, a heterogeneous integration strategy of 3D NAND based compute-in-memory (CIM) architecture is proposed for large-scale deep neural networks (DNNs). While most of the reported CIM architectures today have focused on the image classification models with MB-level parameters, we aim at huge language translation models with GB-scale parameters. Our 3D NAND CIM architecture design exploits two fabrication techniques, wafer bonding scheme and CMOS under array (CUA), to integrate CMOS circuits, 3D NAND cells, and high voltage (HV) transistors at different tiers without thermal budget issue during the fabrication process. The bonding pads between two wafers are designed to transfer the input and output vectors while ensuring $\sim 1~\mu \text{m}$ pitch that is feasible by hybrid bonding. The chip size of the 512 Gb 128-layer 3D NAND CIM architecture is estimated to be 166 mm2 with 7 nm FinFET logic transistors. Using the physical and electrical parameters of standard 3D NAND cells, the 1.15-19.01 tera operations per second per watt (TOPS/W) of energy efficiency is achieved. [ABSTRACT FROM AUTHOR]

This brief presents a programmable voltage generator with the scheme of separated dynamic clock voltage scaling for program operation in 3D NAND flash memories, where the ripple of program voltage can be minimized to reduce the variation of threshold voltage of the programmed cells. The proposed scheme drastically reduces the output ripple and improves the loop stability at the same time. What’s more, the high voltage regulator used in the conventional wordline voltage generator is not necessary anymore. The proposed generator has been implemented in a 0.18 $\mu \text{m}$ triple-well CMOS process, and the effective chip area is 0.55 mm2. Under the equivalent load conditions of 3D NAND flash, the measurement results show that the maximum ripple voltage is 2.06 mV, and the ripple is independent from clock frequency and output voltage. Moreover, the peak efficiency is about 36% at 23 V output voltage. [ABSTRACT FROM AUTHOR]

Data randomization has been a widely adopted Flash Signal Processing technique for reducing or suppressing errors since the inception of mass storage platforms based on planar NAND Flash technology. However, the paradigm change represented by the 3D memory integration concept has complicated the randomization task due to the increased dimensions of the memory array, especially along the bitlines. In this work, we propose an easy to implement, cost effective, and fully scalable with memory dimensions, randomization scheme that guarantees optimal randomization along the wordline and the bitline dimensions. At the same time, we guarantee an upper bound on the maximum length of consecutive ones and zeros along the bitline to improve the memory reliability. Our method has been validated on commercial off-the-shelf TLC 3D NAND Flash memory with respect to the Raw Bit Error Rate metric extracted in different memory working conditions.

The impact of temperature on array Vth distribution was investigated in 3D NAND flash. Cell Vth distributions were obtained under different program and read temperature splits. After the page is programmed under high temperature, it is found that the high tail of Vth distribution exhibits a larger shift than the low tail, during read at different temperatures (85 °C and −25 °C). On the contrary, the low tail of Vth distribution shows a larger shift than the high tail during cross temperature read, after the page programmed under low temperature. The temperature coefficient (Tco) of cell Vth shows cell to cell variations, which can be categorized into two types. For type ①, the Tco is correlated with the selected cell Vth due to polysilicon channel. For type ②, the Tco is independent of the selected cell Vth. The corresponding impacts on Vth distribution are studied via array Monte Carlo simulation. Based on the simulation results, the above temperature dependent observations can be well modeled by the combination of both Tco variation type ① and ②. Furthermore, two optimization approaches are proposed to alleviate the Vth distribution broadening and are validated by experiments. [ABSTRACT FROM AUTHOR]

Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory. Among these new techniques, 3D charge trap flash is considered to be one of the most promising candidates for the next-generation NAND flash devices. However, the long erase latency of 3D charge trap flash becomes a critical issue. This issue is exacerbated because the distinct transient voltage shift phenomenon is worsened when the number of program/erase cycle increases. In contrast to existing works that aim to tackle the erase latency issue by reducing the number of block erases, we tackle this issue by utilizing the “multi-block erase” feature. In this work, an erase efficiency boosting strategy is proposed to boost the garbage collection efficiency of 3D charge trap flash via enabling multi-block erase inside flash chips. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the erase efficiency and access performance of 3D charge trap flash. The results show that the erase latency of 3D charge trap flash memory is improved by 75.76 percent on average even when the P/E cycle reaches $10^{4}$ . [ABSTRACT FROM AUTHOR]

In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a “punch-and-plug” process—with gate-all-around (GAA) cell devices—against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production. [ABSTRACT FROM AUTHOR]

Nowadays, NAND Flash technology is everywhere, since it is the core of the code and data storage in mobile and embedded applications; moreover, its market share is exploding with Solid-State-Drives (SSDs), which are replacing Hard Disk Drives (HDDs) in consumer and enterprise scenarios. To keep the evolutionary pace of the technology, NAND Flash must scale aggressively in terms of bit cost. When approaching ultra-scaled technologies, planar NAND is hitting a wall: both academia researchers and industry worked to cope with this issue for several decades. Then, the 3D integration approach turned out to be the definitive alternative by eventually reaching mass production. This review paper exposes several 3D NAND Flash memory technologies, along with their related integration challenges, by showing their different layouts, scaling trends and performance/reliability features. [ABSTRACT FROM AUTHOR]

We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes. [ABSTRACT FROM AUTHOR]

In this letter, the image characteristics of CMOS image sensor (CIS) pixels using a vertical thin poly-Si channel (VTPC) transfer gate (TG) are established for the first time. The study of three-dimensional (3D) structures in the image sensor field has been started by 3D Flash memories. By adopting the poly-Si channel fabrication concept of 3D NAND flash memories—appropriately modified to fit the requirements of a TG in CIS pixel applications—the VTPC structure effectively suppresses the grain boundary effect. The VTPC-TG performance improves as the poly-Si channel becomes thinner. The possibility of implementing 3D pixel-based CIS is confirmed by applying the fabricated VTPC-TG to a mass-produced 1.12- \mu \textm BSI product, and using it to capture 5-Mpixel images. [ABSTRACT FROM PUBLISHER]

In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a “punch-and-plug” process—with gate-all-around (GAA) cell devices—against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.