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This paper presents a low-distortion and low-power multi-stage noise-shaping (MASH) architecture Sigma-Delta (Σ Δ) modulator with double-sampling. The modulator uses a cascade of integrator feed-forward (CIFF) structure as a cascaded modulator in a MASH architecture. Since the CIFF structure provides a feedforward path from the input signal to the quantizer, the input signal is directly transmitted to the output without loop processing, relaxing the linearity requirement of the modulator, reducing performance requirements for the OTA and harmonic distortion. Double-sampling technique is adopted in the first integrator to double the sampling rate, improving the accuracy of the modulator without the increase of power consumption. In order to eliminate the influence of capacitor mismatch in the sampling network, a fully floating differential switched capacitor (SC) feedback digital-to-analog (DAC) is used in the integrator. The simulation results show that the Σ Δ modulator achieves 113 dB signal-to-noise and distortion ratio (SNDR) and the power consumption is 3.15 mW from a 5 V power supply. [ABSTRACT FROM AUTHOR]

This paper proposes a wide dynamic range (DR) and high-resolution discrete-time (DT) 2-order 4-bit sigma-delta modulator with a novel dynamic-modulated scaling-down (DM-SD) technology for non-invasive electroencephalogram (EEG) acquisition. The DM-SD technology can expand the input dynamic range and suppress large input offsets at the same time. The modulator was designed with 180nm CMOS technology with an area of 0.49 mm 2 . We achieve a 118.1 dB SNDR when the input signal is 437.5 Hz and the signal bandwidth is 1500 Hz. Due to the proposed DM-SD technology, the DR is expanded to 126 dB. The power consumption of the whole modulator is 1.6 mW and a 177.8 dB Schreier figure-of-merit (FoMs) is realized. [ABSTRACT FROM AUTHOR]

With the advancement of brain science in recent years, the non-invasive brain-computer interfaces (BCIs) based on electroencephalogram (EEG) acquisition have been widely adopted in various brain-inspired applications. The acquisition of multi-channel microvolts EEG signals corrupted by the motion artifacts (MAs) of up to several volts poses enormous challenges to the design of analog front-end (AFE), especially the analog-to-digital converter (ADC), which is necessary to achieve low noise, wide dynamic range (DR), high accuracy as well as low power. In this paper, a wide DR ΣΔ modulator with chopper-modulated input-scaling-down (CM-ISD) technique has been proposed to deal with large input offset while extending dynamic range. Fabricated in 180 nm CMOS technology, the prototype occupies a core area of 0.32 mm2. With a 40 Hz input signal and 125 Hz Nyquist bandwidth, the measured signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SNDR) are 117 and 110 dB, respectively. Thanks to the proposed CM-ISD technique, the modulator is capable of withstanding a full-scale (4.5 Vpp) input whereas the measured DR has been extended from 99 to 124 dB. The power consumption is 2.75 mW under 5 V supply voltage, corresponding to 170.6 dB Schreier figure-of-merit (FoMS). The multi-channel EEG acquisition has been demonstrated based on the proposed modulator, showing its potential in advanced non-invasive BCI systems. [ABSTRACT FROM AUTHOR]

This paper proposes a wide dynamic range (DR) and high-resolution discrete-time (DT) 2-order 4-bit sigma-delta modulator with a novel dynamic-modulated scaling-down (DM-SD) technology for non-invasive electroencephalogram (EEG) acquisition. The DM-SD technology can expand the input dynamic range and suppress large input offsets at the same time. The modulator was designed with 180nm CMOS technology with an area of 0.49 mm2. We achieve a 118.1 dB SNDR when the input signal is 437.5 Hz and the signal bandwidth is 1500 Hz. Due to the proposed DM-SD technology, the DR is expanded to 126 dB. The power consumption of the whole modulator is 1.6 mW and a 177.8 dB Schreier figure-of-merit (FoMs) is realized.

This paper presents an application of the Σ Δ modulation technique to the on-chip dynamic test for analog-to-digital converters (ADCs). The required stimulus such as a single- or two-tone signal is encoded into one-bit Σ Δ sequence, which is applied to an ADC under test through a driving buffer and a simple low-pass reconstruction filter. By a systematic approach, we select the order and type of a Σ Δ modulator and develop a frequency plan suitable for the spectral measurement. In this way, we achieve a high dynamic range suitable for spectral harmonic and intermodulation distortion tests for ADCs. For high frequency measurements (up to the Nyquist frequency), we propose a novel low-pass/band-pass modulation scheme that allows to avoid harmful effects of the low-frequency quantization noise. Also we address the distortion components which originate from the buffer imperfections for a nonreturn-to-zero waveform representing the encoded stimulus. We show that the low-frequency distortion components can be cancelled by using a simple iterative predistortion technique supported by measurements with a DC-calibrated ADC. By correlation between low- and high-frequency components also the high frequency distortions can be largely reduced. The presented techniques are illustrated by simulation results of an ADC under test. [ABSTRACT FROM AUTHOR]

This brief presents a two-path discrete-time third-order sigma-delta ($\Sigma \Delta$) modulator with an extra zero in the noise transfer function (NTF) located at $z = -1$ , reducing the NTF coefficients of intermediate terms for optimal design. Applying polyphase decomposition of the NTF, the proposed $\Sigma \Delta$ modulator is implemented by a two-path architecture with cross-coupling branches. The 65-nm CMOS experimental chip running at a sampling rate of 340 MHz achieves a DR of 68.8 dB and a SNDR of 65.4 dB for a 10-MHz signal bandwidth, occupying an active area of 0.2257 mm2 and consuming 19.47 mW from a 1.2-V supply. [ABSTRACT FROM AUTHOR]

One of the design challenges for the resonant dew point measurement was optimizing the rapidity and accuracy of frequency extraction to meet the requirements. We have developed a 1-bit second-order sigma-delta (ΣΔ) analog-to-digital (ADC) to be applied in it, which was anticipated to have a highest resolution and design flexibility than traditional ADC. Based on the Butterworth filter, the design of ΣΔ modulator was modeled firstly to evaluate the performance of filters scheme before the hardware implementation. Furthermore, the design and implement of the digital decimation filters was presented to extend the design flexibility and application. To improve the accuracy and instantaneous of frequency estimation, we developed a new frequency estimation algorithm, which combined the Fast Fourier transform (FFT) and the chirp-Z transform. We built a complete hardware implementation system. We tested the performance of the designed ΣΔ ADC and found that has 11-bit resolution and the high flexibility. The experiment results showed the root mean square (RMS) error of frequency estimation was 0.0917 Hz with minimum error 0.01 Hz, and the SNR can achieve 123.04 dB. Results showed the proposed frequency estimation error decreases approximately 35 times under the premise of the same computation with FFT. Moreover, every completion of the frequency estimation only takes less than 1 s. Finally, the experiment of dew point measurement was carried out. The results indicated that the proposed measurement system was feasible for the frequency extraction of the resonant dew point sensor. [ABSTRACT FROM AUTHOR]

Digital integrated circuits (ICs) can be integrated in low-cost digital CMOS technologies with less number of masks than a mixed-signal CMOS technology. This property, however, limits the access to reliable analog components such as linear capacitors and linear inductors. Regardless of the CMOS process, sigma-delta (ΣΔ) modulation of analog signals can be fulfilled by using ordinary MOS devices as capacitors. Called as MOS capacitors (MOSCAPs), these elements illustrate nonlinear C-V characteristic, although the thin gate oxide layer results a high capacitance per unit area. In this article, we investigate the effect of MOS capacitance nonlinearity on the overall performance of discrete-time sigma-delta modulators. To this end, a behavioral-level model of a MOSFET-only switched-capacitor (SC) integrator is proposed, and enables characterizing the transfer behavior of MOSFET-only modulators. The proposed model is used to analyze the linearity and to select a suitable architecture for the modulator. It helps to decide proper structure of each MOSCAP depending on its significance on the output linearity. In virtue of the new model, behavioral-level simulation of a 1-V 12-bit 20MS/s MOSFET-only 2 + 2 sturdy MASH (SMASH) modulator matches well to circuit-level simulations in 90-nm digital CMOS technology. For a −1.4 dB, 19.7 kHz input and an oversampling ratio of 16, the modulator achieves over 72 dB signal-to-noise plus distortion ratio (SNDR), only 3 dB lower than a conventional design based on linear metal-insulator-metal (MIM) capacitors. [ABSTRACT FROM AUTHOR]

This paper presents a third order continuous time current mode ΣΔ modulator for WLAN 802.11b standard applications. The proposed circuit utilized feedback architecture with scaled and optimized DAC coefficients. At circuit level, we propose a modified cascade current mirror integrator with reduced input impedance which results in more bandwidth and linearity and hence improves the dynamic range. Also, a very fast and precise novel dynamic latch based current comparator is introduced with low power consumption. This ultra fast comparator facilitates increasing the sampling rate toward GHz frequencies. The modulator exhibits dynamic range of more than 60 dB for 20 MHz signal bandwidth and OSR of 10 while consuming only 914 μW from 1.8 V power supply. The FoM of the modulator is calculated from two different methods, and excellent performance is achieved for proposed modulator.

This paper presents a low-power, high-performance continuous-time \Sigma \Delta modulator for MEMS microphones front-end. The \Sigma \Delta modulator 3rd-order loop filter has been implemented with a low-noise, power-optimized active-RC architecture that uses only two operational amplifiers. This solution, along with the use of a 15-level quantizer and of a feedback DAC with three-level current-steering elements, which minimizes the noise contribution for small input signals, allows achieving a DR larger than 100 dB, while consuming less than 0.5 mW, as required in always-running audio modules for portable devices. The proposed \Sigma \Delta modulator, realized in CMOS technology with an area of 0.21\;\text{mm}^{2}, achieves 106 dB A-weighted DR and 91.3 dB peak SNDR, consuming 390\;\upmu \text{W}$ from a 1.6 V power supply. [ABSTRACT FROM PUBLISHER]

The performance of open‐loop ADCs implemented with VCOs is limited by VCO non‐linearity and first‐order noise shaping. The resolution limitation imposed by first‐order noise shaping can be compensated by a ring oscillator VCO with many output phases. Linearity can also be improved by using a feedback loop around the VCO closed with a DAC. However, a long ring oscillator may require a DAC with a prohibitive number of bits if feedback is used to compensate distortion. This Letter proposes an ADC architecture based on the Leslie‐Singh Sigma‐Delta (ΣΔ) modulator that allows to implement a distortion correction loop around a VCO with a simplified DAC of few levels, yet keeping a large number of output quantisation levels to maintain resolution. The Letter discusses the system‐level architecture and shows an implementation circuit example to verify the effective correction of distortion. [ABSTRACT FROM AUTHOR]

This paper proposes a wide dynamic range (DR) and high-resolution discrete-time (DT) 2-order 4-bit sigma-delta modulator with a novel dynamic-modulated scaling-down (DM-SD) technology for non-invasive electroencephalogram (EEG) acquisition. The DM-SD technology can expand the input dynamic range and suppress large input offsets at the same time. The modulator was designed with 180nm CMOS technology with an area of 0.49 mm2. We achieve a 118.1 dB SNDR when the input signal is 437.5 Hz and the signal bandwidth is 1500 Hz. Due to the proposed DM-SD technology, the DR is expanded to 126 dB. The power consumption of the whole modulator is 1.6 mW and a 177.8 dB Schreier figure-of-merit (FoMs) is realized.

Abstract: This paper presents a third order continuous time current mode ΣΔ modulator for WLAN 802.11b standard applications. The proposed circuit utilized feedback architecture with scaled and optimized DAC coefficients. At circuit level, we propose a modified cascade current mirror integrator with reduced input impedance which results in more bandwidth and linearity and hence improves the dynamic range. Also, a very fast and precise novel dynamic latch based current comparator is introduced with low power consumption. This ultra fast comparator facilitates increasing the sampling rate toward GHz frequencies. The modulator exhibits dynamic range of more than 60dB for 20MHz signal bandwidth and OSR of 10 while consuming only 914μW from 1.8V power supply. The FoM of the modulator is calculated from two different methods, and excellent performance is achieved for proposed modulator. [Copyright &y& Elsevier]

In this paper a new successive approximation (SA) quantizer based on the elimination of the digital to analog converter (DAC) from the quantizer structure is presented. Instead; the feedback DAC block of the ΣΔ modulator is shared by SA quantizer. Using an efficient decoding algorithm in the proposed structure in conjunction with the above SA quantizer DAC elimination method, results in a reduction of the level number of the feedback DAC, and hence, a significant drop in power and area consumption is achieved. In order to study the performance of the proposed structure, a third order discrete-time ΣΔ modulator is designed and simulated in 0.18 μm CMOS technology with the following performance characteristics; a signal to noise ratio of 79.2 dB, dynamic range of 84.8 dB, power consumption of 3.75 mW and a figure of merit of 0.66 pJ/conv from a 1.8 V supply with an input signal of 200 kHz bandwidth. [ABSTRACT FROM AUTHOR]

An improved recycling folded cascode amplifier for wide-bandwidth ΣΔ modulator is presented in this article. The proposed amplifier introduces internal positive-feedback pairs to achieve a significant boost in transconductance and DC gain without increasing power or area budget. The proposed recycling folded cascode amplifier was implemented in SMIC standard 65 nm CMOS process. Compared to other recycling folded cascode structures, simulation results show that the proposed amplifier achieves the enhancement of gain-bandwidth and DC gain with the best figure-of-merits. [ABSTRACT FROM AUTHOR]

This paper provides an audio 2-1 cascaded ΣΔ modulator using a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a subthreshold amplifier. By introducing a gain-boost module, the inverter DC-gain is increased from 48 dB to 67 dB. The gain-boost class-C inverter consumes 57 μW at 1.2-V supply, where the gain-boost module consumes only 3 μW. In addition, an on-chip body bias technique is introduced to compensate the process and supply voltage variations of the class-C inverter. The proposed inverter-based ΣΔ modulator chip is implemented in 0.13-μm CMOS process, and achieves 86-dB peak-signal to noise and distortion ratio (SNDR) and 90-dB dynamic range (DR) over 22.05-KHz bandwidth at 1.2-V supply consuming 360 μW, which demonstrates that the gain-boost class-C inverter is particularly suitable for micro-power high-resolution applications. [ABSTRACT FROM AUTHOR]

A gate-leakage compensation scheme is proposed to solve the gate-leakage current issue caused by large-size current-source transistors in multi-bit switched-current (SI) DACs of the continuous-time ΣΔ modulator in deep sub-micron process without extra power consumption. To cover wide current range due to variable coefficients in different modes, the programmable SI-DAC architecture with 2-bit digital controlled unit cells is proposed. Implemented in 65 nm CMOS, the simulated results verify that the proposed scheme solves the gate-leakage issue and the modulator achieves tremendously high performance of 84.5 dB SQNDR and 94.6 dB SFDR with almost 14 and 19 dB improvement in SQNDR and SFDR, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a low-power low-voltage chopper stabilized discrete-time second-order feed-forward ΣΔ modulator with an asynchronous 4-bit successive-approximation-register (SAR) quantizer. The feed-forward topology will reduce the internal signal swing, relaxing the linearity and slew rate requirements for an operational amplifier (op-amp). The analog weighted sum-mation of feed-forward paths is merged with the sampling capacitor array of a SAR quantizer to minimize the distortion and associated hardware overhead. To achieve low power consumption, a partially switched op-amp bias in weak inversion is used for the first integrator. The energy efficiency is further improved by the asynchronous SAR 4-bit quantizer. Moreover, the asyn-chronous scheme will reduce loop delay caused by the summation block, the quantizer and the data weighted averaging (DWA) circuit, improving circuit stability and lowering power con-sumption. A 0.13-µm CMOS experimental prototype achieves 84 dB dynamic range, 84 dB peak SNR and 82 dB peak SNDR over an input signal bandwidth of 10-kHz. The total power consumption of the modulator is 48 µW from a 0.8 V supply at an 800-kHz sampling rate. [ABSTRACT FROM AUTHOR]

This paper presents the design of Delta-Sigma ΣΔ based fractional N PLL frequency synthesizer for GSM mobile systems. The loop filter is one of main element in fractional-N ΣΔ synthesizer because it shapes the noise spectrum of quantization error and reduce the spurious level in the pass band of PLL. The effect of loop filter order is studied and it is shown that by increasing the order of the loop filter, the phase noise performance will be improved, although this requires careful design consideration, as the PLL is prone instability. It's shown that the 3rd order loop filter and 3rd order ΣΔ modulator gives the best performance with reducing phase noise (13dBc/Hz ) and spurious noise (44dBc) of the output signal. [ABSTRACT FROM AUTHOR]

In this paper an integrated interface circuit for condenser MEMS microphones is presented. It consists of an input buffer followed by a multi-bit (12-levels), analog, second-order ΣΔ modulator and a fully-digital, single-bit, fourth-order ΣΔ modulator, thus providing a single-bit output signal with fourth order noise shaping, compatible with standard audio chipsets. The circuit, supplied with 3.3 V, exhibits a current consumption of 215 μA for the analog part and 95 μA for the digital part. The measured signal-to-noise and distortion ratio ( SNDR) is 71 dB, with an input signal amplitude as large as −1.8 dB with respect to full-scale, obtained thanks to the use of a feed-forward architecture in the analog ΣΔ modulator, which relaxes the voltage swing requirements of the operational amplifiers. The test chip, fabricated in a 0.35-μm CMOS process, occupies an area of 3 mm, including pads. [ABSTRACT FROM AUTHOR]

A power-efficient clock/data distribution technique for the input registers of the polyphase comb decimation filter is presented. A general form of the proposed technique is developed with respect to the decimation factor. Both proposed and conventional comb filters are implemented using Xilinx Spartan3 low-power field-programmable gate array family. The implementation results show that applying the proposed technique reduces the dynamic power consumption of the second- and third-order polyphase comb filters up to 62.87% and 57.6%, respectively, depending on the decimation factor and the number of quantizer bits. For a particular power consumption, a higher input sampling rate can be utilized by applying the proposed technique. Consequently, the signal-to-noise ratio of a second-order ΣΔ modulator is increased using second- and third-order modified filters by 21.6 and 20.5 dB, respectively, depending on the decimation factor and the number of quantizer bits. [ABSTRACT FROM AUTHOR]

Modern wireless communication poses the requirements of fast settling time, small channel width, and low phase noise to frequency synthesizer. ΣΔ fractional-N frequency synthesizer is widely adopted due to its excellent characteristics in these aspects. This paper presents a number of system issues and design considerations/tradeoffs which are involved in the design of such a frequency synthesizer from the system point of view. These considerations include selection of loop parameters, choice of key building blocks, and critical system performance issues like spurious tones, quantization noise, in-band phase noise, out-of-band phase noise, and frequency accuracy/resolution. Finally, the future possibilities are briefly analyzed. [ABSTRACT FROM AUTHOR]

This paper deals with the functional-block architecture implementing the new method to measure the carrier frequency error of the single-carrier digital modulations. The method is able to operate on the modulations Mary amplitude shift keying, M-ary phase shift keying, and M-ary quadrature amplitude modulation used in the telecommunication systems. The functional-block architecture obtained from the software-radio SR) architecture is based on the cascade of the analog-to-digital converter (ADC), the digital down converter, and the base-band processing. Looking at the implementation in measurement instrumentation, the performance of this cascaded architecture is investigated by considering three different ADC architectures. They are based on 1) pipeline; 2) single quantizer loop Sigma-Delta (ΣΔ modulator; and 3) multistage noise shaper (MASH) ΣΔ modulator. Numerical tests confirm the important rule of the ADC in this architecture and highlight the interesting performance of he MASH-based ΣΔ modulator for use in advanced measurement instruments. [ABSTRACT FROM AUTHOR]

In this paper, we present a digital oscillator, based on the single-bit ΣΔ modulation principle. With the exception of a front end analog filter, the proposed circuit is entirely digital. The oscillator is achieved by the use of a ΣΔ modulator in the digital resonator loop. A novel topology for constructing stable high-order 1-bit modulators is described. A fourth-order low-pass and eighth-order bandpass oscillators are implemented in field-programmable gate array prototype. The experimental results demonstrate stability and feasibility, achieving more than 110-dR dynamic range for the generated signals. [ABSTRACT FROM AUTHOR]