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A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization

Authors :
Guerra Vinuesa, Oscar
Escalera Morón, Sara
Rosa Utrera, José Manuel de la
Río Fernández, Rocío del
Medeiro Hidalgo, Fernando
Rodríguez Vázquez, Ángel Benito
Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Source :
idUS. Depósito de Investigación de la Universidad de Sevilla, instname
Publication Year :
2005
Publisher :
The International Society for Optical Engineering - SPIE, 2005.

Abstract

This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40°C, 175°C). The modulator architecture has been selected after an exhaustive comparison among multiple ΣΔM topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography.

Details

Language :
English
Database :
OpenAIRE
Journal :
idUS. Depósito de Investigación de la Universidad de Sevilla, instname
Accession number :
edsair.dedup.wf.001..8b31fdfaf20c98e26aa14923dd804bff