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We evaluated a technique that uses power supply charge as the test observable. Charge was computed from the measured supply transient current waveform. Data show that this method is efficient to detect those defects that prevent current elevation (mainly "hard" opens) and therefore represents a valid extension of I/sub DDQ/.

The properties of Gate Oxide Short defects (GOS) in CMOS circuits are investigated identifying the most relevant parameters that determine the behavior of a defective device. Electrical models of the defect are developed and compared with experimentation. Depending upon location and transistor type, GOSs are resistive, diode, parasitic MOSFET or parasitic BJT. We also investigate the necessary conditions to detect a GOS at the circuit level, providing the bases for an efficient ATPG approach.

© 1995 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can be also detected. However, an important set of open and parametric defects escape quiescent power supply current testing because they prevent current elevation. Extending the consumption current testing time, from the static period to the dynamic one (i.e. considering the transient current), defects not covered with I/sub DDQ/ can be detected. Simulations using an on-chip sensor show that this technique can reach a high coverage for defects preventing current and also for those raising the static power consumption.

This work presents a prototype architecture that provides on-line IDDQ measurement for a microprocessor-based system. It has been implemented using an IDDQ testable microprocessor (the Intel 386/sup TM/ EX embedded microprocessor) and an off-chip current sensor. Three current test activation modes are supported. A direct test mode through a sensor dedicated pin, a test mode where the microprocessor controls the off-chip sensor, and a P1149.1 driven test. Measurements and architecture operation are detailed.

A transient current testing technique that computes the charge delivered to the circuit during the transient circuit operation is analyzed. The method is applied to 0.5 /spl mu/m CMOS SRAMs with 1.5 million transistors that passed various logic tests. Results show that Charge Based Testing (CBT) can be used to test submicron ICs and can be applied to non fully static parts.

Transient current (IDD) based testing has been often cited and investigated as an alternative and/or supplement to quiescent current (IDDQ) testing. While the potential of IDD testing for fault detection has been established, there is no known efficient method for fault diagnosis using IDD analysis. In this paper, we present a novel integrated method for fault detection and localization using wavelet transform based IDD waveform analysis. The time-frequency resolution property of the wavelet transform helps us detect as well as localize faults in digital CMOS circuits. Experiments performed on measured data from a fabricated 8-bit shift register and simulation data from more complex circuits show promising results for both detection and localization. The wavelet based detection method shows superior sensitivity than spectral and time-domain methods. The effectiveness of the localization method in the presence of process variation, measurement noise and complex power supply networks is addressed.

We provide an accurate analytical expression for the propagation delay and the output transition time of submicron CMOS buffers that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in deep-submicron technologies. The model is based on the nth-power law MOSFET model and computes the propagation delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.35µm and a 0.18µm process technologies show significant improvements over previously-published models.

A BIST architecture is presented to perform charge-based testing (BIST-CBT) on embedded memories where direct access to I/Os is limited. The proposed architecture includes a charge monitor, a functional test algorithm generator (that applies a standard March B algorithm) and output processing circuitry. The method is based on a charge correlation technique validated experimentally on previous works for submicron SRAMs. The testing methodology implementation has two phases: a short pre-characterisation phase performed during manufacturing test to ensure process-variation immunity, and the actual BIST-CBT. Data from the first phase are processed and loaded in the BIST circuitry registers. The proposed embedded BIST circuitry provides a digital output pass/fail flag that signals the result of the functional and BIST charge analysis (both based on the same March algorithms). To demonstrate the viability of the proposed architecture, a prototype is designed that has been implemented in two parts: the charge monitor is the core of the BIST circuitry, and has been developed in 120 nm CMOS technology, whereas the digital processing circuitry has been implemented on a FPGA device.

A technique to accurately estimate the leakage power in CMOS nanometre integrated circuits (ICs) is presented. The model has similar accuracy to SPICE and represents an important improvement with respect to previous works. The model can be used for a fast and accurate estimation of the standby power dissipated by large circuits.

I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behaviour of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some open defects can be also detected. However, an important set of open defects escapes quiescent power supply current testing because they prevent any current elevation. As a solution, dynamic current testing is investigated. A built-in dynamic current sensor is proposed.

An off-chip monitor is presented that measures the transient supply current of CMOS ICs and provides the charge delivered to the circuit. The monitor is designed to be placed on the automatic test equipment board fixture and automate transient current supply testing. Experimental results demonstrate up to 1 GHz bandwidth operation.

A simple method to evaluate the propagation delay of complex CMOS gates computed from inverter delay models based on the nth-power law MOSFET model is presented. The method is based on a transistor collapsing technique developed for complex gates and takes into account short-channel effects, internal coupling capacitances and the body effect. The propagation delay of complex gates for a 0.18 /spl mu/m technology is evaluated, showing excellent results.

An architecture for simplifying fault diagnosis is presented. The method is applied to circuits incorporating built-in current (BIC) sensors and is based on hardware partitioning, does not increase the number of pins and is independent of the fault diagnosis heuristic at the logic level.

A test technique that uses the charge driven into the circuit computed from the transient power supply current is analysed. Experimental data are provided concerning the merits of this technique and its effectiveness at detecting open defects that do not increase the power consumption (those that cannot be detected with IDDQ).

Many integrated circuit processing defects may cause changes in the value of the quiescent power supply current. Not all of these changes are detectable using classical functional testing techniques. Testing techniques based on the quiescent power supply current inspection have been reported to be efficient in the detection of a wide set of well known physical defects (including bridges and stuck-on). Two quiescent current sensor circuits are proposed and discussed. These circuits are oriented to different testing applications such as the external functional ATE environment, and the built-in self-testing (BIST) design for both on-line and off-line strategies. >

When designing and deploying multimedia systems, it is essential to accurately know about the necessary requirements and the Quality of Service (QoS) offered to the customers. This paper presents two open-source software tools that contribute to these key needs. The first tool is able to measure and register resources consumption metrics for any Windows program (i.e. process id), like the CPU, GPU and RAM usage. Unlike the Task Manager, which requires manual visual inspection for just a subset of these metrics, the developed tool runs on top of the Powershell to periodically measure these metrics, calculate statistics, and register them in log files. The second tool is able to measure QoS metrics from DASH streaming sessions by running on top of TShark, if a non-secure HTTP connection is used. For each DASH chunk, the tool registers: the round-trip time from request to download, the number of TCP segments and bytes, the effective bandwidth, the selected DASH representation, and the associated parameters in the MPD (e.g., resolution, bitrate). It also registers the MPD and the total amount of downloaded frames and bytes. The advantage of this second tool is that these metrics can be registered regardless of the player used, even from a device connected to the same network than the DASH player.

[EN] In this work, we study the effects of the width of the sound source in several acoustical virtual room models with different topologies, sizes and uses, calibrated with commercial software. To achieve this aim, a square distribution of sound sources with variable side length has been considered. We have auralized four channels of speech signal and musical signal in three different locations in each room. By using signal processing techniques, a comparison of multisource auralizations with the ones obtained from a single source in the middle of the stage is made. Also, the variations between the usual room parameters obtained from these simulations are analyzed, in order to show the effect of the hall in the objective evaluation according to the source width., This study has been supported with FEDER funds. The Spanish Ministry of Science and Innovation also supported the present study in a coordinated investigation project framework (references BIA2003-09306-C04 and BIA2008-05485).

SRAM cell stability analysis is typically based on Static Noise Margin (SNM) evaluation when in hold mode, although memory errors may also occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SNM of OAM cells during write operations. The Word-Line Voltage modulation is proposed as an alternative to improve cell stability when in this mode. We show that it is possible to improve 8T OAM cells stability during write operations while reducing current leakage, as opposed to present methods that improve cell stability at the cost of leakage increase.

In this work the need for specific ATPG targeting Gate Oxide Short (GOS) defects is highlighted. Many works have been done to develop ATPG for resistive shorts considering both external bridges between gates, and intra-gate shorts. We show with some examples that in some cases the detection of all detectable intra-gate bridging faults does not imply covering all detectable GOS defects in the circuit. A commercially available standard gate library is analyzed to demonstrate that this problem may appear in real applications. An ATPG tool oriented to detect GOS defects with I/sub DDQ/ testing is presented. ATPG experiments on a set of benchmark circuits show the efficiency of the proposed tool.

A circuit level model for failures causing shorts in the oxide of the gate electrode (GOS) is presented. Experimental results show that the influence of the width of a short between gate and channel in a MOS device is low in comparison with the location in the length direction. The model takes advantage of this result. A unidimensional (length) model for GOS faults is proposed. The experimental results have been obtained by measuring devices with faults where the failures have been introduced by design. The model reduces the complexity of electrical simulations (in comparison with previous unidimensional models) when parametric deviations on an assumed GOS-faulty circuit are analyzed. Results verifying the adequacy of the models and comparison with other research data are presented, considering the effect of the failure on the input and output characteristics of the devices. >

We evaluated a diagnostic technique based on the charge delivered to the IC during a transition. Charge computed from the transient supply current is related to the circuit internal activity. A specific activity can be forced into the circuit using appropriate test vectors to highlight possible defect locations. Experimental results from a small test circuit and a 256 K SRAM demonstrate the experimental viability of the technique. The theoretical foundation is also discussed.

The aggressive scaling of CMOS process technology poses serious challenges on the lifetime reliability of ICs due to the stringent operating conditions and the increase of process parameter variations. Reliability has become an important concern of semiconductor industry and should be improved with each scaled technological node in order to enhance yield. From semiconductor perspective, reliability is the ability of a device to perform its required function under stated conditions for a specified period of time. A semiconductor device fails when the response parameters from the device can no longer perform its intended function. Device failure may occur at any moment of device's lifetime. As technology scales down, the likelihood of manufacturing defects such as open and bridge defects increases due to the growth rate of interconnections. Some of these defects are hard to be detected by traditional test methods and could result in test escapes posing reliability issues. In addition, soft errors have emerged as an important reliability concerns in SRAM memories due to lower node capacitance and more stringent operating conditions.