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A highly integrated high-power transmitter has been designed in a high breakdown GaAs MMIC technology. The transmitter includes, on top of an S-Band 10 W class-F HPA, a DC/DC converter and its associated gate driver, the full voltage regulation control loop, which provides a significant step for phased array transmit chain miniaturization and transmit pulse flexibility. The complete transmitter chip is assembled in a standard QFN package. The DC/DC converter operates at a switching frequency around 100MHz with an efficiency of 82%, including the on-chip control circuits. The overall DC to RF efficiency of the integrated transmitter is 32%. © 2012 IEEE.

International audience; Dielectric barrier discharge (DBD) lamps, being capacitive loads, must be associated with bidirectional current sources for an appropriate control of the transferred power. Pulsed current source supplies, which are known to offer very interesting performances, require specific power switches that are able to manage bidirectional voltage and unidirectional current at much higher frequencies (several hundreds of kilohertz) than commercial thyristors. This paper proposes the detailed design of such a high-speed synthesized thyristor, using discrete components: a MOSFET in series with a high-voltage (HV) diode and a logic circuit that controls its gate. This switch is associated with an optimized self-powered driver, which is a very efficient solution to handle the perturbations associated with the HV and high-frequency operation. Experimental application of this device for DBD excimer lamp supply is proposed.

peer-reviewed Modern isolated switched mode power supplies (SMPSs) commonly utilise digital control methods over their classical analogue counterparts. These methods are now preferred for ease of programmability and implementation, scalability and they also accommodate advanced control techniques such as adaptive control. However in most digital implementations, inexpensive opto-couplers are still used to transmit analogue signals across the isolation barrier. It is well known that these types of opto-couplers suffer many drawbacks including variable gain due to ageing effects. The main research contribution in this thesis focuses on developing and implementing a full bi-directional digital data-link between both sides of the isolation barrier, i.e. all signals (feedback and auxiliary) are digitalised and transmitted as a single encoded data stream across the isolation barrier. A key advantage of this scheme is that only a single set of digital couplers is required to achieve bi-directional communication, when compared with its analogue counterpart which would require multiple opto-couplers. This proposed scheme is therefore a more cost-effective and efficient solution and does not suffer from performance degradation due to ageing effects. To reduce the size and improve power efficiency and loop response, switching frequencies are continually increasing. Higher switching frequencies reduce the transmission window and therefore the number of bits to be transmitted across the isolation barrier per switching cycle needs to be minimised. To achieve this objective for the bi-directional data-link proposed, a new state-dependent encoding scheme for the required analogue-to-digital converter (ADC) has been specifically designed. This state-dependent encoding scheme ensures a high resolution during the steady-state operation of the SMPS while still providing adequate accuracy during transients. Along with the state-dependent ADC, two digital pulse width modulators (DPWMs) for single- and multi-phase SMPSs have been designed for use with the proposed communication system. These DPWMs were implemented using field programmable gate arrays (FPGAs), but are also suitable for application specific integrated circuits (ASICs). The DPWM designs only require a small number of logic elements while achieving high speed and high resolution, temperature independence and good scalability. This has been achieved using a hybrid approach which uses a novel fine-resolution block along with a coarse resolution block. This approach takes advantage of digital clock manager (DCM) blocks available on most commercial FPGAs available today. Manual placing and routing techniques result in high linearity and monotonic behaviour. For test purposes, the bi-directional communication scheme has been implemented on FPGAs and verified using a custom-built SMPS board.

A highly integrated high-power transmitter has been designed in a high breakdown GaAs MMIC technology. The transmitter includes, on top of an S-Band 10 W class-F HPA, a DC/DC converter and its associated gate driver, the full voltage regulation control loop, which provides a significant step for phased array transmit chain miniaturization and transmit pulse flexibility. The complete transmitter chip is assembled in a standard QFN package. The DC/DC converter operates at a switching frequency around 100MHz with an efficiency of 82%, including the on-chip control circuits. The overall DC to RF efficiency of the integrated transmitter is 32%. © 2012 IEEE.

An S-band radar transmitter MMIC is reported containing a class-F power amplifier and a switched mode power supply. The integration of the power supply offers the possibility to optimize the power amplifier bias voltage for each individual device in a AESA antenna. This has several advantages such as amplitude tapering with preservation of efficiency, the reduction of spurious signals due to decoherence and the removal of single point of failure. © 2012 IEEE.

Switched-Capacitor Converters (SCC) suffer from a fundamental power loss deficiency which make their use in some applications prohibitive. The power loss is due to the inherent energy dissipation when SCC operate between or outside their output target voltages. This drawback was alleviated in this work by developing two new classes of SCC providing binary and arbitrary resolution of closely spaced target voltages. Special attention is paid to SCC topologies of binary resolution. Namely, SCC systems that can be configured to have a no-load output to input voltage ratio that is equal to any binary fraction for a given number of bits. To this end, we define a new number system and develop rules to translate these numbers into SCC hardware that follows the algebraic behavior. According to this approach, the flying capacitors are automatically kept charged to binary weighted voltages and consequently the resolution of the target voltages follows a binary number representation and can be made higher by increasing the number of capacitors (bits). The ability to increase the number of target voltages reduces the spacing between them and, consequently, increases the efficiency when the input varies over a large voltage range. The thesis presents the underlining theory of the binary SCC and its extension to the general radix case. Although the major application is in step-down SCC, a simple method to utilize these SCC for step-up conversion is also described, as well as a method to reduce the output voltage ripple. In addition, the generic and unified model is strictly applied to derive the SCC equivalent resistor, which is a measure of the power loss. The theoretical predictions are verified by simulation and experimental results.

International audience; A sliding mode control (SMC) algorithm dedicated to switching mode power supply (SMPS) is validated experimentally in a FPGA. A constant high switching frequency is obtained using an hybrid digital pulse width modulator (DPWM). The proposed SMC strategy cooperates with an off-chip ADC and the hybrid DPWM takes advantage of a digital clock manager (DCM) and a counter-comparator based DPWM with a Multi-stAage-noise-SHaping (MASH) ¿-¿ modulator. Experimental results verify closed-loop operation at switching frequency up to 4 MHz only limited by the discrete SMPS and its dynamic response less than 30 ¿s. Simulation results show that the complete digital controller chip in 0.35 ¿m CMOS process takes 0.72 mm2 of silicon area and the current consumption is roughly 100 ¿A/MHz for a dynamic response of 16 ¿s.

Operation of a S/C power system based on the SMP technique for Maximum Power Point Tracking management is the subject of the present work. Improvements both in transient behaviour and EMC are reported and experimental results are analysed with reference to specific design solutions. Particular design techniques are then presented, specifically developed to avoid that the increased circuit complexity could negatively affect the system reliability, especially in the cases where Commercial Off The Shelf components are used. Basically, the circuits for fundamental operation, designed on the basis of classical and very reliable schemes, are separated from those dedicated to the SMP control, based on digital integrated circuits, with an higher failure rate. Then, the interfaces between the two blocks are designed so that the SMP control circuit can only affect (positively) the system operation when it is correctly operating, while its interactions with the basic circuit are blocked if errors are detected.

Switched-mode power supplies in variable-frequency drives often combine good electrical efficiency with generous production of conducted emission. The common-mode (CM) current through the output-to-motor cablemay perturb nearby systems via cable-to-cable crosstalk. Parameters relevant for the coupling are the rise–fall times and amplitude of the output current and voltage, and types and lengths of the cables. Of the many techniques to reduce the crosstalk, we investigated a particular one: reduction of the CM current by the armor of the motor cable. The armor is intended for mechanical protection, but may also substantially reduce the crosstalk. In an actual installation, we measured the transient current through the three phase leads of a motor cable. The cable length was 85 m, and it was buried in wet soil for most of its length. We also measured the transfer impedance of the armor up to 10 MHz, and used this to calculate the overall CM current in a coupled cable model using assumed reasonable values for the cable and soil parameters.Measurements and model results agreed well on the amplitude of the dominant resonance at about 300 kHz. The ratio of the inside transients to CMcurrent was a factor of 20.

Differential-mode buck-boost inverters have merits such as reduced switch number, ability to provide voltages higher or lower than the input voltage magnitude, improved efficiency, reduced cost and size, and increased power density, especially in low-power applications. There are five buck-boost inverters that can provide flexible output voltage without the need of a large electrolytic input side capacitor, which degrades the reliability of inverters. The continuous input current of these inverters is appropriate for maximum power point tracking operation in photovoltaic and fuel cells applications. Three of the five inverters can be isolated with high-frequency-link transformers where the common-mode leakage current can be mitigated. However, the performance and control of such converters have not been discussed in detail. In this paper, the five possible single-stage three-phase differential-mode buck-boost inverters with continuous input current are investigated and compared in terms of total losses, maximum ripple current, total harmonic distortion, and device and passive element ratings. In addition, the possible methods are presented for eliminating the input third-order harmonic current, resulting from the stored energy in the passive elements, as well as the output second-order harmonic currents. The ability for isolating the input and output sides of the inverters with a small-high frequency transformers is discussed. A changeable-terminal 2.5-kW bidirectional inverter is used to validate the design flexibility of the inverter topologies, when digital signal processor-controlled. NPRP Grant NPRP 4-250-2-080 from the Qatar National Research Fund (a member of Qatar Foundation). Scopus

This paper describes the behaviour of fusing systems in the presence of both nonlinear single phase and three phase loads. Such loads, producing harmonic currents, yield high peak currents. Specifically, IT-equipment where the nonlinearity is caused by the bridge rectifier of the switching power supply and variable speed drives are considered. The paper presents the study of the influence of the waveform of the neutral conductor current on the behaviour of the fusing system. Using a programmable power source, an arbitrary voltage waveform is generated. Each phase is loaded by a variable number of resistors. For different set ups of the power source and load conditions, the phase currents are analysed using on-line monitoring. The ratio of the phase RMS to peak current on the behaviour of fusing systems is analysed.

This paper deals with the analysis of the effects of radio frequency conducted interfering signals (RFI) on integrated circuits (ICs). After reviewing the basic results of the susceptibility analysis of operational amplifiers and smart power integrated circuits, the behavior of several pin-to-pin compatible control ICs for PWM current-mode switching power supplies (SMPS) has been tested in the presence of both continuous wave interfering signals (CW) as well as of pulsed noise signals (underground condition). The tested ICs were selected between some common models available on the market. The variations of the primary functional parameters (inner voltage reference, switching frequency, etc.) are evaluated in different test conditions. The paper gives a comparative view of the results, focusing on the key macroscopic effects.

The improvements in modern circuit technology reduce system size, improve the efficiency and reduce the cost. Utilization of soft-switching resonant power converters give high density high effeciency power converters for narrow output voltage ranges. To overcome this a cascaded switched-capacitor dc-dc converter is used to implement a Universal Serial Bus Power Delivery compliant charger. The converter uses a custom designed application specific integrated circuit designed for switched-capacitor dc-dc converters and wide bandgap technology allowing high frequency, high power design. The converter achieves peak efficiencies up to 98 % at 60 W output power with a corresponding junction temperature of 50 ◦C. Worst case junction temperatures reach 64 ◦C and is viable for use in longterm battery charger systems. The cascaded power stages take up 14 mm × 22 mm.