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Alternative data paths for the cascaded integrator-comb (CIC) decimator are presented that can be derived upon applying one or two modifications. In the first modification, the integrator-comb pair that surrounds the downsampling register is replaced by a simpler Integrate-and-Dump (ID) block that performs the same decimation task. The resulting data path is referred to as CIC-ID. In the second modification, the remaining comb filters are replaced by a timemultiplexed comb, and the resulting data path is referred to as CIC-ID-TMUX. Compared with a classic N -stage CIC, CIC-ID saves one arithmetic unit and one register, whereas CIC-ID-TMUX uses the same number of registers but trades ( N - 1) arithmetic units for a simpler two-to-one multiplexer. Both CIC-ID and CIC-ID-TMUX perform slightly fewer arithmetic operations per output sample because of the absence of the comb filter absorbed by the ID block. Pruning formulas for both architectures are presented along with implementation details.

Threshold logic (TL) circuits gain increasing attention due to their feasible realization with emerging technologies and strong bind to neural network applications. In this work, we devise techniques for automatic synthesis and verification of TL circuits based on constraint solving. For synthesis, we formulate a fundamental operation to collapse TL functions, and derive a necessary and sufficient condition of collapsibility for linear combination of two TL functions. An approach based on solving the subset sum problem is proposed for fast circuit transformation. For verification, we propose a procedure to convert a TL function to a multiplexer (MUX) tree and to pseudo-Boolean (PB) constraints for formal Boolean and PB reasoning, respectively. Experiments on synthesis show that the collapse operation further reduces gate counts of synthesized TL circuits by an average of 18%. Experiments on verification demonstrate good scalability of the MUX-based method for equivalence checking of synthesized TL circuits, and efficiency of PB constraint conversion in cases where the conjunctive normal form (CNF) formula conversion and MUX tree conversion suffer from memory explosion.

This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser po...

A broadband mode (de)multiplexer [(De)MUX] is proposed and experimentally demonstrated based on a triple-waveguide coupler (TWC) with the phase-matching of a multimode access-waveguide. The tolerance to the operating wavelength and fabrication error of the proposed mode (De)MUX can be relaxed with the aid of the wider access-waveguide and the middle waveguide. The optimized mode (De)MUX is with a coupling length of $48~\mu $ m and a broad bandwidth of >122 nm with the mode crosstalk of

The design of a novel 1 × M fold-back type wavelength selective switch (WSS), which has fewer waveguide crossings than a conventional integrated WSS, is reported. The WSS is composed of interleavers, 1 × M optical switches, and arrayed waveguide gratings (AWGs). Switches are combined with AWGs by fold-back waveguides, and each AWG works as both a demultiplexer and multiplexer thus avoiding center wavelength mismatch caused by fabrication errors. Waveguide crossings cause excess crosstalk and loss in lightwave circuits. By using a fold-back architecture the number of crossings can be reduced to less than half that of a conventional design. We discuss the operating principle, the design method, and the scalability of the fold-back type WSS. Furthermore, the switching operation of a 200-GHz spacing, 20-channel, 1 × 2 silicon WSS in a fold-back configuration on a 5 mm × 10 mm SOI chip is demonstrated. This has 15 waveguide crossings in a path, of which six are additional crossings with monitor waveguides. The average insertion loss and average extinction ratio are 29.6 dB and 10.9 dB, respectively.

Today, we are evident to the revolution of the automotive industry and its demand for high bandwidth sensor fusion. Multiple high bandwidth sensors are connected, generating tremendous amount of data to be transferred in real-time in harsh environment, i.e., multi-gigabit intra-vehicle networks. Plastic optical fiber (POF) is an attractive medium for these multi-gigabit intra-vehicle networks due to its inherent EM compatibility, galvanic isolation, low weight, high tolerance to mechanical vibrations, low bending loss, and easy handling. However, commercial off-the-shelf PMMA based POFs are bandwidth-length product limited. Here, we suggest increasing the spectral efficiency using spatial-division multiplexing (SDM). In this article, we have experimentally demonstrated a low cost and eye-safe 3 × 3 multiple-input multiple-output (MIMO) SDM system over a 15 meters multicore (MC) POF using commercial optical components, e.g., RC-LEDs and Si-PIN photodiodes. A 3 × 1 spot-based cores coupler spatial multiplexer was developed to couple the optical components with the MC-POF. This system achieved raw data rates of 1.5 Gb/s and 2.4 Gb/s using offline-processed MIMO equalization. The proposed system enables a flexible and scalable optical MIMO system that can meet the requirements of the automotive industry.

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates $0.43~\mu \text{J}$ and ${0.82~\mu \text {J}}$ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and $0.56~\mu \text{W}$ , respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates $1.25~\mu \text {J}$ per measurement, achieving a resolution of 18.7 mm at 0.55 m.

Logic locking is a new technique to prevent an integrated circuit from hardware Trojan, piracy, overbuilding, etc. Most of the well-known logic locking techniques are vulnerable to sensitization and cone based attacks. Though the existing techniques try to thwart these attacks, they are highly circuit topology dependent and require significant overhead. Therefore, this paper presents a new lightweight logic locking technique that effectively neutralizes the sensitization and cone based attacks. We further propose new multi key-input gates and a new replacement-based logic locking algorithm. The replacement of design gates with our multi key-input gates not only effectively prevents the key-sensitization and signal probability skew based removal attacks but also removes rare nets from design. On the other hand, our logic locking algorithm significantly increases the brute-force attempts against cone-based attack with minimum replacements by replacing the nodes which have the maximum number of fan-outs and paths to output nodes. We evaluate our technique using ISCAS benchmarks, and the results demonstrate that the proposed key-gates on average reduce 32 percent area-overhead over the XOR/MUX key-gates, whereas our algorithm on average doubles the effective key size while reducing 50 percent area overhead over the best-known technique.

A microwave resonator array is integrated with liquid metal to select an individual resonator response within a resonator array, enabling simple and accurate analysis for dielectric sensing. Galinstan, a liquid metal, acts as a multiplexer by inducing a capacitive load to the nearby resonator, lowering its resonant frequency, and thereby isolating its resonant response from other resonators in the array. The liquid metal could be positioned within a fluidic channel to be above any of the resonators, which tuned the resonant frequency from 3.9 to 3.3 GHz where it can be analyzed individually. The resonators showed a consistent response to liquid metal tuning, with tuning error measured below 30 MHz (5%). The sensor also exhibited stable sensitivity to test materials placed on the selected resonator, with a maximum resonant frequency shift of 300 MHz for a dielectric test material (ε = 10.2) and almost no variation in resonant amplitude. The selected resonant response was only sensitive to materials on the selected resonator, and was unaffected by test materials, even when placed on other resonators. The presented design enabled robust and accurate detection of materials using planar microwave resonators that can be controlled at a user’s convenience, specifically for use in systems where multiple parameters or system settings may need to be individually determined.

The aim of this research paper is to provide a general overview of Mux and Demux. This research paper starts with a brief description of these electronic devices. A multiplexer, also known as a data selector, is a system that can merge two or more data lines into a single data line for transmission to another venue. A demultiplexer, also known as a data distributor, is a device that divides a single, multiplexed data transmission line into individual data signals. This article addresses the 1 to 4 multiplexer and demultiplexer. Various applications of mux and demux in the fields of telephone and satellite communication, as well as uses of computer science, are discussed.

This article presents a methodological technology for studying digital logic devices. Recommendations on the technology of teaching digital logic devices using rational, best methodological methods and teaching techniques are given. The proposed topic is "Multiplexer and demultiplexer". Studying methods used: modular studying, developmental studying, demonstration (frontal), step-by-step studying, problem-based studying. The process of implementing learning technology explained by the plan prepared for the lesson (mostly the basics of electronics in Kazakhstan are not included into the educational basis of the school and are only taught in higher educational institutions, therefore, the basic learning range, conventionally referred to in the lesson plan, seminars or lectures.

Tremendous and inescapable application of full adder adds impetus to its optimization till high-end performance. Use of full adder propels the design engineer to unearth various digital circuits, whose implementation otherwise would not be a cakewalk. This paper exhumes finest 3-bit parity checker in terms of power dissipation (PWR) and energy-delay product (EDP) variability. MCML (MOS Current Mode Logic) based implementation is practiced to improvise the circuit. Further, in this treatise, above mentioned 'CNFET-based 3-bit MCML parity checker' (used as full adder) and Transmission Gate based multiplexer is used to implement a novel design of '4-Bit 4-Tube CNFET based ALU' at 16-nm Technology Node. This CNFET-based ALU thus implemented is further compared with its CMOS counterpart. Simulation results establish the superior performance of proposed '4-Bit 4-Tube CNFET-based ALU' in terms of propagation delay (tp) (9.04×), PWR (1.68×), PDP (15.09×) and EDP (136.42×). The exposition establishes that the idea of using a 'CNFET-based 3-bit MCML parity checker' to design a new ALU circuit, i.e., '4-Bit 4-Tube CNFET-based ALU' would provide a gigantic horizon for a design engineer.

The main purpose of this paper is to focus on the design of Viterbi Decoder (VD) with low power, which is significant for receiver section of data communication applications such as Radar, Satellite, Telephone and Automatic speech recognition. The Viterbi decoder algorithm consists of three most important blocks – Branch Metric Unit (BMU), Add Compare and Select (ACS) Unit and Survivor Memory Unit (SMU). BMU computes the metrics between the input and output state transitions. ACS unit include the Path Metric Unit (PMU), which computes the metrics with the sequence to a next state of a path and selects the lower metric value as a survivor path. SMU stores the data bits which utilizes the trace back method to fetch the likelihood path from the current state to a previous state. An ACS unit is an essential block for VD. The basic recursive ACSU design consists of Ripple Carry Adder (RCA), Comparator and a Selector block, which consume more area, power and operates with high junction temperature. To overcome these drawbacks, a modified ACSU design is implemented with recursive cancellation technique. ACS unit is modified by including a trace back mechanism to obtain a low latency and high speed in VD. It is designed with low complexity multiplexers, adders, logical AND gate and comparator block. This breaking recursive ACSU design utilizes less power, high throughput, low latency and also operates at low temperature. This analysis and simulation process are accomplished using Vivado Design Suite.

A dual channel system based on a dual-parallel Mach–Zehnder modulator (DPMZM) is proposed for simultaneous measurement of angle of arrival (AOA) and Doppler frequency shift (DFS). The echo signals are received by two antennas and sent into two sub modulators (sub-MZMs) of the DPMZM respectively. The transmitted signal is fed into one of the sub-MZMs to act as a local oscillator signal. The upper and the lower sidebands of the output signal from the DPMZM are separated by a wavelength-division multiplexer (WDM) to form two channels. By measuring the power of the beating signal of the two channels, the AOA can be measured and the phase measurement error is less than 3.4° in the range of about 300° (The AOA is measured from ±10° to ±90°). Moreover, the system can measure DFS with the measurement error less than 0.07 Hz and determine the DFS direction by comparing the phase relationship between the two channels. The system structure is simple and compact, which is a simple and effective solution for modern radar and electronic warfare receiver.

In this brief, we show how to derive all the optimum multi-path delay commutator (MDC) fast Fourier transform (FFT) hardware architectures in terms of delays and multiplexers and calculate the number of such architectures. The proposed approach is based on analyzing the orders at the FFT stages that lead to optimum number of delays and multiplexers. The results show that there exist a large number of optimum MDC FFTs. This large design space can be explored in the future in order to design efficient MDC architectures that not only optimize the number of delays and multiplexers, but also other figures of merit such as the number of rotators or the input/output data order.

Designing a high-quality switch block ensures the efficient data transmission in digital circuits and systems. In this paper, an innovative 2:1 multiplexer is successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs) at 180 nm SOI technology node. Optimization of the reservoir thickness and gate work function of the S-FED satisfy high ION/IOFF ratio and noise-immunity. DC, AC, and transient mixed-mode simulations are employed to scrutinize and compare performance of constituent logic gates based on the S-FED and CMOS. Simulation results demonstrate superior noise margins up to 100 mV for the S-FED-based inverter compared with the CMOS-based counterpart. Furthermore, the S-FED-based transmission gate with switching frequency of 38.9 GHz can act as a high-speed alternative for the CMOS-based one. Both multiplexer architectures configured by the S-FED and CMOS are compared in terms of performance parameters. In this regard, average power consumption and PDP quantities for the S-FED-based multiplexer reveal significant reductions by about 2 and 3 orders of magnitude, respectively, compared with the CMOS-based one. In addition, propagation delay time increases drastically with scaling power supply in the CMOS-based multiplexer; while, this increase is suppressed for the S-FED-based version.

Almost 50% of random logic power is consumed in System-on-chip (SOC) by the memory latch circuits. VLSI designers of high performance SOC are struggling to realise a performance rich and energy efficient design method. A number of power optimisation techniques and methods have been suggested which ultimately increase hardware complexity. Consequently, due to more number of components the cost as well as the area used on chip increases. In this study the design and demonstration of D latch and S-R latch based on the Silicene based multiplexer device (SMLD) using Verilog-A is done. The working of SMLD based latches is validated through circuits simulations in SPICE. The SMLD based D latch and S-R latch show an improvement in hardware reduction by 93.75% and 50% respectively as compared to CMOS based D latch and S-R latch. Also the improvement in area utilization on chip by 94.10% and 52.83% is achieved by SMLD based D latch and S-R latch respectively.

Wavelength Division Multiplexing (WDM) networks with reconfigurable optical add/drop multiplexers (ROADMs) realize automatic scheduling and restoration at the wavelength level and are therefore part of the solution to meet increasing bandwidth and routing flexibility requirements for transport networks. The wavelength selective switch (WSS) is the key component in all commercial ROADM systems. Liquid crystal on silicon (LCoS) technology dominates current WSS installations as LCoS-based WSS can support Flexgrid technology enabled networks, and high port counts with excellent performance. WSS designs are becoming increasingly specialized for a wide variety of applications. For single WSS used in broadcast and select (B&S) architecture, superior port isolation is key for the desired signal to be filtered from the whole spectrum. While for twin WSS deployed in route and select (R&S) nodes, many features are desired for various network applications. These include multiple common ports, premium ports with superior port isolation, and high port counts. Future WSS may be asked to address a number of different end user applications, and as such there is a demand for combinations of custom spectrum range, compact form factors, increased WSS port count, low cost, thermal and mechanical ruggedization. The first commercially available quad WSS is part of this increasing trend of utilization of WSS throughout network architectures.

The optical fiber deployed in the metropolitan infrastructure carrying high-speed WDM traffic data is used also for network surveillance, identifying and localizing the onset of vibrations and dynamic stress events, potentially dangerous for the integrity of the fiber telecom asset. A coherent approach is adopted in a counter-propagating interferometer to develop a sensing system exploiting the ring layout of the metro network. With respect to usual dual Mach-Zehnder interferometric sensors, where typically the reference arm is kept isolated, in our arrangement we use as reference arm a fiber inside the same deployed cable, minimizing the impact of the city strong environmental noise. Preliminary assessments of the proposed sensing solution have been experimented in a metro ring of 32-km standard single-mode fiber deployed in the city of Turin, Italy, devoted to telecom applications. The sensor is demonstrated to operate preserving the coexistence with the high-speed WDM telecom traffic. With respect to complex and expensive sensing solutions based on pulsed phase-OTDR techniques, in the present case continuous-wave counter-propagating optical signals are exploited and the spatial resolution in dynamic event localization depends only on the receiver sampling rate: in our implementation, by adopting off-the shelf low-cost commercial 20 MS/s sampling boards, 10-meter spatial resolution is experimentally achieved. The proposed sensing solution provides significant added value to the deployed metro fiber infrastructure and the same interferometric approach based on the counter-propagating layout can be easily exploited in metro networks even in case of presence of optical nodes equipped with reconfigurable optical add-drop multiplexers useful for WDM traffic routing.

The approach to designing digital circuits using three-dimensional (3D) perpendicular nanomagnetic logic (pNML) is thoroughly investigated. Nanomagnetic logic (NML) technology eventually optimizes the circuit performance in comparison with conventional metal–oxide–semiconductor (MOS) technology, which suffers from the hot carrier, velocity saturation, and short-channel effects, which may considerably degrade device performance. In contrast, nanomagnetic logic is immune to radiation; it behaves as nonvolatile memory and shows zero leakage current, as required for use in high-speed and low-cost nanoelectronics applications. In this paper, novel and organized designs, e.g., for 3D Ex-OR, parity generator, parity checker, multiplexer, and arithmetic logic unit (ALU) functionality, are synthesized using pNML technology. Previous designs are not compact in terms of delay, layer count, or bounded area. To overcome this, new designs for the mentioned functionalities are proposed based on pNML with smaller area and lower latency compared with previous circuits.

Waveguide components have been widely explored for several decades, due to their inherent merits of low insertion losses, high quality ( Q ) factors, and a significant power-handling capacity. Historically, cavity-based narrowband filters and multiplexers have been explored and designed for base stations and satellite applications. Compared with using single-mode resonators (SMRs), the implementation of multiple-mode resonators (MMRs) in waveguide structures is a promising solution to dramatically reduce the circuit volume and improve the frequency selectivity. Taking advantage of MMR techniques, various innovative waveguide structures have been proposed for a wide range of application scenarios. This article presents an overview of advances in microwave multiple-mode waveguide components, including narrow-, wide-, and multiband filters; multiplexers; three-state diplexers; crossovers; and balanced/unbalanced elements. Representative examples and their results are comprehensively discussed and summarized.

We introduce recently developed space division multiplexing (SDM)-associated technologies into optical wireless communications (OWC) and propose to use incoherent and low-coherence spatial modes to realize optical broadcasting with reliable performance by mitigating coherent interference. We experimentally demonstrate reconfigurable optical beam steering using a programmable multi-plane light conversion (MPLC)-based mode multiplexer (MMUX) and realize point-to-multi-point optical wireless communications with low-loss up-link optical beam combining and reach extension using multimode fiber (MMF). Both incoherent and low-coherence spatial modes can be generated employing cost-efficient components such as a multimode vertical cavity surface emitting laser (MM-VCSEL) and broadband amplified spontaneous emission (ASE) noise source.

Brain tumors are one of the most lethal diseases in the world. The segmentation of brain tumor is of great significance for physician in formulating appropriate diagnostic and treatment plans, not only accurate but also efficient 3D segmentation algorithms are urgently demanded in clinical practice. Nowadays, several 3D convolution neural networks have achieved impressive segmentation performance. However, these architectures come with extremely high computational overheads due to the extra depth dimensionality in 3D convolution, which may make these models prohibitive from practical large-scale clinic application. In this work, we aim at designing a more efficient and lightweight network without accuracy reduction for real-time segmentation of magnetic resonance images. To this end, we propose a multi-branch sharing network which consists of novel multi-branch sharing units. Different from other works, our proposed multi-branch sharing units focus the information sharing and communication between grouped layers by leveraging a Multiplexer operation, which can reduce the computational cost significantly while maintaining decent performance. Extensive experimental results on the BraTS2018 challenge dataset show that the proposed architecture achieve real-time inference while maintaining high accuracy for 3D brain magnetic resonance image segmentation.

In this article, a beyond 1.6 Tb/s net rate pulse amplitude modulation (PAM) communication system is experimentally demonstrated for 20 m rack-rack optical interconnects with low cost intensity modulation direct detection (IM-DD) architecture, which is enabled by mode division multiplexing (MDM) and wavelength division multiplexing (WDM). The MDM with three linearly polarized modes is realized by a multiplane light conversion (MPLC) mode multiplexer with the maximum modal crosstalk less than – 20 dB. The experimental results show that 2.01 Tb/s (1.84 Tb/s net rate) PAM-6 signal carried on three modes and four wavelengths is successfully transmitted over 20 m standard OM2 multimode fiber (MMF) with the BERs of received signals from all channels below hard decision forward error correction (HD-FEC) threshold of 3.8 × 10–3. Look-up table (LUT) pre-distortion and Volterra nonlinear equalizer (VNLE) are employed for nonlinear impairment mitigation to improve the system performance. Compared to linear feedforward equalizer (FFE), 0.3 dB and 1 dB receiver sensitivity improvements are obtained by LUT and VNLE, respectively. To the best of our knowledge, our proposed scheme achieves the highest bit rate of 167.5 Gb/s per wavelength in MDM system with IM-DD structure. The experimental results show that our proposed PAM MDM communication scheme is a promising candidate for future 1.6 Tb/s short reach rack-rack optical interconnects.

Optical fiber transfer delay (OFTD) measurement with high accuracy and stability is an urgent demand for many applications such as fiber-optic sensors and fiber-based distributed systems. In this article, we propose a novel method using fiber-optic microwave interferometry to meet the above practice demand. Two incoherent optical carriers with different wavelengths are coupled into an intensity modulator driven by a microwave signal. The intensity-modulated signal is then divided into two portions through a dense wavelength division multiplexer. One portion directly passes through the reference path while the other undergoes the transfer delay of a fiber under test (FUT). After photo-detection, two probe signals that undergo different delays are recovered and superimposed. By sweeping the microwave frequency, periodic microwave interference fringe is generated. Then, OFTD measurement is achieved by measuring the frequency of the last valley in the interference fringe. Experimental results show that a system stability of ±0.02 ps, an accuracy of ±0.07 ps, and a measurement range of at least 500 m are achieved.

Full adder cell is an important module in arithmetic and processing systems whose performance has a great impact on performance of the whole system. By continuous scaling of the MOS transistors, some challenges and problems appear such as high leakage dissipation for which emerging technologies have been studied as a solution. Carbon nanotube field effect transistor (CNFET) is one of the most potential alternatives for the traditional MOSFET. The threshold voltage of a CNFET can be adjusted by tuning its CNT diameter. This property makes them to be appropriate for designing voltage mode multi-valued logic circuits. In this paper, a novel multiplexer-based ternary full adder cell using CNFET is presented. The proposed circuit is simulated and compared with the state-of-the-art designs using Synopsys HSPICE simulator. Simulations are done to investigate the effect of process (P), voltage (V) and temperature (T) variations on the circuit. The results show that the proposed design reduces the energy consumption by about 54% than the best reported design, while is robust against PVT variations.

Due to the benefits of low power, high bandwidth and complementary metal-oxide-semiconductor (CMOS) compatibility, the design of optical circuits has spurred great attention among researchers in the domain of electronic design automation. With this motivation, all-optical combinational and sequential circuits such as adders, multiplexers, multipliers and flip-flops have been explored in recent times. In this paper, we have explored the designs of all-optical array multiplier and four types of parallel multipliers (carry save adder multiplier, Wallace tree multiplier, Dadda multiplier and reduced area multiplier) using two different design approaches named as Design1 and Design2. In order to design these multipliers, semiconductor optical amplifier (SOA)-based Mach–Zehnder interferometers (MZIs) have been used as the basic optical component. The basic MZI switch, full adder and 2-bit multiplier have been simulated using OptiSystem software to analyze the power loss. Furthermore, an all-optical merged multiplier has been designed, which is often used in digital signal processors. In comparison with other designed multipliers, it is evident from the simulation results that the MZI-based reduced area multiplier of Design1 approach has the highest performance in terms of speed, while the MZI-based carry save adder (CSA) multiplier with Design1 approach has the least optical cost.

Advancements in adiabatic quantum computing have enabled a rapid development in thermodynamically reversible logic circuits, which can reduce energy wastage to almost negligible levels. Various reversible logic gates using silicene-based multiplexer logic devices (SMLDs) are designed and demonstrated herein using Verilog-A, then validated by SPICE circuit simulations. The results confirm that the various reversible gates correctly implement the corresponding truth tables, thereby validating the use of SMLDs as building blocks for such gates. The SMLD-based reversible logic gate designs enable a reduction in hardware complexity by 76.92–80.64% compared with complementary metal–oxide–semiconductor (CMOS) technology and a 50% reduction in hardware compared with pass transistor logic-based designs, respectively.

The objective of this paper is to exemplify the significant improvements achieved in speed and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 VDD digital logic applications. A heterojunction negative-capacitance TFET (NCTFET) has been designed using SILVACO TCAD and its accuracy demonstrated by properly fitting the simulated polarization data with calculated L-K equation solution. The prospects of the proposed structure have been manifested in the steep average subthreshold-slope of 27mV/decade over 9 decades of current and high ION/IOFF of 1016, possible due to the internal voltage amplification and voltage pinning effects. The device has been suitably implemented in inverter, ring-oscillator, 2:1 multiplexer and Full-Adder circuits and benchmarked in delay and power-consumption with a reference TFET (R-TFET) and previously proposed structures. The effect of varying thickness of ferroelectric material on the circuit-level performance has also been discussed. Furthermore, the NCTFET has been implemented in a 6-T SRAM which successfully demonstrates the effect of tFE on noise margin and read-write delay, operated at 0.4 VDD. The proposed NCTFET has been presented and justified as a promising candidate for high-speed and low power digital circuits.

This paper presents a quad-channel 1.25-10.3125 Gbps wireline transceiver implemented in 40 nm CMOS technology. The transmitter consists of a bit width adjustment, a 40:2 multiplexer, a 2:1multiplexer, and a current-mode logic driver with a 3-tap feedforward equalizer. The receiver has a two-stage continuous-time linear equalizer, a 2-tap half-rate fully adaptive decision-feedback equalizer, a phase interpolation-based digital clock and data recovery (CDR) followed by a 2:40 demultiplexer, a bit width adaption. The transceiver also supports AC/DC coupling, CDR locking detection, PLL locking detection, loss of signal detection, automatic termination impedance calibration. A ring VCO-based PLL is designed in each lane to save power consumption, and a dual-core LC VCO-based PLL is implemented in each bank to generate a low jitter clock signal. At 10.3125 Gbps, the transceiver can equalize 28 dB Nyquist loss at a bit error rate of 10−12, and it consumes 114 mW with a 1.1 V supply. This work presents a high power efficiency of 11.05 mW/Gbps, and the transceiver is suitable for multi-standard applications due to its flexibility and power efficiency.