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An investigation of the performance of organic and polymeric thin-film transistors (OTFTs) made of several organic semiconducting and insulating materials in the last two decades is presented, in an attempt to capture the state-of-the-art experimental values for effective mobility, threshold voltage, on/off ratio, and subthreshold slope in OTFTs made of different materials by different fabrication approaches. The analysis of published data demonstrates that the effective mobility decreases when the product of the semiconducting film thickness (tO) and gate capacitance per unit area (CI) increases. The decrease is given by a power-law function with parameters for several organic semiconductors, and examples are provided on how the deduced trend can be used in the practical design of organic circuits. The second observation is that the polarity of the OTFTs’ threshold voltage VT is random, but the spread in magnitudes of ∣VT∣ decreases, when CI increases. This trend, together with the third observation that...

Interest in organic and polymer thin film transistors (OTFTs and PTFTs; hereafter both are called PTFTs) has grown rapidly in the last decade. However, the theory of charge transport in PTFTs lags experiments, so it is difficult to provide the required feedback to device designers and technologists. Therefore, the authors present an analysis of charge transport in PTFTs. It is based on extensive published theoretical and experimental material. The discussion includes examples exploring the trend in experimental results. It is noted that because of the similarity in device structures and current-voltage characteristics between PTFTs and inorganic metal-oxide-semiconductor (MOS) field-effect transistors (FETs), the MOS theory and model have been used extensively in analysing the properties of PTFTs. The MOS model has also been significantly modified to obtain agreement with experiments, and these modifications are discussed. However, recent experimental data from state-of-the-art PTFTs reveal that even the adapted MOS model cannot reliably describe the charge transport in PTFTs, because important PTFT properties such as charge injection or charge build-up result in unrealistic values for several physical parameters (e.g. trap concentrations or time constants) in the adapted MOS model. Therefore, the injection-drift limited model (IDLM) is introduced in this work in an attempt to bring the theory of charge transport and the experimental data closer. The IDLM incorporates the important charge transport phenomena in PTFTs injection, drift and charge build-up. The paper concludes with a discussion of unsolved problems in charge transport in PTFTs.

The behavior of single and double gate accumulation mode silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs) is thoroughly investigated. Accumulation mode devices present advantages over inversion mode transistors regarding transconductance, ease of fabrication, and parasitic effects. We have concluded, from experimental results and 2D simulations, that short channel effects such as DIBL and subthreshold swing degradation are substantially reduced in the volume accumulation regime, being even lower in thin-film double gate accumulation mode SOI MOSFETs than in inversion mode double gate SOI devices for adequate technological characteristics. The potential of thin-film accumulation mode SOI MOS transistors down to sub-0.1 mum technologies and up to 125 degrees C is demonstrated. (C) 2001 The Electrochemical Society.

The authors address the modelling of 1/f noise in SOI MOS devices for circuit simulation. A simple and unified model is presented which is valid for all operating regimes; it is verified by comparison with noise measurements. It is shown that this model is especially useful for low-power SOI MOS circuit design.

The relation between the empirical mobility model parameters used for amorphous thin film transistors and physical device parameters is analyzed, when both localized and free carriers have to be considered to represent the device behavior. A simple procedure is presented to obtain the characteristic temperature and trap concentration of the DOS at the conduction band, using only the linear transfer characteristic at room temperature. An empirical analytical expression that represents analytically the dependence of the surface potential on the gate voltage is presented and validated. Using this expression, the procedure described to calculate the above mentioned parameters is completely analytical. The procedure presented is applied to experimental data of a-IGZO TFTs fabricated with two different technological process.

We report on self-heating, thermal and kink effects in a-Si TFTs. These effects become crucial for gate lengths of 4 microns and shorter. Our data show that self-heating effects in TFTs might reduce the highest operating temperature for AMLC displays by up to 30 to 40/spl deg/C for a 4 /spl mu/m gate device and even more for shorter devices.

We derived an analytical model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) device, the principle of which has been recently demonstrated. Despite some similarities with classical junction-based DG MOSFETs, the charge-potential relationships are quite different and cannot be merely mapped on existing multigate formalisms. This is particularly true for the technological parameters of interest where reported doping densities exceed 10(19) cm(-3) for 10- and 20-nm silicon channel thicknesses. Assessment of the model with numerical simulations confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.

In this paper, we propose to derive an analytical model for the doped symmetric double-gate (DG) MOSFET that is valid in all regions of operation. We show that doping the silicon channel can be converted in an equivalent silicon thickness and threshold voltage shift using a formalism developed for the undoped device. Adopting the same physical parameters, we demonstrate that this approach is in agreement with numerical technology computer-aided design simulations. This concept is therefore an interesting basis for a unified model for doped and undoped symmetric DG MOSFETs.

Amorphous oxide semiconductor thin film transistors (AOSTFTs) with SiO2 and Indium-Gallium-Zinc-Oxides (IGZO) as dielectric and semiconductor layers respectively, are characterized in the temperature range between 300 and 400 K. The behavior of the threshold voltage, mobility factor and saturation coefficient is analyzed as function of temperature. It is shown that, using the Unified Model and Extracted Method (UMEM), the output characteristics of the devices in the linear region can be well modeled at different temperatures. This is done determining the extracted model parameters at 300 K and taking into account the law of variation with temperature for each parameter, corresponding to the specific fabrication technology of the devices. In the saturation region, an abnormal reduction of the drain current is observed. This effect has to be further studied and the representation of its behavior incorporated to the model.

Recently we presented a new expression to model mobility in a-Si:H TFTs model parameters in the subthreshold region and the procedure for the extraction of basic model parameters in this region. The main characteristics of extraction procedure is the use of the Integral Function Method (IFM), that permits to extract in a simple and direct way basic model parameters from experimental transfer and output characteristics. In this work we report results of comparing simulated in AIMSpice a-Si:H TFTs after including the new subthreshold model, with experimental curves. The model and extraction procedure has been tested for a-Si:H TFTs with channel length down to 4 /spl mu/m, observing good coincidence between simulated, using parameter values obtained with our new extraction procedure and experimental curves, in all working regions of the devices.

A new MOSFET parameter extraction tool is presented. This tool uses digital signal processing techniques to increase the signal/noise ratio within well-known extraction methods based on determining maxima of derivatives. This signal processing is related with calculations based on Fourier transform and filtering procedures to smooth data. The procedure is applied to extract three different parameters, and results are compared with other methods using experimental data.

In this paper, we describe the small signal and noise properties of SOI MOSFETs. A first order discussion is carried out to discuss the parameters that strongly influence the cut-off frequencies (f/sub t/, f/sub max/) and the related noise performance in up-to-date SOI MOSFETs. Then a high frequency noise modeling is used to discuss the bias dependence of the gate and drain noise current and related key noise parameters as well as their upcoming variations along the gate length down-scaling. The capability of the noise modeling is then highlighted through comparisons with experimental data, and the influence of the parasitic capacitances (overlap, fringing) is discussed. Finally, special emphasis is made towards the influence of a direct tunneling current on the noise performance of SOI MOSFETs.

We describe direct extraction techniques for the most important parameters of a new physics-based polysilicon (poly-Si) TFT model, suitable for circuit simulation. The physics-based model covers all operating regimes using continuous functions, includes short-channel effects and has been validated for devices of channel lengths down to 2 /spl mu/m. In spite of a small parameter set, the model includes the necessary dependencies on channel length.

In this paper, the RF noise properties of fully depleted (FD) SOI MOSFETs in the presence of a tunneling gate current (TGC) are described using a physical compact noise modeling. A complete noise model is first proposed to account for the presence of TGC. Its influence on the RF noise performance of FD SOI performance is then presented and it is shown that both the minimum noise figure and the optimum noise match conditions are affected in the sub-10 GHz frequency range, for TGC densities higher than 5 A/cm/sup 2/.

The models presented so far for accumulation-mode (AM) SOI MOSFETs are not very appropriate for mixed analog-digital circuit simulation, since they use different equations with abrupt transitions between the different regimes and they do not consider the short-channel effects nor charge conservation. In this paper we present an explicit model for the drain current and intrinsic capacitances of AM SOI pMOSFET model, based on physical principles and on approximate unified expressions of the mobile charge densities. The model shows good agreement with short-channel device measurements. Our AM model may be combined with our unified FD SOI MOSFET model in order to reliably simulate SOI CMOS circuits, in particular for low-voltage low-power analog applications.

For compact modeling of the organic field-effect transistor above-threshold drain current, we suggest using an approach that was recently proposed for the improved compact MOSFET model with the correct accounting of the nonzero output conductance in the saturation regime. This approach ensures a monotonic decrease of transistor output conductance from its maximum value in the linear regime to the minimum value in the saturation regime.