301. Addressing FinFET metrology challenges in 1× node using tilt-beam critical dimension scanning electron microscope.
- Author
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Xiaoxiao Zhang, Hua Zhou, Zhenhua Ge, Vaid, Alok, Konduparthi, Deepasree, Osorio, Carmen, Ventola, Stefano, Meir, Roi, Shoval, Ori, Kris, Roman, Adan, Ofer, and Bar-Zvi, Maayan
- Subjects
METROLOGY ,SCANNING electron microscopes ,ELECTRON beams ,ENGINEERING ,FEASIBILITY studies - Abstract
At 1 × node, a three-dimensional (3-D) FinFET process raises a number o f new metrology challenges for process control, including gate height and fin height. At present, there is a metrology gap in inline in-die measurement of these parameters. To fill this metrology gap, in-column beam tilt has been implemented on Applied Materials V 4 i+ critical dimension scanning electron microscope for height measurement. Low-tilt (5 deg) and high-tilt (14 deg) beam angles have been calibrated to obtain the height and the sidewall angle information. Evaluation of its feasibility and production worthiness is done with applications in both gate height and fin height measurements. Transmission electron microscope correlation with an R
2 equal to 0.89 and a precision of 0.81 nm have been achieved on various in-die features in a gate height application. The initial fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to greater challenges brought by the fin profile, yet it is promising for the first attempt. Sensitivity to design of e×periment offset die-todie and in-die variations is demonstrated in both gate height and fin height. The process defect is successfully captured with inline gate height measurement. This is the first successful demonstration of inline in-die gate height measurement for a 14-nm FinFET process control. [ABSTRACT FROM AUTHOR]- Published
- 2014
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