Search

Theoretical and experimental studies of amorphous-silicon field-effect-devices developed in Tokyo Institute of Technology are reviewed in this paper. Mobility as high as 1.9 cm2/Vsec, which is about an order of magnitude higher than the one reported to data, was observed. The first amorphous-silicon logic circuits, image sensors and charge coupled devices are presented. Problems which must be overcome, are described.

Field dependence of field-effect mobility in hydrogenated amorphous-silicon has been investigated using a novel 4-terminal transistor structure. The mobility evaluated from the transistor characteristics did not depend on electric field strength up to 20 kV/cm.

This letter proposes a novel amorphous-silicon field-effect transistor whose local threshold voltage is distributed along the channel. A low off-current is the most important feature of the new device, while the on-current is as high as that of the conventional device. The superior off-characteristics of the novel device were verified experimentally.

Process conditions for gate oxide formation in amorphous-silicon MOS transistors have been investigated systematically. It was found that the n+ micro-crystal silicon layer just above the active transistor region should be removed before the gate oxidation at 250°C. Annealings in nitrogen ambient just after the oxidation and in hydrogen ambient after gate electrode evaporation were also effective. The highest field-effect mobility measured by the transistor fabricated under the optimum process conditions was about 4.8 cm2/Vs. Dynamic response characteristics have also been evaluated.

A fine metal line with T-shaped cross-sectional form was fabricated by a lift-off technique using the double-layer electron beam resist method. The minimum lower and upper widths of the T-shaped cross-section were 0.2 μm and 0.7 μm, respectively, and, keeping the lower width within 0.3 μm, we could increase the upper width at will.

A native silicon-oxide layer has been thermally grown at 250°C by using a nitric and sulfuric acid mixture in a liquid phase under high-pressure conditions. It was found that the grown oxide layer was mainly of silicon-dioxide; however, the density of intermediate oxide was higher than that in a conventional and a thermally-grown oxide layer. The resistivity and the breakdown field strength of the oxide layer were more than 1014 Ω·cm and 4 MV/cm, respectively. The interface state density, evaluated from high-frequency C-V characteristics, showed a V-shaped distribution and its minimum value was about 1011/cm2eV.

A new low-temperature method of thermal-oxidation for amorphous-silicon has been proposed, and preliminary experimental results on its application to amorphous-silicon MOS transistors are presented. The resistivity of the oxide was over 1014 Ωcm and the field-effect mobility deduced from the saturation region of the transistor characteristics was 0.003 cm2/Vs.

The problem of low drift mobility of holes in hydrogenated amorphous silicon (a-Si:H) has been solved by controlling the hydrogen content in the film. A-Si:H films with low hydrogen content have been prepared by the radical-controlled method in which the glow discharge of the mixture of SiF4 and H2 is used and the residence time of the reactant species is controlled. A prototype MOSFET demonstrates a hole mobility of 0.12 cm2/Vs and an electron mobility of 0.24 cm2/Vs, suggesting the feasibility of the a-Si CMOS circuit.

Fully self-aligned amorphous-silicon MOS transistors have been proposed and fabricated for the first time. All positions, i.e., an active region, source and drain region, contact holes and metal electrodes are determined by only one photo-mask for the top silicon-nitride layer of a multi-layer structure deposited successively on a glass substrate. The total number of photolithographic steps is 6. On-off current ratio and the maximum field-effect mobility of the fabricated transistor are 105 and 0.25 cm2/Vs, respectively.

Large-signal oscillation dynamics of silicon p-i-n avalanche diode was computed. A large-signal conductance takes a negative value only near the Read frequency. Near this frequency, the p-i interface is equivalent to the avalanche region of the Read diode and the i-region except near the p-i interface is equivalent to the drift region of the Read diode. Segregation of such two regions as the Read diode is due to a difference of saturated velocity as well as of the ionization coefficient between electrons and holes. The oscillation dynamics under high dc current density condition is almost identical to that of the same oscillation frequency under low dc current condition.

This paper presents the results of numerical and analytical calculation of large signal properties of Read diodes. The results indicate that (i) threshold current density is proportional to the square of the oscillation frequency and that (ii) dc current density that causes microwave power saturation is proportional to oscillation frequency. It is elucidated that the optimum values of dc current density and ac voltage are determined mainly by the field distribution in the drift region. The optimum field profile of Read diode differs from the profile proposed by Read and resembles the profile of p-n-n + diode.

Computer simulations of silicon Read and p-n-n + diodes under large signal conditions reveal that the p-n-n + diode oscillates with a pulsed electron current as the Read diode and the field gradient in an active region of the both diodes is an important factor for high output power.