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The International Technology Roadmap for Semiconductors (ITRS) [1] identifies a number of potentially enabling device and materials technologies to extend and compliment CMOS. These emerging memory and logic devices employ alternate “states” including 1D charge state, molecular state, polarization, material phase, and spin. The improvement of these materials and devices depends on utilizing existing and new metrology methods to characterize their structure, composition and emerging critical properties at the nanometer scale. The metrology required to characterize nanomaterials, interfaces, and device structures will include existing structural metrology, such as TEM, SEM, and others, as well as metrology to characterize new “state” properties of the materials. The characterization of properties and correlations to nanostructure and composition are critical for these new devices and materials. Characterizing the properties of emerging logic technologies will be very difficult, as an applied stimulus is req...

Currently, the work‐functions of metal gates are determined using capacitance‐versus‐gate‐voltage measurements of a dedicated MOS capacitor structure. Alternatively, Kelvin Force Microscopy (KFM) is a promising technique which allows the work‐function to be measured with high spatial resolution (

Super‐resolution in optical microscopy has been pursued historically through different methods, e.g., dark‐field, phase contrast, and oblique illumination, etc. For each type of microscopy, the ultimate resolution available is dependent upon the amount of a priori knowledge the observer has about the object. The metrology of photolithographically patterned structures on silicon wafers is aided by a foreknowledge of the target design. By manipulating the angular degrees of freedom of the illumination solid angle, our resolution for these patterned wafers is enhanced through what we have termed scatterfield microscopy. Examples of using oblique illumination to control the illumination angle are provided as we image the zero‐order and first‐order diffraction from sub‐resolved overlay targets. Lines with critical dimensions as narrow as λ/8 are resolved using this technique.

Many potential thin‐film multilayer structures, which could otherwise have useful properties for nanoelectronic applications, may fail due to deleterious reactions at hetero‐interfaces that destroy or alter the intended performance. For simpler materials, thermodynamic calculations may provide valuable insights. However, for many new combinations of complex materials, the data set required for stability prediction is incomplete. Kinetic factors, very difficult to predict, also affect the suitability of a given materials combination for a particular application. Consequently, there is a need for direct experimental evaluation of interfacial stability for candidate materials in a number of technologically important systems, including the advanced CMOS (complementary metal‐oxide‐semiconductor) gate stack. In this paper, we describe the application of sensitive thin‐film, MEMS (micro‐electro‐mechanical systems)—type DSCs (differential scanning calorimeters) to investigate the thermal signatures produced by interfacial reactions, using Ni/Si as an example.

Small Signal Surface Photo Voltage (SPV) measurement has become a widely accepted metrology for measuring resistivity of epitaxial and Czochralski wafers. For this metrology technique there are currently no Standard Reference Matertials (SRMs®) as defined by the National Institute of Standards and Technology (NIST). This paper will present a method for creating a NIST traceable standard for SPV measurement by further processing NIST 100 mm diameter silicon resistivity, SRM 2543 wafers.

A 50 μm metal probe has been combined with pattern recognition optics and a 3‐directional precision stage for automated CV and IV testing of dielectric layers in scribe‐line test structures on IC product wafers. Highly repeatable contact conditions are obtained though the use of a MEMS‐based torsion balance spring mounting which provides capacitance measurements within 0.1% for repeated landings of the probe. High repeatability capacitance measurements provide for correspondingly high quality determination of dielectric characteristics, EOT, Vfb, Dit, Na and Qeff, from CV analysis. Dielectric leakage and breakdown characteristics, including Vbd, Qbd and TTBD, can be obtained for positive and negative ramped bias conditions. Measurement of capacitor structures provides CET and electrode work function values which can be followed throughout the process history of the wafer and directly compared to final test results. Examples of measured dielectrics include thin (∼1 nm) SiO2, Al‐oxides, nitrided Si‐oxides a...

High resolution X‐ray diffraction (HRXRD) measurements were performed using a commercially‐available X‐ray metrology tool, the BedeMetrix™‐L, on small test pads containing arrays of SiGe line structures selectively deposited in Si recesses with various window dimensions. Reciprocal space maps (RSMs) were performed in two orthogonal 〈110〉 directions in order to determine the lattice parameter parallel and perpendicular to the lines. With narrow lines, asymmetric relaxation effects were seen: the SiGe was fully strained along the long dimension of the lines while there was significant relaxation along the short dimension of the lines. The magnitude of the relaxation increased significantly for lines with short dimension below about 1 μm. We show how to determine the lattice parameters, and hence the strain of the SiGe in the [110] and [−110] directions, the Ge composition and the relaxation initially using RSMs, but with an extension to measurements more suitable for in‐fab metrology.

As the CMOS gate stack continues to scale to smaller dimensions, new materials must be introduced into the stack to keep pace with design requirements. One way to measure the properties of new materials systems is through the use of high‐throughput experimentation, called combinatorial methodology. We describe two examples of combinatorial experimental design for CMOS. In the first, we will demonstrate library design and growth of Al‐Hf‐Y‐O films for high‐k applications. In the second, we will demonstrate Ni‐Ti‐Pt metal gate libraries for Si/Hf02/metal gate electrode applications.

Straining the active regions in MOSFET devices is one of the key contributors to increase device performance in present and future technology nodes. Since dedicated strain on the transistor level is required with opposite sign for NMOS and PMOS transistors, the need to measure strain locally has become a challenge for analytics and metrology. Raman spectroscopy is capable of obtaining strain information non‐destructively on the sub‐μm scale, and therefore, this technique has been considered for process monitoring. In this paper it will be shown for silicon‐germanium thin films, how both strain and composition can be determined independently by measuring two phonon modes of the film. This technique enables fast measurement of mechanical strain and chemical composition with high accuracy on the μm‐scale. Thus, the micro‐Raman technique is well suited for metrology of strained silicon test structures. Furthermore, it is shown that mechanical strain close to silicon‐germanium structures can be measured with near‐field resolution utilizing tip‐enhanced Raman scattering (TERS). For device characterization, first steps of Raman‐based approaches towards nano‐Raman strain measurement in transistor channels have been done. However further development of this technique for improved deep submicron spatial resolution and for metrology applications is required.

Recent progress in developing algorithms for solving the electronic structure problem for nanostructures is illustrated. Key ingredients in this approach include pseudopotentials implemented on a real space grid and the use of density functional theory. This procedure allows one to predict electronic properties for many materials across the nano‐regime, i.e., from atoms to nanocrystals of sufficient size to replicate bulk properties. We will illustrate this method for doping silicon nanocrystals with phosphorous.

The nanoelectronic industry is facing a major change. It induces significant evolutions in the way R&D is conducted worldwide. Europe developed specific models of cooperation. Among them CEA‐LETI promotes the collaborative proximity with manufacturing sites and academia in the Grenoble area (France). This paper will detail this evolution of the nanoelectronic industry, how it induces renewed R&D models and how it affects the nanocharacaterization needs and methods.

Thin film characterization methods are pushing the development of new applications beyond the standard measurements of thickness and composition and towards a complete understanding of the physical, optical, and electrical properties at the atomic scale. One of many important aspects is characterizing the electrical quality of the gate dielectric film with respect to charge trapping and leakage currents. This has conventionally been done with post‐processing electrical measurements, which deliver results that may be complicated by subsequent process steps and thermal treatments. A need to non‐invasively probe the film early in processing, as well as an economic drive to extend the capabilities of existing in‐line platforms, has led us to explore using optical methods for characterizing charge trap centers in dielectric films. In this work, we explore the capability of using spectroscopic ellipsometry as a method of identifying charge trapping states in the Si/SiO2/high‐κ gate stack system. We briefly revi...

Photoelectron‐Emission Microscopy (PEEM) is the most promising approach to photoemission‐based (XPS, UPS) imaging techniques with high lateral resolution, typically below 100 nm. It has now reached its maturity with a new generation of instruments with energy‐filtering capabilities. Therefore UPS and XPS imaging with energy‐filtered PEEM (EF‐PEEM) can be applied to technologically‐relevant samples. UPS images with contrast in local work function, obtained with laboratory UV sources, are obtained in ultra‐high vacuum environment with lateral resolutions better than 50 nm and sensitivies of 20 meV. XPS images with elemental and bonding state contrast can show up lateral resolution better than 200 nm with synchrotron excitation. In this paper, we present the principles and capabilities of EF‐PEEM and nanospectroscopy. Then, we focus on an example of application to non‐destructive work‐function imaging of polycrystalline copper for advanced interconnects, where it is shown that EF‐PEEM is an alternative to Kelvin probes.

Research in nanoelectronics poses new challenges for metrology, but advances in theory, simulation and computing and networking technology provide new opportunities to couple simulation and metrology. This paper begins with a brief overview of current work in computational nanoelectronics. Three examples of how computation can assist metrology will then be discussed. The paper concludes with a discussion of how cyberinfrastructure can help connect computing and metrology using the nanoHUB (www.nanoHUB.org) as a specific example.

Real‐time, high resolution wafer mapping of critical medium current ion implants can reveal “device killing” problems well before parametric binning at electrical test. Device fails associated with electrical testing at the “End Of Line” have been correlated to mechanical scan problems that can be monitored with a spatially significant Dynamic Surface Charge, wafer metrology technique. High‐resolution mapping allows implant “Micro‐Uniformity” to be evaluated in real time, enabling metrology of device‐critical implant parameters before “End Of Line” electrical testing.

Vacuum ultraviolet (VUV) reflectometry data are presented for two material systems. The unique absorptive properties of materials in the VUV wavelength regime make it possible to simultaneously measure ultra thin film thickness and compositional aspects of the low temperature CVD SiO2:N and ALD hafnium titanate films considered here.

We investigated so‐called cross polarization (or polarization conversion) effects to extend the capabilities of conventional spectral‐ellipsometry based scatterometry. Therefore, we developed a procedure how to adapt an automated rotating polarizer ellipsometer in order to determine the ratio between diagonal and off‐diagonal elements of the Jones matrices for suitable samples. This so called generalized ellipsometry leads to six spectra instead of two, which contain more extractable information about the geometry of the sample under investigation, i.e. the diffraction grating. We created spectral libraries by using the rigorous coupled wave analysis (RCWA) method, which contain elements of the Jones matrix for different grating geometries. These libraries allow an analysis of measured spectra, as well as sensitivity studies and optimization for different analyzer angles and grating orientations with respect to the plane of the incoming light beam (conical diffraction). Due to sidewall effects which might cause polarization conversion, we demonstrate the advantage when employing conical diffraction, especially for measurements of asymmetric and 2D periodic structures.

Amorphous Carbon films deposited by PECVD (RF) have recently been introduced as a new material for semiconductor processing, e.g. in 193 nm ARC lithography [1] and in the DRAM production [2]. A large amount of literature has already been published on with regard to the applications of this class of material [3]. Hence, it has been reported that Amorphous Carbon films undergo a hydrogen chemical desorption when deposited above 500 °C, together with an amorphous to graphite phase transition. Unfortunately, the intrinsic nature of the amorphous carbons depends strongly upon deposition techniques. Film morphology can be completely different from one case to another since there are so many deposition techniques. Optical characterization of these films has also undergone development for several decades. In Spectroscopic Ellipsometry (SE), several models have been proposed from simple Lorentz oscillators' absorption, toward the Tauc Lorentz or Forhoui Bloomer equations. Nevertheless, none of these models suffici...

Chemical mechanical planarization (CMP) is a critical process for creating high performance interconnected structures. If line structures are under polished, residual copper or barrier will short out the circuitry resulting in defective dies. However, over polishing increases the line resistance, negatively impacting both the speed and performance of devices. To maintain high yield, it is thus critical to maintain the copper lines at the desired thickness. This requires strict process control. Several metrology techniques are used to monitor CMP processes including optical techniques that measure dielectric polishing and high resolution profilometry (HRP™) that can measure the relative step height differences between structures such as interlayer dielectric pads, copper pads, and line arrays. In contrast, the picosecond ultrasonic laser sonar method (PULSE™) measures the copper thickness and therefore directly measures the parameter of interest for CMP process monitoring. The picosecond ultrasonic technique is well established for measuring on solid copper structures such as pads. However, in the dense narrow line arrays that are required for current and next generation devices, the measurement spot size, while only approximately 10 μm in diameter, may cover hundreds of copper line/dielectric pairs. Therefore a new detector was developed that is insensitive to the dielectric signal. The capabilities of picosecond ultrasonic laser method to measure both copper pads and 0.6 μm line arrays were recently tested at STMicroelectronics (STM). The results were compared against Scanning Electron Microscopy (SEM). The samples included different products and six different metal layers. This paper will further describe the picosecond ultrasonic method, its use at STM, and detailed results for the various samples.

We use synchrotron x‐ray reflectometry and Bragg diffraction to study silicon loss in the low temperature plasma oxidation of silicon‐on‐insulator (SOI) wafers. We show that Laue oscillations associated with the Si (004) Bragg peak give the number of Si (004) planes in the device layer to within an experimental error of 0.07 nm and that X‐ray reflectometry gives the total thickness of the device layer and the surface oxide to within 0.05 nm. We find that silicon loss in samples processed in two different plasma systems correspond to an increase in total thickness that is consistent with the formation of SiO2.

As porous SiOCH is a widely used inter‐metal dielectric for 65 nm nodes and below, the control of its elaboration process by in‐line monitoring is necessary to guarantee successful integration of the material. In this paper, the sensitivities of several non‐destructive metrology techniques towards the film elaboration process drifts are investigated. It appears that the two steps of the process should be monitored separately and that corona charge method is the most sensitive technique of the review for this application.

Complementary Metal Oxide Semiconductor (CMOS) down‐scaling leads to a dramatic reduction of the gate dielectric thickness for the isolation efficiency. The properties of hafnium aluminium oxide (HfAlO) are investigated as an alternative to conventional SiO2 as it exhibits the desirable characteristics of a high dielectric constant, a wide bandgap and good thermal stability with silicon. In this study, we show that complementary characterization techniques can be used to tune the deposition parameters to get optimized high‐κ dielectrics since the advanced capabilities of the characterization protocols and configurations allow analysis of few nanometer thick layers.

Due to shrinking size of lithographic feature and limitations of SEM process, the native accuracy of CD‐SEM instrument falls outside of ITRS requirements for characterization of lithographic structures for technology node 45 nm and smaller. This work provides overview and feasibility study of metrology system that can deliver accurate CD measurements from CD‐SEM by using combination of image metrology and SEM beam modeling methods for automated evaluation and correction of CD‐SEM bias. Open issues and further metrology needs are also discussed.

The direct depth measurement of structures with aspect ratios between 1 and 4 in the arrays of memory cells represents a major challenge for inline metrology. For 75 nm and larger technology nodes these measurements are carried out using inline AFM using 50±5 nm diameter cylindrical AFM probes. However, for 58 nm and smaller technology nodes these AFM probes are not capable anymore, because the tip diameter is comparable to the diameter of the trench structures themselves. Here we report about the development of 30 nm diameter cylindrical AFM probes suitable for direct depth measurements of 58 nm ground rule (GR) structures. The focus of the development was on tip lifetime, gage capability and throughput in a high volume environment. For the tests two different tip materials—silicon (Si) and electron beam deposited (EBD) carbon were investigated. Both tip types proved to be fully gage capable, and showed no throughput losses in comparison to larger node measurements. The tip lifetime under production cond...

The feasibility of using piezoelectric drop‐on‐demand inkjet printing technology to produce trace metal contamination standards on silicon wafers has been demonstrated. Prototype standards of Fe and Cu contamination with surface concentrations between 1013 atoms/cm2 and 1015 atoms/cm2 have been produced using a piezoelectric inkjet printer. Preliminary secondary ion mass spectrometry (SIMS) measurements show that secondary ion intensities are linear with respect to concentration. The success of these preliminary experiments has prompted further work that is currently underway to prepare additional elements at concentrations ranging from 107 atoms/cm2 to 1015 atoms/cm2 for characterization by both SIMS and total reflection x‐ray fluorescence (TXRF).

A new microscope has been developed that uses a beam of helium ions which is focused and scanned across the sample. In principle, and in its applications, it is similar to a traditional scanning electron microscope (SEM). However, the source technology, the sample interaction, and the contrast mechanisms are distinctly different. The helium ion source offers high brightness (4×109 A/cm2sr) and a small energy spread (ΔE/E∼3×10−5), and hence allows the beam to be focused to small probe sizes (as small as 0.25 nm). As the beam interacts with the sample, the beam penetrates relatively deeply before it diverges and hence there is a narrow sample interaction region near the surface. The helium beam generates secondary electrons, scattered helium atoms (ions and neutrals), and other detectable particles from which images can be generated or analysis can be performed.

In‐plane geometrical defects on wafer surfaces following Chemical Mechanical Planarization (CMP) processing in the lateral millimeter range and in vertical dimensions in the nanometer range are of increasing importance. They will become a severe yield limiting factor in the 32 nm generations and below. At the wafer edge these defects are known as edge roll off (ERO). The feasibility of measuring flatness and geometry of bare silicon wafers and patterned wafers from different process steps as e.g. shallow trench isolation (STI) and interconnect metallization was successfully demonstrated using wave front sensing. The used wave front sensing methods were according to Makyoh and Shack Hartmann. The specifications achieved were for the Makyoh method a lateral resolution of 2.4 mm and for Shack Hartmann method 1.1 mm. The vertical resolution was 100 nm for the Makyoh method and 50 nm for the Shack Hartmann method.

Three dimensional microstructures find applications in diffractive optical elements, photonic elements, etc. and can be efficiently fabricated by grayscale lithography. Good process control is important for achieving the desired structures. Metrology methods for grayscale lithography are discussed. Process optimization for grayscale e‐beam lithography is explored and various process parameters that affect the grayscale process are discussed.

Energy dispersive x‐ray fluorescence is a powerful technique for measurement of film thickness as well as compositions. As chip packaging is becoming part of typical Fab process, additional multilayer stack films are used for re‐distribution of bumps and under bump metallization. These re‐distribution and under‐bump film stacks are characterized using XRF. In addition, composition of lead‐free Ag/Sn bump is also measured using small spot x‐ray fluorescence.

Ni-silicides formed by a variety of processing techniques were studied with secondary ion mass spectroscopy (SIMS) and local electrode atom probe (LEAP registered ) analysis. SIMS provided 1-D chemical analysis over an approximately 60 micron diameter area. LEAP provided 3-D atom identities and locations over an approximately 100-150 nm diameter area. It was determined that the 200 deg. C drive-in anneal results in a Ni{sub 3}Si{sub 2} phase, which is converted to NiSi at temperatures between 360 deg. C-400 deg. C. LEAP detects no As or Pt segregation after the 200 deg. C drive-in anneal, but did quantify As segregation of up to 7% of the material composition just inside the NiSi-Si interface after the phase-formation anneal. The presence of oxygen at the interface results in a silicide chemical surface roughness of up to 3.5 nm as compared to 0.5 nm with a clean, non-oxidized surface. Silicide stability was demonstrated over the phase-formation-temperature range of 360 deg. C - 400 deg. C including when a second rapid thermal anneal step was used. LEAP analysis was also able to quantify the surface roughness of the interface as a function of anneal temperature and the non-uniform Pt and As distribution across themore » silicide surface as viewed in 2-D surface projection.« less

For further miniaturization and performance enhancement of CMOS transistors, new materials and structures are now being introduced. The implementation of these new technologies while minimizing unwanted variations requires tremendous challenges in metrology and characterization techniques. This article deals with measurement techniques for the three major causes of random variation of device performance, i.e., line width and line edge roughness measurement, dopant profiling and mechanical stress monitoring. It is emphasized that the scanning probe microscopy is an indispensable technique for further extension of Si CMOS because of its ability to measure various quantities with nanometer spatial resolution. Examples are the atomic force microscopy for metrology of critical dimensions and three dimensional features, UV Raman spectroscopy with scanning near‐field optics for stress monitoring, and scanning tunneling microscopy for potential and dopant profiling.

Sheet resistance and leakage current of spike rapid thermal processed (RTP), millisecond flash (fRTP) annealed and chemical vapor deposition (CVD) grown ultra‐shallow junctions (USJ) are compared with a non‐contact junction photovoltage, RsL, technique. Theoretical reverse‐biased diode and non‐contact leakage currents are compared. A significant leakage current increase for spike RTP and fRTP processed USJ formed in halo‐implanted profiles is described by high electron and hole recombination‐generation in the end‐of‐range (EOR) damage layer enhanced by trap assisted and band‐to‐band tunneling. The reduced thermal budget of fRTP allows junction formation with reduced dopant diffusion and with lower sheet resistance. However when strong halo doping is employed, there is often a significant increase in junction leakage relative to that for junctions formed in lightly‐doped test wafers. This increased leakage current can be reduced by annealing the halo implants before implanting the USJ or by lowering the halo dose. USJ grown with CVD demonstrate low leakage current due to localization of recombination centers at the edge of the depletion layer, where recombination (generation) is small. This study demonstrates the importance of characterizing USJ formed in halo profile for advanced ULSI.

We report metrology methods to characterize nanowires. In this work, representative devices and test structures, including nanoelectromechanical switches, non‐volatile nanowire memory devices with SONOS structure, and both transfer‐length‐method and Kelvin test structures, have been developed to investigate the electrical and mechanical properties of the silicon nanowires. These methods and test structures can be readily applied to other (non‐Si) semiconductor nanowires/nanotubes.

In this paper we demonstrate an application of the micro corona‐Kelvin metrology to monitoring of the electrical properties of silicon oxynitrides prepared with a plasma nitridation process currently used for advanced gate dielectrics. Key measurement parameters to be discussed are: dielectric capacitance equivalent thickness (CET), dielectric voltage in valence band tunneling range (VB), interface trapped charge (Qit) and flatband voltage. Negative polarity tunneling conditions are used as a measure of dielectric valence band. Taking advantage of the large valence band offset difference between Si3N4 and SiO2, we employ these tunneling measurements for very sensitive probing of the nitrogen content in SiON dielectrics.

We have demonstrated that scanning nano‐Raman spectroscopy (SNRS), also known as tip enhanced Raman spectroscopy (TERS), with side illumination optics can be effectively used for analysis of silicon‐based structures at the nanoscale. Despite the disadvantages of side illumination optics, such as difficulties in optical alignment and shadowing by the tip, it has the critical advantage that it may be used for the analysis of non‐transparent samples. A key criterion for making SNRS effective for imaging Si samples is the optimization of the contrast between near‐field and far‐field (background) Raman signals, which improves by an order of magnitude by optimizing the incident and scattering polarization scheme. The resulting nano‐Raman images of semiconducting structures yield a spatial resolution ∼20 nm.

Two complementary methods are described for measuring the fracture strength and toughness of components and materials at the nano scale. The first makes use of a test specimen formed into a theta‐like geometry that is loaded vertically in compression, subjecting an incorporated horizontal ligament to uniaxial tension, thereby permitting component tensile strengths to be measured. Demonstrations are shown for Si specimens with 10 μm‐scale ligaments. The second makes use of instrumented indentation testing, “nanoindentation,” methods in which an acute, cube‐corner probe is loaded onto a surface generating cracks that permit material toughness to be measured. Demonstrations are shown for a series of low dielectric constant film at sub‐μm length scales.

A new FEOL metrology technique based on the use of elastic material probes (EM‐Probes) is demonstrated for gate dielectric process development and monitoring for the 45 nm technology node and beyond. It is shown that critical gate dielectric electrical parameters such as Equivalent Oxide Thickness (EOT), Gate Leakage Current Density (JLEAK), and Stress Induced Leakage Current (SILC) can be accurately measured in a non‐damaging, non‐contaminating fashion on product wafers. Correlations to final device parameters are discussed which are better than any other method available.

Laser scattering on unpatterned wafers is a common technique, mainly used in semiconductor fabs for optical wafer inspection (i.e. defectivity). Previously, the low frequency part of the scattered light (called “haze”) was viewed mainly as a noise source that limits the particle detection sensitivity. However, the haze signal of KLA Tencor SP1 and SP2 tools contains enough information to improve in‐line surface characterization and to give, in less than one minute for a full‐wafer mapping, very encouraging results when running large metal contamination studies or when developing and monitoring, for example, SGOI, GeOI and silicides processes.

Infrared spectroscopy is a characterization technique that is widely used to observe molecular vibration signatures. Using a particular optical configuration such as multiple internal reflections (MIR) or attenuated total reflection (ATR) it is possible to enhance the signal from ultra thin layers or from low concentration contaminants. Reasons of the enhancement of the sensitivity, thanks to these optical configurations, are explained. Advantages of these techniques are highlighted by showing a wide range of applications in which they are used. We present here, the results obtained using these configurations in several fields of microelectronics or nanotechnology: i) the silanization of silicon surfaces are being developed for biological applications; a study of the grafting efficiency and verification of different processes which modify the terminal functional groups are shown; ii) the characterization of high κ materials designed to replace silicon gate oxides 32 nm technology node; results obtained fr...

When metal electrodes are deposited on a high-{kappa} metal-oxide/SiO{sub 2}/Si stack, chemical interactions may occur both at the metal/high-{kappa} and the high-{kappa}/Si interfaces, causing changes in electrical performance. We report here results from medium energy ion scattering (MEIS) and x-ray photoelectron (XPS) studies of oxygen and silicon transport and interfacial layer reactions in multilayer gate stacks. Our results show that Ti deposition on HfO{sub 2}/SiO{sub 2}/Si stacks causes reduction of the SiO{sub 2} interfacial layer and (to a lesser extent) the HfO{sub 2} layer. Silicon atoms initially present in the interfacial SiO{sub 2} layer incorporate into the bottom of the high-{kappa} layer. Some evidence for titanium-silicon interdiffusion through the high-{kappa} film in the presence of a titanium gate in crystalline HfO{sub 2} films is also reported.

The emergence of ultra‐sharp carbon nanotube (CNT) tips provides a new approach to minimize the distortion of the measured linewidth profile caused by interaction with the finite probe tip size. However, the inevitable tilt angle resulting from attaching the nanotube to an ordinary probe causes a significant probe‐related distortion on one sidewall of the linewidth sample. In order to obtain accurate images at both sidewalls, the sample is measured twice. After the first measurement which provides an accurate image on one sidewall, the sample is rotated 180° to measure the other sidewall. The two images are stitched together as a composite image in which both sidewall images are minimally distorted. To accurately stitch the two images, their position difference caused by the 180° rotation must be eliminated. In this paper, the template matching method is adopted after the primary image processing that includes surface leveling and rotation. At the optimum matching position, these two images are stitched as a composite image, in which the average linewidth and the standard deviation are calculated.

Naysayers have been claiming for some time now that the dramatic progress of microelectronics in accordance with Moore's law is about to come to a crashing halt. We give examples from novel semiconductor memory and logic devices that indicate that the future is likely to be even more exciting. Conventional Si CMOS may be enhanced by spintronics and quantum interference devices. We will point out metrology needs and opportunities in some of these areas.

Spatial variation of local work function (LWF), which represents the surface potential, was examined for p‐n junctions on a Si(111) substrate and for (110) cross sectional surfaces of boron‐doped p‐p+ multi‐layers (1E17–5E19/cm3) grown on a (001) substrate. The LWF maps obtained by the vacuum‐gap modulation scanning tunneling spectroscopy (VGM‐STS) on oxygen‐passivated atomically flat (111) terraces reveal the variation in carrier density across a p‐n junction. Density of local fluctuations in LWF maps (i) decreases with increase of the bias voltage, and (ii) correlates well with the boron doping concentration, verifying their origin in local electrostatic fields around negative point charge centers and in particular, boron acceptors beneath the surface. The results demonstrate the ability of VGM‐STS to measure both the surface potential and distribution of charge centers with a sub‐nanometer resolution on oxidized Si surfaces.

Due to the new challenges accompanying every new shrink node in semiconductor industry new materials have to be implemented or device design has to be adapted—both to realize the intended device that still obeys physical laws. Visualization of these problems is a task of metrologists facing themselves physical borders. Monitoring stress becomes a major challenge arising from new processes applied as well as from worse surface to bulk volume‐ratio or intended implied stress in new concepts of devices. High k‐materials might induce macroscopic stress, which can be monitored on the wafer scale in wafer bow experiments. This unintended stress is even higher in patterned areas but not known in a micrometer scale. The knowledge of microscopic stress—or even nanoscopic stress—is even more important on intended stress implemented in devices and thus target of interest. This paper offers two ways of monitoring sub‐micrometer stress. One is the well established scanning Micro‐Raman technique. The second is a relatively new method called Tip‐Enhanced‐Raman‐Spectroscopy (TERS). Both methods have their advantages but also challenges. The results of the easy to use scanning Micro‐Raman technique need to be interpreted and information needs to be unfolded. Whereas the challenge of Tip‐Enhanced‐Raman‐Spectroscopy lies in the experimental skills: handling a scanning‐probe‐microscope‐tip in a Micro‐Raman beam with the perspective of having a resolution restricted only by the SPM‐diameter or even smaller.

This paper describes a series of electrical measurements and sample modifications that enabled the electrical properties of hybrid‐orientation direct silicon bonded wafer interfaces to be determined. It is shown that the carrier transport across this near‐surface (110)/(100) boundary is dictated by the defects present at the bond interface. These interface states are believed to pin the Fermi‐level, producing a conduction barrier with a thermal activation energy Ea = 0.56 eV. The defect band has been identified by deep‐level transient spectroscopy and associated with the defect states typically observed in plastically deformed silicon. The carrier transport behavior across the bonding interface, as well as the observed interface trap levels are therefore attributed to the dislocation network present at the bonding interface.

This work demonstrates the application of a Markov Chain Monte Carlo (MCMC) approach to modeling X-ray reflectometry (XRR) data taken from a sub 10 nm Hafnium oxide film. We present here a comparison of two structural models for a 6 nm HfxOy atomic layer deposition (ALD) film on Si. Using the MCMC method and two distinct structural models, we show evidence of a thin interface between the HfxOy and Si layers with a density much higher than native SiO2. Results from genetic algorithm XRR analysis and thickness measurements using cross-sectional transmission electron microscopy are included for comparison. We also demonstrate that our interpretation of HfxOy thickness differs between the two structural models (i.e., total film thicknesses may be partially additive within each model).

The automated metrology tool, combining X‐ray reflectivity XRR and small‐angle X‐ray scattering SAXS has been demonstrated as a capable equipment to assess standard porous Ultra low‐κ (ULK) metrology. Therefore those techniques have enabled characterizations of several ULK used in sub‐65 nm nodes integration. Standard ULK material for 65 nm node technology has been monitored through the whole C065 integration steps using those combined techniques.

Comparisons with SIMS analyses with nuclear techniques such as elastic recoil detection (ERD), nuclear reaction analysis (NRA), and high‐resolution Rutherford backscattering spectrometry (HR‐RBS), have shown that SIMS analyses without fully oxidizing the analytical area agree well with these techniques at sufficiently high concentrations (where the nuclear techniques are applicable). The ability to measure both the B profile and an oxide marker with this non‐oxidizing SIMS technique also allows accurate positioning of the B profile with respect to the SiO2/Si interface. This SIMS analysis protocol has been used to study the differences in near‐surface dopant distribution for plasma‐based implants. This study specifically focuses on measuring near‐surface profile shapes as well as total implant doses for ultra‐shallow B implants in Si especially those made with high peak B concentrations.

The continuous anodic oxidation technique (CAOT) is specifically designed to rapidly, accurately, and non‐destructively measure the resistivity profile of doped ultra shallow silicon films, either single crystal or polycrystalline, up to a thickness of 1000 A with atomic layer resolution. A localized electrolyte is applied to a small test structure on the surface of a silicon wafer. Direct current passed through the electrolyte between a metallic cathode and the silicon wafer controls the rate of thickness of the silicon surface being converted into silicon dioxide, thus removing doped silicon from the conductive path on the test structure. During the continual anodic oxidation growth, a series of electrical measurements are made on the test structure without removing the overlying anodic oxide or the electrolyte. These measurements permit us to determine incremental sheet resistances taken at various distances from the original surface, and to determine the desired resistivity profile.