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A new technique was developed for embossing microstructures on thermoplastic substrates, which can achieve high accuracy replication with little loss of the production efficiency. The technique is no need of the preheating process and cooling device. In the new technique, just the surface layer of the polymer substrate was heated through heat transmission and ultrasonic viscoelastic heating was the major heat source. For our new technology, the temperature of the mould just provided the initial temperature of the mould-substrate interface and a higher boundary temperature for embossing. The replication accuracies of three embossing technologies were contrasted, including ultrasonic embossing at room temperature (HER), thermal assisted ultrasonic embossing (TUE) and local thermal assisted ultrasonic embossing (L-TUE). The results indicated that, the replication accuracy of L-TUE was approximate with TUE. Moreover, the effects of the processing parameters on the replication quality, including average replication depth and uniformity over the entire chip, were investigated. Different with our prediction, the replication accuracy did not monotonously improved with the ultrasonic force and the temperature of the mold. Finally, the temperature test was carried out to study the temperature characteristic of our new technology. [ABSTRACT FROM AUTHOR]

Two sapphire substrates are tightly bonded through a fresnoite-glass thin film, by irradiation with a 1,064 nm nanosecond laser. The composition of the glass solder at the bond interface changes, due to incorporation of Al from the upper substrate. The oxidic solder remains amorphous after laser irradiation, but after annealing (850 °C for 1 h) crystalline structures are observed in different morphologies, which are attributed not only to fresnoite, but also to Ba-Ti-Al-O phases, which lead to a strong luminescence of the laser irradiated region under UV excitation. [ABSTRACT FROM AUTHOR]

This paper deals with the improvement of the TTV values (Total Thickness Variation) of 300 mm silicon wafers thinned down at 100 μm using the ZoneBond (ZoneBond is registred by Brewer Science Inc.) technology. We have demonstrated that the thin film TTV of the film was mainly driven by the bonding process and was very tolerant towards the coating step. It was also shown that, within the experiment precision, the TTV value was not changed by the grinding thinning process. 8 µm was the best TTV value obtained after the optimization of the bonding parameters. [ABSTRACT FROM AUTHOR]

Direct bonding of InP dies to Si wafer at low temperature utilizing AlO high-κ dielectric as the interfacial material for homogeneous bonding is reported. The bonding technique is assisted with a UV/Ozone exposure for surface activation and the activation time is optimized for the various intermediate layer thicknesses (5, 10, 20 nm). After the pre-bonding stage, annealing is carried out at 300 °C for 3 h. A bonding interface with minimal interfacial voids is reported for low intermediate layer thickness. The bonding interfaces are examined and a homogeneously bonded interface is shown in the IR images as well as in the FIB micrographs. Additionally a heat transfer simulation is also carried out and the InP/AlO-AlO/Si bonded structure is shown to closely match the thermal characteristics of a direct bonding approach with no intermediate layer. A high quality bonding interface is revealed along with improved heat dissipation characteristic for AlO interface. Therefore, AlO proves to be an advantageous candidate for its use in potential Si photonic integrated circuits application. [ABSTRACT FROM AUTHOR]

This paper presents the vacuum wafer level packaging of in-house manufactured two-dimensional micro- mirrors based on the electrostatic driving principle, fabricated using a bulk technology on bonded-silicon-on-insulator wafers. The so called buried signal line concept is used in order to obtain a wafer bond friendly bonding frame. Two versions of the buried signal line concept are described in the paper: crystalline Si and poly-Si based. Anodic and glass frit bonding methods were used to bond a stack of four wafers, resulting in a vacuum-sealed package. The fabrication technology, alignment, bonding, dicing and electrical characterization are discussed. A vacuum level of 120 Pa with no getter materials was reached in the package. Due to vacuum packaging the driving voltage of the micro-mirrors after dicing could be significantly decreased from approximately 170 V to less than 35 V. [ABSTRACT FROM AUTHOR]

This paper presents a new bonding procedure for thick silicon wafers. Those wafers are less flexible and have usually a larger wafer bow. That implicates that standard bonding techniques, such as silicon fusion bonding or anodic bonding, produce non satisfactory yield results. A compliant layer is required to overcome this problem. For the new bonding principle, silicon wafers are structured by a self-masking deep reactive ion etching process. Thereby a forming of needle-shaped nanostructures (known as Black Silicon) on the surface is generated. Between both wafers a green LTCC (low temperature cofired ceramic) foil was placed which assumes multiple functions. The foil is able to compensate the wafer bow, is easy to structure and leads to a quasimonolithic compound after pressure assisted sintering. In the paper the fabrication steps for bonding are explained in detail, especially the adjustment of flexible and unflexible substrates. The interface and the mechanical properties were analyzed and discussed. [ABSTRACT FROM AUTHOR]

Silicon direct wafer bonding is a process with many application areas. Depending on the application, perfect insulation or negligible resistance is desired across the bonded interface. We have investigated the resistivity of hydrophilic high-temperature silicon direct wafer bonds by measuring the resistance across bonded frames suitable for device encapsulation. Frame widths of 100, 200, and 400 µm were fabricated. Hydrophilic pre-bonded laminates resulted in strong bonds and a dicing yield above 89 % for frame widths of 200 µm or wider. The average resistance of dies from boron implanted laminates was 0.35-0.44 Ω, and the average resistance of dies from un-implanted laminates was 0.51-0.68 Ω. All resistances were independent of the bonding area, showing that the resistance of the bonded interface was negligible. Dies from boron implanted wafers had good Al-Si contacts and lower standard deviation of the resistance, indicating that the implantation improved the reliability of the electrical contacts. In the case of boron implanted laminates, the low resistance is explained by a discontinuous SiO and areas with continuous silicon lattice at the bonded interface. The results show that the oxide formed during silicon-silicon direct wafer bonding is broken up during bond annealing for 2 h at 1,050 °C, forming electrical connections of high quality between the two bonded wafers. [ABSTRACT FROM AUTHOR]

Wafer level metal bonding involving copper layers is a key technology for three-dimensional integration. An appropriate surface activation can be performed in order to obtain room temperature direct bonding with bonding strength to be compatible with microelectronic device integration. In this paper, we focus on bonding strengthening mechanisms in the low temperature range from 20 to 100 °C. In order to improve the bonding interface closure, several process parameters are studied: water amount available when surfaces are brought into contact and copper layers deposition technique have been identified to be predominant in this low temperature range. Based on metal oxidation theory, several mechanisms are proposed and some calculations on this bonding strengthening are performed. For the first time, activation energies of this phenomenon are obtained for copper layers deposited by different method in the specific environment of the bonding interface. This study gives guidelines and recommendations for the integration of this metal bonding technique at low temperature. [ABSTRACT FROM AUTHOR]

SOI circuit exhibits excellent performance and rehabilitee but with the component miniaturization trend and the clock frequency increase, the self-heating phenomena that arise from the SOI structure itself must not be underestimated. In order to minimize this problem, several candidates have been identified to replace the buried silicon oxide (SiO) by high thermal conductive dielectric layers such as HfO, SiN, diamond or AlO. In order to elaborate a SOI structure using this kind of innovative buried dielectric, first of all, their direct bonding with silicon has to be studied. In this work, we investigate the bonding thermal behaviour of Si/AlO and AlO/AlO direct bonded structures: bondings are submitted to room temperature up to 900 °C annealing. Amorphous or crystallized AlO thin films were used in this study. Bonding energies are measured in an anhydrous atmosphere and bonding defectivity is analysed using scanning acoustic microscope (SAM). With amorphous a-AlO layer, for T > 200 °C, high bonding energy are obtained even if high defect density appeared when annealing temperature exceeded 400-500 °C. Spontaneous debonding phenomena even occurred for a-AlO/a-AlO direct bonding. This defectivity, unobservable using infrared camera, may be explained by chemical or structural AlO modification such as gases desorption, internal stress or crystallisation state. Bonding with crystallized AlO film has been also characterized by infrared spectroscopy and complementary analysis. No high defect density is observed with crystallized AlO layer. Based on these results, an AlO bonding mechanism is proposed. [ABSTRACT FROM AUTHOR]

Indium phosphide (InP) and gallium arsenide (GaAs) 100 mm wafers were bonded by direct wafer bonding in a cleanroom environment. Unexpected high bow values measured at room temperature after different thermal annealings are the focus of this study. Various experiments such as in situ bow measurements, surface XPS characterizations and TEM cross section observations highlight the key mechanisms that evolve with temperature. Over 200 °C, gallium oxide is formed at the bonded interface due to the presence of water that is trapped at the InP/GaAs interface during the hydrophilic bonding. These results allow us to explain the heterostructure debonding/re-bonding behavior. [ABSTRACT FROM AUTHOR]

The use of reconstructed silicon wafers obtained after high temperature annealing under H atmosphere was demonstrated as an efficient way for increasing the bonding energy of silicon hydrophobic bonding (Rauer et al. ). Mechanisms occurring in these bondings are the focus of this paper. Si bonding interface closure was analyzed at the nanometer scale using X-Ray Reflectivity and Fourier Transform InfraRed spectroscopy in multiple internal reflexion mode. These two characterization techniques enable one to follow the interface closure taking under consideration mechanical and chemical aspects. We have shown that the terrace morphology and the monohydride surface termination specific to reconstructed Si surfaces both play a role in obtaining an efficient bonding gap closure after annealing at low temperature. [ABSTRACT FROM AUTHOR]

Metal wafer bonding is a well-established technology in the semiconductor industry. This technology gains more and more importance due to increasing market demands, particularly for three-dimensional integrated circuits and integration of complementary metal oxide semiconductor and microelectromechanical systems devices used in consumer electronics. Cu-Cu wafer bonding at low temperature is a very attractive process which can be used for both mechanical joints and electrical interconnects in wafer-level processes. In order to facilitate a permanent Cu-Cu bond at low temperature-in contrast to a typical ~400 °C Cu-Cu bonding temperature-the effect of material properties and bonding parameters has to be understood well. Therefore a comprehensive characterization including both, namely surface and interface analysis before and after wafer bonding of non-patterned Cu layers, respectively, is required in order to optimize the Cu-Cu metal wafer bonding process. Low temperature Cu-Cu bonding, namely ≤200 °C, of ~500 nm sputter-deposited Cu films was demonstrated and characterized. Selected analytical methods, such as transmission electron microscopy, Auger electron spectroscopy and electron backscatter diffraction, and their corresponding specimen preparation techniques for microstructure and elemental composition evaluation are introduced. Experimental results of surfaces and interfaces investigation (materials properties with high impact on their bonding behavior), such as the (i) surface roughness, (ii) Cu native oxide, (iii) Cu (surface) purity and (iv) Cu grain size, as well as the influence of the (vi) bonding temperature are presented. [ABSTRACT FROM AUTHOR]

We have realized ultrathin body GaSb-on-insulator (GaSb-OI) on Si wafers by direct wafer bonding technology using atomic-layer deposition (ALD) Al2O3 and have demonstrated GaSb-OI p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Si. A 23-nm-thick GaSb-OI p-MOSFET exhibits the peak effective mobility of ~76cm²/V s. We have found that the effective hole mobility of the thin-body GaSb-OI p-MOSFETs decreases with a decrease in the GaSb-OI thickness or with an increase in Al2O3 ALD temperature. The InAs passivation of GaSb-OI MOS interfaces can enhance the peak effective mobility up to 159 cm²/V s for GaSb-OI p-MOSFETs with the 20-nm-thick GaSb layer. [ABSTRACT FROM AUTHOR]

The mobility of indium on the Zn-polar (0001) surface of single crystal ZnO wafers was investigated using real-time x-ray photoelectron spectroscopy. A sudden transition in the wettability of the ZnO(0001) surface was observed at ~520 °C, with indium migrating from the (000Î) underside of the wafer, around the non-polar (H00) and (1120) sidewalls, to form a uniform self-organized (~20 Å) adlayer. The In adlayer was oxidized, in agreement with the first principles calculations of Northrup and Neugebauer that In2O3 precipitation can only be avoided under a combination of Inrich and Zn-rich conditions. These findings suggest that unintentional In adlayers may form during the epitaxial growth of ZnO on indium-bonded substrates. [ABSTRACT FROM AUTHOR]

This letter reports the influence of the added InGaN interlayer on reducing the inherent interfacial barrier and hence improving the electrical characteristics of wafer-bonded current aperture vertical electron transistors consisting of an InGaAs channel and N-polar GaN drain. The current-voltage characteristics of the transistors show that the implementation of N-polar InGaN interlayer effectively reduces the barrier to electron transport across the wafer-bonded interface most likely due to its polarization induced downward band bending, which increases the electron tunneling probability. Fully functional wafer-bonded transistors with nearly 600 mA/mm of drain current at VGS = 0V and Lgo = 2 μm have been achieved, and thus demonstrate the feasibility of using wafer-bonded heterostructures for applications that require active carrier transport through both materials. [ABSTRACT FROM AUTHOR]

Mechanical contact caused using excessive probe force produces an oversized scrubbing mark that may result in damage to the die pad and the silicon chip breaking for thin wafer. Therefore, investigating the relationship between the wafer thickness and the limited breaking stress of the wafer, and applying this relationship as a basis for establishing suitable design rules for a multilayer needle layout are crucial. In this paper, two experimental techniques, three-point-bending test and ball-on-ring, were setup and carried out to measure the force-displacement relation of various wafer thicknesses (100–25 $\mu $ m). The results from the testing then coupled with finite-element analysis to reverse finding the breaking stress/strain as a function of wafer thickness. In addition, experimental setup with a single tungsten needle probe contact with Al pad were employed to investigate the relations between the overdrive, beam length, and scrub mark length. A 3-D computational probing simulation model was developed and verified against the experimental data. The model is then used to examine the effects of the beam length, overdrive distance (OD), and shooting angle on the maximum stress induced within the wafer. Finally, a four-layer probe card needle shape design has been demonstrated as a practical application example; it is shown that for a wafer thickness of 25 $\mu $ m and an OD of 60 $\mu $ m, the allowable shooting angles of a four-layer needle probe card are as follows: 1500 $\mu $ m and 0°–4° (Layer 1); 2100 $\mu $ m and 0°–9° (Layer 2); 3500 $\mu $ m and 0°–15° (Layer 3); and 4000 $\mu $ m and 0°–15° (Layer 4). [ABSTRACT FROM AUTHOR]

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed. [ABSTRACT FROM AUTHOR]

The fabrication of LiNbO3 waveguide slabs with sub-micron thickness is presented using He ion-induced splitting and the Cu-Sn bonding technique. The exfoliation time of implanted LiNbO3 was investigated as a function of annealing temperatures to reveal the activation energies during the splitting process. Defect-free waveguide films with large areas of several cm2 are consistently produced by using the inter-diffusion bonding of Cu-Sn interface. The fabricated film was investigated by using the Rutherford backscattering/channeling method and dark mode spectroscopy. [ABSTRACT FROM AUTHOR]

The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level. [ABSTRACT FROM AUTHOR]

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 x 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm²/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm²/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes. [ABSTRACT FROM AUTHOR]

Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm²/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density. [ABSTRACT FROM AUTHOR]

We demonstrate pressureless wafer bonding using silver abnormal grain growth caused by stress migration at 250°C, which is very low for a direct solid-state bonding temperature. The bonding achieved a die-shear strength of more than 50MPa, which exceeds the fracture toughness of Si wafer. Various deposition temperatures for the silver films, i.e., initial residual stress, reveal that the bonding process is driven by thermomechanical stress. Abnormal grain growth is induced at the contact interface instead of hillocks growing on the film surface. Pressureless wafer bonding can be applied to advanced devices such as thin-wafer multi-chip integrations. [ABSTRACT FROM AUTHOR]

Wafer-level Cu-Sn intermetallic bonding is an interesting process for advanced applications in the area of MEMS and 3D interconnects. The existence of two intermetallic phases for Cu-Sn system makes the wafer bonding process challenging. The impact of process parameters on final bonding layer quality have been investigated for transient liquid phase wafer-level bonding based on the Cu-Sn system. Subjects of this investigation were bonding temperature profile, bonding time and contact pressure as well as the choice of metal deposition method and the ratio of deposited metal layer thicknesses. Typical failure modes in intermetallic compound growth for the mentioned process and design parameters have been identified and were subjected to qualitative and quantitative analysis. The possibilities to avoid abovementioned failures are indicated based on experimental results. [ABSTRACT FROM AUTHOR]

Regularly distributed dislocation networks with a controllable spacing have been formed by wafer bonding. Different kinds of Si bicrystals were fabricated by (001), (111) and (110) Si wafers bonded with (001) silicon-on-insulator (SOI). NiSi2 formed on the bicrystal was found to be affected by the underlying dislocation arrays, confined by the dislocation grids while the surface stress and dislocation density is high enough. It has been demonstrated that through controlling the surface stress arrangement, the shape of the silicide nanostructures can be controlled and various nanostructures can be obtained. This study supports the fundamental understanding of the stress effect on the formation of silicide nanostructures on Si bicrystals and the shape-controlled nanosilicide could be useful for the growth of catalyst-assisted onedimensional nanostructures. [ABSTRACT FROM AUTHOR]

ABSTRACT Triple-junction solar cells from III-V compound semiconductors have thus far delivered the highest solar-electric conversion efficiencies. Increasing the number of junctions generally offers the potential to reach even higher efficiencies, but material quality and the choice of bandgap energies turn out to be even more importance than the number of junctions. Several four-junction solar cell architectures with optimum bandgap combination are found for lattice-mismatched III-V semiconductors as high bandgap materials predominantly possess smaller lattice constant than low bandgap materials. Direct wafer bonding offers a new opportunity to combine such mismatched materials through a permanent, electrically conductive and optically transparent interface. In this work, a GaAs-based top tandem solar cell structure was bonded to an InP-based bottom tandem cell with a difference in lattice constant of 3.7%. The result is a GaInP/GaAs//GaInAsP/GaInAs four-junction solar cell with a new record efficiency of 44.7% at 297-times concentration of the AM1.5d (ASTM G173-03) spectrum. This work demonstrates a successful pathway for reaching highest conversion efficiencies with III-V multi-junction solar cells having four and in the future even more junctions. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 \mum when 3\,\times\,3-, 5\,\times\,5-, 4\,\times\,9,- or 10\,\times\,10-mm^2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20-\mum-pitch Cu–SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu–SnAg microbumps exhibited ohmic contacts, and the resistance of \sim40~m\Omega/bump was sufficiently low for 3-D large-scale integration application. [ABSTRACT FROM AUTHOR]

In medical ultrasound imaging, mostly piezoelectric crystals are used as ultrasonic transducers. Capacitive micromachined ultrasonic transducers (CMUTs) introduced around 1994 have been shown to be a good alternative to conventional piezoelectric transducers in various aspects, such as sensitivity, transduction efficiency or bandwidth. This paper focuses on a fabrication process for CMUTs using anodic bonding of a silicon on insulator wafer on a glass wafer. The processing steps are described leading to a good control of the mechanical response of the membrane. This technology makes possible the fabrication of large membranes and can extend the frequency range of CMUTs to lower frequencies of operation. Silicon membranes having radii of 50, 70, 100 and 150 µm and a 1.5 µm thickness are fabricated and electromechanically characterized using an auto-balanced bridge impedance analyzer. Resonant frequencies from 0.6 to 2.3 MHz and an electromechanical coupling coefficient around 55% are reported. The effects of residual stress in the membranes and uncontrolled clamping conditions are clearly responsible for the discrepancies between experimental and theoretical values of the first resonance frequency. The residual stress in the membranes is determined to be between 90 and 110 MPa. The actual boundary conditions are between the clamped condition and the simply supported condition and can be modeled with a torsional stiffness of 2.10−7 Nm rad–1 in the numerical model. [ABSTRACT FROM AUTHOR]

The electrical behavior of wafer bonded heterojunctions is usually modeled with the assumption of a pure thermionic conduction at the interface. In this paper, we study the case of highly doped bonded wafers using a Technology Computer Aided Designed (TCAD) modeling approach. Several plausible options of interface including fixed surface charges, interface states densities or a defective interface layer, are discussed and compared with current-voltage measurements. Considering both thermionic and tunnel transport through the interface, we show how the ratio of the competing transport mechanisms depends on the shape of the interfacial energy barrier. Finally, the simulation accurately predicts the effect of the operating temperature on current-voltage characteristics, thanks to a process-compliant description of the direct bonded heterojunction. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Silicon-on-silicon-carbide substrates could be ideal for high-power and radiofrequency silicon devices. Such hybrid wafers, when made by wafer bonding, contain an intermediate silicon dioxide layer with poor thermal characteristics, which can be removed by high-temperature annealing in an inert atmosphere. To understand the dynamics of this process, removal of 2.4-nm-thick SiO layers from Si-SiO-Si and Si-SiO-SiC substrates has been studied at temperatures ranging from 1100°C to 1200°C. The substrates were analyzed by transmission electron microscopy, electron energy-loss spectroscopy, secondary-ion mass spectroscopy, and ellipsometry, before and after annealing. For oxide thickness less than 2.4 nm, the activation energy for oxide removal was estimated to be 6.4 eV, being larger than the activation energy reported for removal of thicker oxides (4.1 eV). Under the same conditions, the SiO layer became discontinuous. In the time domain, three steps could be distinguished: bulk diffusion, bulk diffusion with void formation, and bulk diffusion with disintegration. The void formation, predominant here, has an energetic cost that could explain the larger activation energy. The oxide remaining after prolonged annealing corresponds to one layer of oxygen atoms. [ABSTRACT FROM AUTHOR]

We demonstrate an electrical control of an interfacial trapping effect for hot electrons injected in silicon by studying a magnetic tunnel transistor on wafer bonded Si substrate. Below 25 K, hot electrons are trapped at the Cu/Si interface, resulting in collector current suppression through scattering in both parallel and antiparallel magnetic configurations. Consequently, the magneto-current ratio strongly decreases from 300% at 27K to 30% at 22 K. The application of a relatively small electric field (∼333 V/cm) across the Cu/Si interface is enough to strip the trapped electrons and restore the magneto-current ratio at low temperature. We also present a model taking into account the effects of both electric field and temperature that closely reproduces the experimental results and allows extraction of the trapping binding energy (∼1.6meV) [ABSTRACT FROM AUTHOR]

The stroke of a microelectromechanical systems (MEMS) stage suspended by a flexure mechanism and actuated by electrostatic comb-drives is limited by pull-in. A method to analyze the electrostatic stability of a flexure mechanism and to optimize the stroke with respect to the footprint of flexure mechanisms is presented. Four flexure mechanisms for large stroke are investigated; the standard folded flexure, the slaved folded flexure, the tilted folded flexure and the Watt flexure. Given a certain stroke and load force, the flexures are optimized to have a minimum wafer footprint. From these optimizations it is concluded that the standard folded flexure mechanism is the best flexure mechanism for relatively small strokes (up to ±40 μm) and for larger strokes it is better to use the tilted folded flexure. Several optimized flexure mechanisms have been fabricated and experimentally tested to reach a stroke of ±100 μm. The displacement of the fabricated stages as a function of the actuation voltage could be predicted with 82% accuracy, limited by the fairly large tolerances of our fabrication process. [ABSTRACT FROM AUTHOR]

In this work we describe the bonding and contacting of a micro machined vertically integrated 3-D micro scanner, which is a key-component for a number of scanning imaging micro systems, such as confocal microscopes on-chip or optical coherence tomography (OCT) probes for micro endoscopy. The 3-D micro scanner is composed of two electrostatic silicon MEMS micro actuators which are vertically aligned and bonded with glass and ceramic components to create hermetically sealed cavity for scanning micro lenses. In addition, the through wafer vias (TWV) technology is employed to establish electrical connection from the top to the bottom through a stack of two SOI wafers, one glass wafer and one ceramic wafer. Presented methods are of general importance for various silicon-based vertically integrated devices. [ABSTRACT FROM AUTHOR]

This paper describes a three-dimensional DRAM in which the floating body capacitance (FBC) of a fully depleted SO1 (FD-SOI) device is used as a storage node. This 1T DRAM lends itself particularly well to a 3D wafer-to-wafer bonding process because of the absence of deep etched and filled trench capacitor structure, and the improved thickness control tolerance in wafer thinning. A novel three-tier, 3D, IT embedded DRAM is presented that can be vertically integrated with a microprocessor, achieving low cost, high-density on-chip main memory. A 394 Kbits test chip has been designed and fabricated using the Lincoln Labs 3-Tier 3D 0.18 um fully depleted SO1 CMOS process where an earlier (and previously reported) successful 3D SRAM was obtained. The measured retention time under holding conditions in this 180 nm process is greater than 10 ms. The test chip measures an access time of 50 ns and operates at 10 MHz. [ABSTRACT FROM AUTHOR]

A wafer-level packaging design for GaAs-based image sensor is presented. Key processes, such as GaAs/glass wafer bonding, GaAs substrate thinning, through substrate grooves (TSGs) fabrication, redistribution layer formation, polymer passivation, and laser jet bumping, are examined and characterized. GaAs image sensor package with 64 leads is successfully fabricated on 4-in thinned GaAs/glass test vehicle wafer. In the package, two long TSGs are wet etched as the interconnection path. Process parameters are systematically studied and given. Then, fabrication results of these processes were discussed. Finally, electrical tests show that ohmic contact is obtained with a resistance of around 30 \Omega between two nearby interconnections. [ABSTRACT FROM PUBLISHER]

A new thermosetting polymer, modified poly (diallyl phthalate) (PDAP), is used as intermediate layer to realize a void-free wafer-level transfer bonding, in which the bonding interface contains patterned metal. Through glass–silicon bonding experiments, bonding defects are easily recognized with light microscopy. Three typical defect types are identified as: uneven flow defect, particle defect and bubble defect. The processing parameters, such as bonding pressure, pre-baking temperature, polymer thickness and coating conditions, have been optimized based on analysis of the defect formation. The optimized conditions have yielded a void-free wafer-level adhesive bonding. Then, the die shearing test indicates a good bonding strength. Additionally, the transfer bonding process is applied in SOI–silicon bonding as a practical example of MEMS fabrication. [ABSTRACT FROM AUTHOR]

The objective of this study is to optimize the Cu/Sn solid–liquid interdiffusion process for wafer-level bonding applications. To optimize the temperature profile of the bonding process, the formation of intermetallic compounds (IMCs) which takes place during the bonding process needs to be well understood and characterized. In this study, a simulation model for the development of IMCs and the unreacted remaining Sn thickness as a function of the bonding temperature profile was developed. With this accurate simulation model, we are able to predict the parameters which are critical for bonding process optimization. The initial characterization focuses on a kinetics model of the Cu 3Sn thickness growth and the amount of Sn thickness that reacts with Cu to form IMCs. As-plated Cu/Sn samples were annealed using different temperatures (150°C to 300°C) and durations (0 min to 320 min). The kinetics model is then extracted from the measured thickness of IMCs of the annealed samples. [ABSTRACT FROM AUTHOR]

This paper presents a MEMS energy harvesting device which is able to generate power from two perpendicular ambient vibration directions. A CYTOP polymer is used both as the electret material for electrostatic transduction and as a bonding interface for low-temperature wafer bonding. The device consists of a four-wafer stack, and the fabrication process for each wafer layer is described in detail. All the processes are performed at wafer scale, so that overall 44 devices can be fabricated simultaneously on one 4-inch wafer. The effect of fabrication issues on the resonant frequency of the device is also discussed. With a final chip size of about 1 cm2, a power output of 32.5 nW is successfully harvested with an external load of 17 MΩ, when a harmonic vibration source with an RMS acceleration amplitude of 0.03 g (∼0.3 m s−2) and a resonant frequency of 179 Hz is applied. These results can be improved in an optimized design. [ABSTRACT FROM AUTHOR]

We increased the active region/waveguide thickness of terahertz quantum cascade lasers with semi-insulating surface plasmon waveguides by stacking two symmetric active regions on top of each other, via a direct wafer bonding technique. In this way, we enhance the generated optical power in the cavity and the mode confinement. We achieved 470 mW peak output power in pulsed mode from a single facet at a heat sink temperature of 5 K and a maximum operation temperature of 122 K. Furthermore, the devices show a broad band emission spectrum over a range of 420 GHz, centered around 3.9 THz. [ABSTRACT FROM AUTHOR]

We have studied the formation of III-V-compound-semiconductors-on-insulator (III-V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III-V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O2 plasma-assisted DWB process with ECR sputtered SiO2 BOX layers and a DWB process based on atomic-layer-deposition Al2O3 (ALD-Al2O3) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO2 and ALD-Al2O3 BOX layers are desorption of Ar and H2O gas, respectively. In order to suppress micro-void generation in the ECR-SiO2 BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al2O3 BOX layers to increase the deposition temperature of the ALD-Al2O3 BOX layers. It is also another possible solution to deposit ALD-Al2O3 BOX layers on thermally oxidized SiO2 layers, which can absorb the desorption gas from ALD-Al2O3 BOX layers. [ABSTRACT FROM AUTHOR]

Adhesion energies are determined for three different polymers currently used in adhesive wafer bonding of silicon wafers. The adhesion energies of the polymer off-stoichiometry thiol-ene-epoxy OSTE+ and the nano-imprint resist mr-I 9150XP are determined. The results are compared to the adhesion energies of wafers bonded with benzocyclobutene, both with and without adhesion promoter. The adhesion energies of the bonds are studied by blister tests, consisting of delaminating silicon lids bonded to silicon dies with etched circular cavities, using compressed nitrogen gas. The critical pressure needed for delamination is converted into an estimate of the bond adhesion energy. The fabrication of test dies and the evaluation method are described in detail. The mean bond energies of OSTE+ were determined to be 2.1 and 20 J m-2 depending on the choice of the epoxy used. A mean bond energy of 1.5 J m-2 was measured for mr-I 9150XP. [ABSTRACT FROM AUTHOR]

In this study, a sandwiched titanium-on-glass (TOG) substrate was used to fabricate laterally driven microelectromechanical systems devices with bulk titanium as the structural material. 4" TOG wafers with a titanium device layer of 25 μm were fabricated by low temperature SU-8 wafer bonding and chemical mechanical polishing. By using inductively coupled plasma for titanium deep etching as well as dry release, suspended high-aspect-ratio bulk titanium structures were realized with only one mask. A laterally driven electrostatic comb-driven bulk titanium resonator was manufactured as a preliminary demonstration. The resonator achieves a quality factor of 110 at 34 kHz, and survived 10 000 g shock without damage. Due to the high mechanical endurance and excellent corrosion resistance of titanium, TOG technology may open up many new applications in harsh environments. [ABSTRACT FROM AUTHOR]

The anodic bonding technique, which is primarily used in glass to silicon wafer bonding, has been extensively used in microelectromechanical systems (MEMS) for the packaging of microsensors and microactuators. When the bonding voltage is applied, the bonded region instantly occurs at the contact point of the cathode with the glass. The geometric shape or arranged pattern of the cathode electrode significantly affects the bonding quality, particularly the gas-trapping at the bonded interface and the bonding time. This paper presents a novel anodic bonding process, in which the non-contacting and rotating electrode with radial lines is used as the cathode for scan bonding with arc-discharge assistance. The experimental results show that a bonding ratio of 99.98% and an average bonding strength of 15.45 MPa for a 4-inch silicon/glass bonded pair can be achieved in a 17 s bonding time by using a cathode electrode with eight 45 included-angle radial lines at a rotation speed of 0.45 rpm, a non-contact gap of 120 µm, a bonding voltage of 900 V and a bonding temperature of 400 ?C. This ultrafast and high-quality anodic bonding has been synchronously realized under this scan bonding technique. [ABSTRACT FROM AUTHOR]

Monolithic fabrication of continuous facesheet high-aspect ratio gold microelectromechanical systems (MEMS) deformable mirrors (DMs) onto a thermally matched ceramic--glass substrate (WMS-15) has been performed. The monolithic process allows thick layer deposition (tens of microns) of sacrificial and structural materials thus allowing high-stroke actuation to be achieved. The fabrication process does not require wafer bonding to achieve high aspect ratio three-dimensional structures. A gold continuous facesheet mirror with 3.4 nm surface roughness has been deposited on a 16 x 16 array of X-beam actuators on a 1-mm pitch. A stroke of 6.4 µm was obtained when poking two neighboring actuators. Initial electrostatic actuation displacement results for a high-aspect ratio gold MEMS DM with a continuous facesheet will be discussed. [ABSTRACT FROM AUTHOR]

With an enlargement of the wafer size, development of large-area plasma sources and control of plasma density distribution are required. To control the spatial distribution of the plasma density, wireless power transfer is applied to an inductively coupled plasma for the first time. An inner powered antenna and an outer resonant coil connected to a variable capacitor are placed on the top of the chamber. As the self-resonance frequency ?r of the resonant coil is adjusted, the power transfer rate from the inner powered coil to the outer resonant coil is changed and the dramatic evolution of the plasma density profile is measured. As ?r of the outer resonant coil changes from the non-resonant condition (where ?r is not the driving angular frequency ?rf ) to the resonant condition (where ?r = ?rf ), the plasma density profile evolves from a convex shape with maximal plasma density at the radial center into a concave shape with maximal plasma density in the vicinity of the resonant antenna coil. This result shows that the plasma density distribution can be successfully controlled via wireless resonance power transfer. [ABSTRACT FROM AUTHOR]

A novel stress-relaxation structure with a ring-shaped beam for ensuring stability in a piezoresistive three-axis accelerometer assembled using wafer-level encapsulation and resin-mold packaging is proposed and evaluated in this paper. The reduction of the unstable increase in sensitivity due to buckling against three stress sources, i.e., the thermal stress in device fabrication, wafer bonding, and resin molding, was evaluated by both computer simulation and experiments on test samples. The measured increase in sensitivity due to stress during wafer bonding and resin molding was kept at 1.26 times using the ring-shaped beam, compared with 7.64 times when using a conventional straight beam. In addition, the standard deviation in the sensitivity of resin-molded samples was kept at 0.04 mV/G using the ring-shaped beam, compared with 2.19 mV/G using the straight beam. The sensitivity variation against the temperature change was also kept small and linear; thus, the effect of the ring-shaped beam was confirmed. \hfill[2012-0125] [ABSTRACT FROM PUBLISHER]

Serious wafer bending and residual stress are formed during the growth of the epi-GaN layer on a sapphire substrate due to the difference of the thermal expansion coefficients (TECs) in these two different materials. Using the theoretical analysis and a simulation model with the finite element method to describe the realistic shape for the wafer bending of epi-GaN wafers, we examine the influence of different thicknesses and TECs in the top epi-GaN layer for wafer bending reduction. Furthermore, wafer bending is also found to be worse when the process temperature and the wafer size become higher and larger. Although commercial patterned sapphire substrate can partially solve this issue, the quality of the epi-GaN layer, grown on this patterned substrate, will be impacted. In this work, the new process to reduce the wafer bending and relax the residual stress is proposed. With an additional laser treatment on the sample surface after the growth of the top epi-GaN layer on the sapphire substrate, a slight crack can provide the extra space for the relaxation of the residual stress and will not influence the GaN quality. The wafer bending can be reduced to ~37µm from the original ~45µm in the 2 inch wafer with optimized surface structure design by this treatment. [ABSTRACT FROM AUTHOR]

Micro-optoelectromechanical systems (MOEMS) deformable mirrors are being developed for focus control in miniature optical systems including endoscopic microscopes and small form-factor camera lenses. A new process is described to create membrane mirrors made from the photoset polymer SU-8. The SU-8 also serves as the adhesive layer for wafer bonding, resulting in a simple, low cost fabrication process. The process details and the optical properties of the resulting focus control mirrors, which have a diameter of 2 mm, a stroke in excess of 8 µm and very low residual aberration, are described. Multiple actuation electrodes allow active control of more than 1.4 µm peak-to-peak of wavefront spherical aberration. The MOEMS mirror is demonstrated in a confocal microscope in which it provides focus control during capture of in vivo images. [ABSTRACT FROM AUTHOR]

The ultra-thin body and ultra-thin buried-oxide (UTBB) Germanium-on-Insulator (GeOI) substrates have been fabricated by direct wafer bonding and polishing techniques. The Ge and BOX layer thicknesses are as thin as 9 and 13 nm, respectively. The UTBB GeOI substrates exhibit superior crystal quality (similar to the bulk single crystalline Ge) and sufficiently reduced surface roughness. As a result, the Hall hole mobility of UTBB GeOI reaches 1330 cm²/V s with a carrier concentration of 2 × 1016cm-3. The inversion mode UTBB GeOI nMOSFETs have also been demonstrated with suppressed mobility degradation during Ge layer thinning, indicating the feasibility of this GeOI substrate formation technique in future CMOS technologies. [ABSTRACT FROM AUTHOR]

A new concept of microelectromechanical system based thermoelectric power generator (TPG) with unique heat dissipation path is investigated in this study. By using solder based wafer bonding technology, the authors can bond three pieces of wafers to form vacuum packaged TPG. According to the finite element method and analytical modeling results, the output power per area of device is derived as 68.6 μW/cm2 for temperature difference of about 6 °C between two ends of thermocouple junctions. It shows that the proposed device concept is an effective and low cost approach to enhance the output voltage. [ABSTRACT FROM AUTHOR]