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Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

We report on the continuous-wave and passively Q-switched waveguide laser at the wavelength of ~1024 nm, based on the (Yb0.1Y0.9)3(Sc1.5Ga0.5)Ga3O12 (Yb:YSGG) crystal. The ridged waveguide was fabricated on the surface of 100 at. % Yb:YSGG crystal by the swift ion irradiation and the precise diamond blade dicing. Utilizing this waveguide as the gain medium and resonant cavity, the laser emission at ~1024 nm was realized. Coating the Tungsten Disulfide onto the waveguide surface as the saturable absorber, the Q-switched laser emission was also obtained with the pulse duration of 125 ns.

We report on an optical signal amplifier based on an Er:MgO-doped near stoichiometric lithium niobate (Er:MgO:SLN) waveguide. The Er:MgO:SLN waveguide was fabricated using swift carbon ion irradiation combined with precision diamond blade dicing. Under 980 nm laser pumping, the waveguide provides a 2.13 dB/cm gain at 1536 nm, 1.49 dB/cm gain at 1552 nm, and 1.37 dB/cm gain at 1565 nm, with the pumping power of 99.5 mW. This work demonstrates the potential application of swift ion irradiated Er:MgO:SLN waveguides for the optical amplifiers in the C communication band.

The evidence of multi-photon absorption enhancement by the dual-wavelength double-pulse laser irradiation in transparent sapphire was demonstrated experimentally and explained theoretically for the first time. Two collinearly combined laser beams with the wavelengths of 1064 nm and 355 nm, inter-pulse delay of 0.1 ns, and pulse duration of 10 ps were used to induce intra-volume modifications in sapphire. The theoretical prediction of using a particular orientation angle of 15 degrees of the half-wave plate for the most efficient absorption of laser irradiation is in good agreement with the experimental data. The new innovative effect of multi-photon absorption enhancement by dual-wavelength double-pulse irradiation allowed utilisation of the laser energy up to four times more efficiently for initiation of internal modifications in sapphire. The new absorption enhancement effect has been used for efficient intra-volume dicing and singulation of transparent sapphire wafers. The dicing speed of 150 mm/s was achieved for the 430 μm thick sapphire wafer by using the laser power of 6.8 W at the repetition rate of 100 kHz. This method opens new opportunities for the manufacturers of the GaN-based light-emitting diodes by fast and precise separation of sapphire substrates.

A broadband antireflective subwavelength structure was developed suitable for large diameter silicon or alumina lenses used in the optical systems of superconducting cameras. In this study, a broadband antireflective subwavelength structure that can be easily fabricated with a dicing blade was designed. The model comprised both a pyramidal section (550 $\mu$ m in depth) and a straight section (150 $\mu$ m in depth) to simplify fabrication with a metal bonded V-shaped blade and a normal straight dicing-blade. The simulated transmittance between 97 and 334 GHz was > $\text{90}\%$ , which is comparable to that with a 700- $\mu$ m-depth tapered structure. The structure was fabricated on a flat surface, and transmittance at cryogenic temperatures was measured using a Fourier transform spectrometer. The measured average transmittance between 186 and 346 GHz was approximately 95 $\%$ , and the experimental result is in good agreement with the simulation results.

This paper presents the optimization work of 355 nm ultraviolet (UV) laser diode ablation process for CMOS 45 nm Copper (Cu) low-k semiconductor wafer. The micromachining parameters included laser power, laser frequency, feed speed, and defocus amount were optimized via design of experiment (DOE). Package reliability stressing tests were carried out as part of the efforts to validate the robustness. The results show that high repetition rate, low laser pulse energy and a high pulse overlap produced zero dicing defects. The laser groove depth increased as the laser pulse energy increased. It is shown that, laser grooving is one of the best solutions to choose for dicing quality, throughput and yield improvements for CMOS 45 nm Cu low-k wafer dicing.

In this paper, an on-machine error calibration method, covering error modeling and measurement, is proposed to evaluate and compensate the errors caused by the mechanical and optical system equipped in the micromachining center using the femtosecond laser. Through preliminary tests by dicing silicon wafer, it has revealed that the squareness, laser beam misalign and focal position offset, are the main causes to result in the inaccuracy of micromachining. Consequently, an error modeling method is proposed to evaluate the error distribution in the workspace, and hereafter a comprehensive error vector of the laser beam, combining the squareness errors of Z-axis with the laser beam misalign, is generated by the variable substitution method. Subsequently, an increment error model in the instant local coordinates is established to satisfy the requirement of the programming method commonly used in the laser machine tools. Furthermore, a series of holes and grooves are machined on the femtosecond laser micromachining center to validate the proposed approach and model. The machining dimensions including diameters, distances and angles, are measured on-machine to identify the squareness errors, laser beam misalign and focal position offset according to the proposed error model. Finally, the experimental results show that, comparing to the uncompensated tests, the machining accuracy has been significantly improved with the proposed method.

Glass is an ideal material for package substrates due to the excellent electrical properties, tailorable coefficient of thermal expansion, high mechanical rigidity, availability in large and thin panel form, and smooth surface for fine line fabrication. Glass does have challenges, arising mainly from the brittle nature of glass, and glass substrates with copper and polymer re-distribution layers can suffer brittle fracture after dicing processes. This paper demonstrates three methods to prevent cracking induced by redistribution layer (RDL) stress and dicing defect in glass substrates for RDL build-up up to $90~ {\mu }\text{m}$ polymer and $40~ {\mu }\text{m}$ copper. These methods are edge coating, two-step dicing, and laser ablation dicing. Edge coating is a protective layer of polymer located on the diced edge of the glass substrate. After dicing, edge coating puts the glass in compression and prevents moisture from reaching the glass and, in turn, prevents the glass cracking from RDL stresses and dicing defects. In two-step dicing, the first step is used to ablate the RDL using a laser and the second step is used for blade dicing within the ablated region to singulate the glass. The resulting structure from such a dicing process reduces stress at the free glass edge, ensuring that the glass does not crack during dicing. Two-step dicing also allows for thicker RDL build-ups while ensuring no glass cracking occurs from dicing defects. Laser ablation dicing uses a CO2 laser to singulate the glass panel into individual substrates instead of blade dicing, which reduces the dicing defect size and creates a heat affected zone. Use of laser ablation dicing allows for thicker RDL build-ups with minimal process change when compared to blade dicing.

A simple process to improve the quality factor of metal–insulator–silicon (MIS) capacitors is introduced. Typically, MIS capacitors show a low quality factor in the gigahertz range because the lower electrode is silicon, which has low conductivity. The electrical conductivity of the lower electrode of the MIS capacitor is improved by the application of side metal coating through a simple process. To make the side metal of the MIS capacitor, a 200 µm-deep trench is formed between each capacitor using a sawing machine, and then the top electrode and side metal coating are added at the same time. Since scribing is performed prior to realisation of the top electrode, no additional dicing process is required. The quality factor of the proposed capacitor is improved from 73.8 to 101.3 at 2 GHz just by the addition of the side metal electrode.

In flip chip mounting process, chip is fragile since chip is not protected by mold resin. It is known that the backside coating tape has been used widely to correspond to blade dicing. We had developed a release sheet integrated backside coating tape corresponding to blade dicing for a thin wafer. On the other hand, stealth dicing becomes popular to prevent chipping. In this study, we investigate the process of release sheet integrated backside coating tape corresponding to stealth dicing. we evaluate process consisting of stealth dicing, mount, laser marking, cool expanding, heat shrinking, heat curing and pick up. As a result, it is found that it is possible to manufacture a chip with backside coating layer in lower height expanding by optimization of the base film material of release sheet and expanding condition.

In wafer fabrication, most machining processes such as slicing, edge grinding, finishing, lapping, polishing, back thinning and dicing, are based on grinding or/and abrasive process, which always generate micro cracks and subsurface damage. In this chapter, theoretical analysis on ductile mode cutting of silicon wafer shows that machined silicon surface with free of fracture and nanometer scale surface roughness can be achieved when dislocation dominates its chip formation rather than crack propagation. Nanometric cutting of silicon wafers using an ultra-precision CNC lathe with single crystal diamond cutters are carried out to investigate the tool edge radius effect on critical undeformed chip thickness and verify ductile mode cutting performance of silicon wafer. Machined workpiece surfaces and used diamond tools are examined using a scanning electron microscope (SEM), transmission electron microscopy (TEM) and atomic force microscope (AFM). Experimental results from the nanometric cutting tests indicate that in cutting of silicon wafers, there is a critical undeformed chip thickness, at or below which chip formation is under ductile mode cutting generating continuous chips. And critical undeformed chip thickness differs when cutting of silicon wafers using diamond cutters with different tool edge radius. Larger diamond tool edge radius, larger critical undeformed chip thickness. But there is an upper bound for diamond tool edge radius, above which chip formation is changed from ductile mode to brittle mode even though undeformed chip thickness remains to be smaller than tool edge radius. Experimental results are found to well substantiate the analytical findings and nanometric ductile mode cutting of silicon wafer is successfully achieved under certain cutting conditions.

Blade dicing compatible particle protective layer is investigated for feasibility study of collective Die-to- Wafer (D2W) direct bonding. Having the compatibility to blade dicing, the protective layer needs to be insoluble for de-ionized water (DIW), because blade dicing requires cooling water to maintain the cutting performance. Therefore, polymers soluble in alkaline solutions (e.g. TMAH, NH 4 OH), however, insoluble in DIW are tested for collective die to wafer direct bonding. With the dicing particle protective layer technology, successful collective die to wafer direct bonding with current die assembly tools are achieved. The alternative protective layer ensures high yield and cost of ownership for collective die to wafer integration

TLS-Dicing (Thermal Laser Separation) is a unique technology for separating wafers into single chips in semiconductor back end processing. TLS-Dicing uses thermally induced mechanical stress to separate brittle semiconductor materials, like silicon (Si) and silicon carbide (SiC) wafers. TLS is a two-step TLS-Dicing method consisting of scribing and cleaving. The scribing is used to create a starting point of the second step – the cleaving step. A continuous wave laser in combination with water spray cooling generates a thermal distribution. This leads to a mechanical stress capable to guide one defined crack along the dicing street which leads to the separation of the material. This work investigates a new scribing method – the Deep Scribe – in detail. While using Deep Scribe a pulsed laser beam of near infrared wavelength is focused with an objective into the silicon. This generates a line of subsurface material modification. By using this scribe technique no particles occur at the surface. Additionally, straightness and the bending strength of separated silicon chips can be improved in comparison with state of the art dicing technologies. In this presentation, we will discuss the latest developments in Deep Scribe TLS with focus on the physical effects of the interaction between laser beam and material, as well the requirements for generation of a Deep Scribe. We will investigate the influence of adjusting parameters such as focus position, duration of laser pulse and laser power, on position and size of the modified area. We will also study the effects of thermal laser separation with Deep Scribe on bending strength of diced chips, a crucial parameter for wafer thinning applications. For comparison, similar wafers were cut with current state-of-the-art mechanical blade dicing.

Gallium nitride (GaN)-based high-electron-mobility transistor (HEMT) power devices have advantage like high voltage operation, high temperature application and high switch speed compared to the traditional silicon (Si)-based semiconductor devices. Due to GaN high cost, it had development combined on a variety of substrates, including sapphire, silicon carbide (SiC) and silicon (Si). Si substrates have become attractive because of the lower device cost and the ability to use standard semiconductor processing lines. The challenges of GaN on Si substrate are big lattice mismatch and hard characteristic of III–V material. Die sawing is a key process due to the GaN brittle characteristic that can cause chipping and mircocracks that cause bad thermal dissipation for devices.In paper, we optimize dicing capabilities in the Flip Chip Scale Package (FCCSP). Due to GaN layer has higher hardness and melting point than Si substrate, Laser Grooving is recommended to use before the blade saw GaN layer and reduce top chipping. On GaN layer result of Laser Grooving cut is very clean on the topside of the die with no chipping issues. Backside quality is a key monitor item of die sawing due to the excessive force required to break and separate the hard III–V material. This paper finds out a suitable die sawing process parameter to meet backside chipping spec and a competitive result compared to Si die sawing.The characterization analysis is including typical reliability testing (Temperature Cycle Test, un-bias HAST and High Temperature Storage Test) are used as verification monitor items for package. The result shows no delamination and SAT issues in the reliability stage.

This paper addresses large dies stitching challenges. Stitching is a way to combine several shots "stitched together" to create a die larger than what can fit on a photomask. This technique that was originally dedicated to advanced research is now more widely used and requires a fully automated industrial flow. Technical constraints come from a number of different actors and results must be shared by even more teams. We will present the methodology used to optimize both the yield and the data exchange between cross-functional teams. We will show how this automated flow can be easily customized to save more silicon thanks to advanced dicing techniques.

We have demonstrated the first MgO:PPLN ridge waveguides based on ZnO indiffusion and dicing. The fabrication process utilizes ductile regime dicing of a planar waveguide layer producing second harmonic generation (SHG) devices with a near-symmetric sinc2 spectral profile, indicating highly uniform 40 mm long devices. A near circular pump mode is also obtained enabling efficient coupling to single mode telecommunication fibers. A conversion efficiency of 145%/W, for 1560-780 nm SHG, has been measured.

The development of facile, reliable and low temperature soldering plays a crucial role when the physical and chemical characteristics of the materials are very critical. In case of piezoelectric material, i.e. high dielectric constant PZT (Lead Zirconate Titanate), the Curie temperature is in the range of (130-150)°C as for the Rhombohedral-to-tetragonal phase Temperature ${\mathrm {(T_{RT})}}$ of PMN-PT (Lead Magnesium Niobate – Lead Titanate) that is usually below 100°C. The study aims to analyze the defects occurring during the manufacturing process of an Ultrasound (US) transducer for medical imaging with a low melting temperature Sn/In (52/48) solders. The effects and the root cause offouling of the Sn/In solderings due to the galvanic corrosion have been detected by means of Scanning Electron Microscope (SEM) and Energy Dispersive X-ray (EDX) analysis. The paper has been focused on the mechanical dicing process of the US transducers and, in particular, on the blade cooling water that showed large quantities of metals, i.e. Tungsten (200mglL). The cooling water quality explains the kinetics and the root cause of the galvanic corrosion. The residual metals of the mechanical dicing process in the cooling water activated the galvanic corrosion phenomenon on the US transducers due to the low redox potential of the indium by makingprohibitive the weldability and the reworkability of the Sn/In solder.

University research computing centers are increasingly faced with the need to support applications that are better suited for cloud infrastructure than HPC infrastructure. A common approach is to shoehorn cloud-based applications onto the university's existing HPC system, which has been done with varying levels of success. Another approach as been to create stand-alone HPC systems and private cloud systems, resulting in ineffective use of resources. A more recent approach has been to use hybrid systems where the HPC system "bursts" excess jobs to private cloud nodes configured as bare-metal nodes built from the same (expensive) hardware as the HPC system.This paper explores another model, namely the use of private cloud infrastructure (built from inexpensive commodity networks and storage systems) to host both HPC jobs and VMs simultaneously Utilizing VMs allows these emerging applications to leverage cloud frameworks specifically designed for them (e.g., OpenStack, Kubernetes, Mesos, Hadoop, and Spark), while at the same time effectively supporting a growing percentage of the HPC jobs (e.g., single node jobs, and embarrassingly parallel jobs). Because the system can be constructed from commodity cloud networks and storage, it makes cost-effective use of the resources as opposed to HPC systems used to run jobs that do not use (waste) its expensive resources.To demonstrate the advantages of using cloud infrastructure for both cloud applications and HPC applications, we describe a system that can dynamically launch OpenHPC systems on commodity OpenStack infrastructure. Moreover, users can use the system to deploy "personal" OpenHPC clusters, customized to their application's needs (e.g., number of nodes, cores per node, memory per node). We have used the system to effectively run OpenHPC work-loads on a cluster of large memory OpenStack nodes, allowing users to create, for example, a large memory HPC-style cluster of 500 GB nodes running OpenHPC, and a cluster of 1TB VMs operating simultaneously. Performance degradation due to virtualization has been insignificant, particularly when compared to the advantages of being able to use optimized frameworks running on cost-effective hardware.

This paper provides a generic way to fabricate a high-index contrast tapered waveguide platform based on dielectric crystal bonded on glass for sensing applications. As a specific example, KLu(WO4)2 crystal on a glass platform is made by means of a three-technique combination. The methodology used is on-chip bonding, taper cutting with an ultra-precise dicing saw machine and inductively coupled plasma-reactive ion etching (ICP-RIE) as a post-processing step. The high quality tapered waveguides obtained show low surface roughness (25 nm at the top of the taper region), exhibiting propagation losses estimated to be about 3 dB/cm at 3.5 μm wavelength. A proof-of-concept with crystal-on-glass tapered waveguides was realized and used for chemical sensing.

In the silicon dicing processes, the laser induced thermal-crack propagation (LITP) has been reported about its superiority over traditional dicing methods in aspect of crack surface quality and mechanical properties. However, this process may cause deviation of its propagation path especially under the condition of asymmetric linear cutting. Aiming to solve the path-deviation problem, a method of pre-crack on the surface of the silicon wafer has been proposed. A mathematical model which consists absorption of laser, heat transfer, generation of thermal stress, and crack initiation and propagation, has been established. Numerical simulation in the LITP of silicon wafer with respect to two pre-crack modes: pre-crack on the end and pre-crack on the surface were conducted to study the high-quality crack propagation mechanism. Unbiased crack propagation was found in the simulation of pre-crack on the surface process and the mechanism of it was revealed through the analysis of the tensile stress distribution. It was found that the three-dimensional shape of the tensile stress at the front of the crack tip would result in an uncertain propagation in conventional LITP of pre-crack on the end. Conversely, the slice shape of the tensile stress would induce a certain propagation direction that was along the plane of the pre-crack in the simulation of pre-crack on the surface. The experimental results verified the unbiased propagation mode and showed good crack surface quality.

In this study, a low temperature wafer-level packaging process aimed for encapsulating MEMS mirrors was developed. The glass cap wafer used in the package has an antireflective (AR) coating that limits the maximum temperature of the bonding process to 250°C. Copper thermocompression was used as copper has a high self-diffusivity and the native oxidation on copper surfaces can be completely removed with combination of ex situ acetic acid wet-etch and in situ forming gas anneal. Making it suitable for a development of a low temperature bonding process. In this work, bonding on of sputtered and electrodeposited copper films was studied on temperatures ranging from 200°C to 300°C as well as the effect of pretreatment on bond strength. The study presents a successful thermocompression bonding process for sputtered Cu films at a low temperature of 200°C with high yield of 97 % after dicing. The bond strength was recorded to be 75 MPa, well above the MIL-STD-883E standard (METHOD 2019.5) rejection limit of 6.08 MPa. The high dicing yield and bond strength suggest that the thermocompression bonding could be possible even at temperatures below 200°C. However, the minimum bonding temperature was not yet determined in this study.

While recent advances in femtosecond writing have allowed rapid and flexible realization of lab-on-chip and integrated optics systems in various media, miniaturisation of such fs-written waveguide architectures remains hampered by high bend loss α b . Despite efforts to reduce bend loss, e.g. by annealing the waveguides [1] or writing stress structures [2], the minimum bend radius at telecommunications wavelengths remains large (> 16mm) in silica [1]. To overcome this, we demonstrate a novel bend loss reduction method by inducing stress to fabricate a microcrack on the outer bend edge of the waveguide. The large index difference at the core-microcrack interface (1.45 vs 1.0) enhances modal confinement and inhibits radiation loss. Laser induced stress cracking is often used for dicing glass sheets with excellent smoothness (roughness < 30nm) [3]; hence such cracks will not exacerbate scattering losses when integrated alongside a waveguide.

This paper reports the design, fabrication and evaluation of a reflection-type micro Rb vapor cell fabricated by local anodic bonding of small 45° mirrors. The 45° mirrors with a Bragg reflector are fabricated by using dicing process. The vapor cells having a horizontal cavity with the 45° mirrors at the both ends are fabricated by anodic bonding process. Optical absorption of Rb and CPT (Coherent Population Trapping) resonance for atomic clock operation are evaluated.

A vertical interconnect technology for stacking micro solid thin film batteries (STFB) in IoT devices is proposed. This technology consists of stacking glass substrates with a layer of solid thin film battery, drilling by laser machining, filling the holes with solder to connect the stacked batteries, and dicing the stacked wafer to 1×1 mm micro stacked batteries. In this work, various metals are evaluated to identify the appropriate electrode drilled with glass and resin. The effects of the laser wavelength are also investigated.

For all applications where a semiconductor device is used, there is a demand for improved performance under all environmental conditions. One such application, which is in regular use, is the smartcard chip that is found predominantly in bank or travel cards and passports. These may endure harsh physical treatment in normal usage and the demands for severe robustness criteria for these card-based applications are continually increasing to ensure that the packaged chips are able to continue functioning without breaking. Key to achieving these exacting standards is the singulation of the chips in a way that does not generate any inherent mechanical weakness. The standard blade sawing process has so far met existing requirements but the technology roadmap for such devices has presented new challenges with the deployment of fragile ultra-low k BEOL dielectrics. This has prompted the introduction of laser grooving before dicing to minimize damage to these materials caused by the sawing blade but this, in combination with mechanical dicing, can itself result in weakening of the die and a higher risk of failure. Plasma dicing has the potential to improve die breakage strength significantly, essentially as there is no mechanical element to the dicing action. However, this technique requires that the silicon be exposed in the dicing street, which must be free of metals and dielectrics before etching. Under some circumstances this can be achieved by mask design and dedicated processing but in practice laser grooving is again a prime candidate for meeting these conditions. To be compatible with the plasma etching process the laser recipe needs to be optimized according to both the presence and layout of test structures in the dicing street. An influential factor is that the options for the street layout are themselves dependent upon the front-end technology and its complexity level. This paper will examine how laser grooving process adjustments devised to promote successful plasma dicing integration can affect the die strength whilst adapting to different structures and materials contained in the dicing street. We will compare results between alternative plasma dicing integration schemes to show how design layout for the scribe lane influences their choice, especially where die strength is a priority. We will also investigate the impact of varying some of the etch process output parameters to seek an understanding of whether the etching step itself has a role to play in die robustness improvement for the practical, future application of plasma singulation to real cases on an industrial scale.

As the materials that the wafer dicing process need to singulate become more complex a diverging current Process of Record (PoR) dicing technologies are not able to meet the quality and or cost requirements. Laser provides the solution to dice all these different materials but has the challenge to achieve the die strength level specified. In this paper we will elaborate on the advances made to apply a laser full cut process while achieving the required die strength.

Recent developments in high-speed communication technology have accelerated reductions in the size and thickness of semiconductor packages. Fan-out wafer level packaging (FO-WLP) is an emerging packaging trend. Considering cost and scalability, there are also high expectation for ultra-thin Flip chip-Chip scale package (FC-CSP) technology which has evolved into a structure that is an approaching die-sized dimensions. As the packaging structure changes to Ultra-thin FC-CSP, it is necessary to control package warpage with smaller quantity of epoxy molding compound (EMC.) This study evaluated strip warpage of molded array package (MAP) and singulated unit warpage after dicing to investigate the effect of EMC properties on the package warpage. It has been understood that the mold shrinkage of EMC is the most dominant factor in warpage control of packages. However, the degree of warpage amount is not proportional to various properties in a packaging structures with a high ratio of silicon die to EMC, such as Ultra-thin FC-CSP when modelling low strip and unit warpage. For strip warpage, high mold shrinkage and low 25°C flexural modulus showed a proportional relationship. While high Tg demonstrated some effectiveness for unit warpage, clear correlation was not established. This investigation developed a "molding stress index" which is calculated by integrating the storage modulus and the coefficient of thermal expansion (CTE) multiplier over a temperature range from temperature (35 °C) to molding temperature (175 °C.) The results demonstrate that this parameter can be used to evaluate the changes in properties such as CTE, modulus and Tg in accordance with the change of temperature comprehensively. There is a tendency toward strip and unit warpage when the molding stress index is high. This study suggests that the molding stress index is an effective evaluation method to lower the unit warpage. This evaluation also confirmed that both lower strip and unit warpage for various substrates were realized with EMC having high mold shrinkage and low modulus at normal temperatures while maintaining a high molding stress index. In addition, further warpage reduction is possible by jointly optimizing the properties of EMC and substrate.

Feasibility study of alternative dicing technologies for collective die to wafer direct bonding combined with wafer to wafer direct bonded dies has been performed. Several dicing technologies such as blade dicing, laser grooving + plasma dicing, laser grooving + stealth dicing and laser grooving from backside were evaluated for this integration scheme. For the case of blade diced dies, the collective die to wafer direct bonding are not succeeded. This was due to particle interruption, caused by remaining particles from dicing. For the case of laser grooving + plasma dicing and laser grooving from backside, successful die to wafer direct bonding were observed. However, the die edge was not bonded for the case of laser grooving + stealth dicing. This was attributed to the occurrence of the laser recast caused during laser grooving. Based on the characterization of dicing techniques for this approach, we have achieved successful integration of collective die to wafer bonding combined with wafer to wafer bonded dies.

As an important biometric technique, fingerprint verification is widely used for smartphone, IoT and payment due to the small size and high security. To meet full screen trend of smartphone, optical finger print sensor (FPS) using CIS aroused great interest and gradually replaced capacitive FPS. For such a device, a thin package size with better image performance is required. To meet these critical requirements, 3D wafer-level chip scale package (WLCSP) with via last TSV (through silicon via) was the best solution for CIS. In this paper, 3D WLCSP for FPS based on CIS with via last TSV interconnects was developed. For the optical FPS, the package size is 920×656µm with 580µm height, which includes 200µm thick glass, ~100µm thick optical layer, ~100µm thick CIS chip and BGAs of 80µm height. Electrical interconnections are implemented by via last TSVs, where big silicon trenches were formed on the backside of the two-row pads on the adjacent chips, then followed small TSVs were etched to contact with the pads of the backside. Dry etch was used to remove the oxide of the pads and PVD, electroplating and electroless plating were used to form redistribution layer (RDL). The light reflection and scattering at the sidewalls of the CIS chip and optical layer will affect the sensor performance greatly. Therefore, the coating of black materials on the sidewalls was developed to improve the performance of the optical FPS for high-end applications. The precut on dicing street was used to form the deep trench on CIS wafer and optical layer for black shielding. To form a void-free filling, the wetting property of the black glue is very important. Three different materials with required optical shielding properties were used. The process of dispensing of black glue into the trenches was developed. The droplet diameter of 50µm with a jetting speed of 70mm/s was used for black material filling. The results showed that one of the materials with 15µm thickness on the sidewalls with 99.9% optical shielding from 430-560nm light wavelength and void-free filling was obtained which is good enough for the application. Reliability of the 3D WLCSP with black shielding was characterized by thermal cycling (TC) and highly accelerated stress test temperature storage (HAST) tests and the results show good package level reliability. The results indicate that the 3D WLCSP can provide a low cost and reliable solution for optical FPS.

Hierarchical, self-assembled structures are ordered on multiple scales, and formed by objects comprised of even smaller elements. Such structures are widely reported for nanoparticles, macromolecules, and peptides, and even in entropy-driven hard particle assembly hierarchical colloidal crystals have been reported. Here we consider the hierarchical self-assembly of a cubic colloidal crystal from congruent hard cube derivatives, and investigate how various ways of slicing and dicing a cube can affect the ability of the pieces to entropically re-assemble the initial colloidal crystal formed from perfect cubes. We present design rules that support heuristics reported for different systems, and present evidence for a previously unreported cubatic phase from 2 : 1 rectangular prisms.

A surface channel waveguide (WG) laser is produced by diamond saw dicing of a 15 μm thick 10 at. % Tm:KY1-x-yGdxLuy(WO4)2 monoclinic double tungstate thin film grown by liquid phase epitaxy on an undoped KY(WO4)2 substrate. The WG propagation losses are 1.1±0.5 dB/cm. When pumped at 802 nm, laser operation is achieved with a maximum output power of 262 mW at 1833 nm with a record slope efficiency of 82.6% (versus the absorbed pump power) in a TE10 spatial mode (linear laser polarization, E‖Nm). Diamond saw dicing of double tungstate epitaxies is a promising technology for manufacturing WGs for sensing applications.

In this study, a sandwich structure (silicon/polymer/silicon) was prepared to demonstrate the adhesion strength between polymer and silicon layers using a four-point bending system. For the first time, the stealth dicing (SD) method was applied to the silicon layer to generate an initial crack, and the SD method was compared with the traditional method of forming a trench by blade dicing. From the experimental results, the SD method improved the test yield and showed a lower level of sudden force drop. As a result, SD is a highly reliable way to measure the adhesion strength using a four-point bending system.

We report on a miniature all-fiber dual parameter sensor capable of simultaneous measurement of the refractive index (RI) and temperature of fluids and gases. The high-sensitivity sensing element is comprised of two Fabry–Perot (FP) micro-resonators fabricated in a single-mode fiber and has a total length of

Modern high-tech MEMS manufacturing is not able to function without developed system of quality monitoring. Wellmanaged quality monitoring system enables to predict production risks and minimize them effectively. We devoted our research to such quality measurement tool as monitoring of product’s geometrical parameters between different MEMS manufacturing stages. This paper presents an example of automated approach to the analysis of optical images with the aim to control critical dimensions (CD) of MEMS products. For the purpose of CD monitoring, the special software has been developed. It executes several algorithms, such as image segmentation and Deriche edge detection, which allow to process one or several of images in a resource-saving manner. These algorithms were tested on both the interprocess control of critical dimensions and the control of kerf width and chipping after dicing technological process. As the result of their applying, huge-sized images (2 GB) are being processed in time less than 2 minutes and full optical inspection takes less than 10 minutes per wafer.

Nowadays, conventional glass processing techniques, such as “score and brake” method, are being replaced by laser-based techniques. Precision, speed and quality makes laser glass processing a very attractive technique for industry. However, new laser-based techniques have to be validated in respect to conventional processing. For this we introduce comparative investigation of free glass processing techniques – rear side laser cutting, laser-based and mechanical dicing. Local weakening of the material and mechanical separation is a highly efficient two-step glass cutting approach. Material modification can be introduced by laser or mechanically. However, when complex shape cutting is required rear side laser cutting can offer much more flexibility. Glass is a brittle material, therefore generation of micro-cracks during processing is inevitable. Such side-effects can influence processed surface quality and material flexural strength. Rear side glass cutting experiments were carried out by tightly focusing the laser beam on the sample back-surface. Nanosecond laser pulses with wavelength of 532nm were used. In the case of laser glass dicing process, Bessel beam was introduced to form elongated modifications in glass. High pulse energy sub-nanosecond laser at 1064 nm wavelength was introduced. For mechanical processing, the conventional “score and break” method was used without any additional post processing. In all cases surface chipping was introduced. There was no significant difference in terms of micro-crack size for rear side cutting and mechanical dicing techniques. However, sample resistance to mechanical load was higher for mechanical processing. In this work, in-depth investigation of these effects will be introduced.

We report on the fabrication and characterization of Er:YGG films suitable for waveguide amplifiers that could in principle be used in integrated path differential absorption lidar systems. Presented is our fabrication technique, comprising pulsed-laser-deposition growth of ~10 μm-thick crystalline films, their channeling via ultraprecision ductile dicing with a diamond-blade, producing optical quality facets and sidewalls, and amplifier performance. Net gain at 1572 nm and 1651 nm is obtained for the first time in Er-doped YGG waveguide amplifiers. Additionally, in a channel waveguide a maximum internal gain of 3.5 dB/cm at the 1533 nm peak was realized. Recent crystal film quality improvements promise further performance enhancements needed for the intended application for high-peak power sources in the 1.6-μm spectral region targeting Earth observation systems for monitoring greenhouse gases.

Bessel beams are invariant solutions to the Helmoltz equation that can also propagate, with finite pulse energy at high intensity, in a quasi-invariant regime in transparent dielectrics. Homogeneous energy is deposited along a line focus by infrared ultrashort pulses. If the cone angle is sufficiently high, the laser-deposited energy density is enough to open nanochannels in glasses or sapphire with a single laser pulse. This has found applications in the field of glass cutting via the technique of "stealth dicing". Here we address two important challenges in this field. First, high quality Bessel beams are essential for controlled energy deposition. Second, the maximal angle used up to here for channel drilling was 26° for 800 nm laser central wavelength. This enabled the formation of channels with diameters down to typically 300 nm in glass and sapphire. It is questionable if higher cone angles could also produce channels with potentially smaller diameters. Here, we generate high quality Bessel-Gauss beams with a setup based on reflective, off-axis axicons. The Bessel zone exceeds 100 µm for cone angles up to 35 degrees. This corresponds to central spot diameter down to 0.5 µm FWHM. We qualified these beams with a 100 fs laser source centered at 800 nm wavelength. We report nanochannel drilling down to typically 100 nm over at least 30 µm length in glass. Our approach opens novel perspectives for high quality Bessel beam generation but also for the highly confined laser-matter interaction for high precision processing of transparent dielectrics.

Laser grooving is a powerful method widely used in the semiconductor industry for chip singulation because of the advantages it provides, such as high grooves profile quality, lower mechanical stresses on devices. Nevertheless, challenges related to unexpected drawbacks on process such as efficiency, quality and reliability still remain. In order to maximize control of this critical process and reduce its undesirable effects, numerical models of nano-second laser pulsed and multistack material interaction have been developed. The modeling strategy using finite elements formalism is based on the convergence of two approaches, numerical and experimental characterizations. To evaluate this interaction, several laser grooved of multilayer samples Cu/SiO2, Al/SiO2, and complete state of the art back-end-of-line (BEOL) material stack were correlated with finite elements modeling. Three different aspects were studied; phase change, thermo-mechanical sensitive parameters as well as optical sensitive parameters. The mathematical model makes it possible to highlight a groove profile (depth, width, etc.) of a single pulse or multi-pulses on BEOL wafer material. Moreover, the heat-affected zone (HAZ) has been predicted as a function of laser operating parameters (power, frequency, spot size, defocus, speed, etc.). After modeling validation and calibration, a satisfying correlation between experiment and modeling results has been observed in terms of groove depth, width and HAZ.

In order to better understand the initiation of crack defects and predict the thermo-mechanical failure of underfill in microelectronic packages, a confocal microscopy-based digital image correlation (confocal-DIC) method was developed to measure the underfill local strain directly. A special underfill, consisting of transparent epoxy with Al 2 O 3 particle fillers, was applied to meet the requirement of confocal imaging inside the resin. A preliminary validation was accomplished on two samples with a simple structure: (a) non-constrained sample for isotropic dilatation and (b) a thin-layer sample for strain gradients in the resin on a glass substrate. Results from both samples were in good agreement with the calculation from the coefficient of thermal expansion (CTE) or the numerical simulation from finite element method (FEM). Furthermore, we applied this technique to measure the strain distribution in the underfill at the chip corner area when the assembly was under thermal loading at 60 °C. The results showed that the maximum strain value appeared exactly at the chip corner area, which is consistent to the simulation results. The measured maximum first principle strain reached around 0.9 %, while the strain on the sidewalls was approximately 0.5 %. Due to the imperfections of the real corner resulting from dicing effects, the measured strain at the corner was lower than the FEM result. In general, the good agreement between measurements and calculations demonstrates the accuracy of our methodology for measuring the underfill local strain in microelectronic packaging assemblies.

It is a main stream for 3-dimensional (3D) NAND flash which has the advantage of large storage capacity, excellent and reliable performance. Several different wafer architectures for 3D NAND flash including BICS (Bit Cost Scalable), TACT (Terabit Cell Array Transistor) and VG (Vertical Gate) etc. are all in mass production mode in current market. These new 3D NAND flash technologies are able to stack flash cells vertically in 32, 64, 96 layers or even more layers compared with 2D flash whose metallization layer is only single one. Therefore, the memory capacity in a 3D flash chip with these technologies can be increased dramatically to double, quadruple or more times than 2D flash one. However, more metallization layers on a wafer means more process stress to be introduced to the wafer itself. Thus, it will be a big challenge for wafer thinning and separation in IC assembly process later. This paper gives an overview of several different wafer thinning and separation technologies in IC packaging process. Potential process constraint or limitations, including die strength, side wall and sub-surface condition, are studied and associated with their wafer processes.

This paper describes the fabrication of silicon neural probes based on low-cost semiconductor technologies, such as photolithography, thin-films deposition and blade dicing. Each 8 mm long fabricated neural probe has 13 platinum recording sites (microelectrodes) with different dimensions, ranging from 50 × 50 μm2 to 300 × 300 μm2. The platinum microelectrodes impedance were characterized through electrochemical impedance spectroscopy with results ranging from 5 kΩ to 600 kΩ at 1 kHz. Local field potentials were recorded when performing in-vivo electrophysiological recordings on an adult mouse. The results demonstrate the functionality of the neural probe, by acquiring local field potentials activity even with a microelectrode area of 50 × 50 μm2. Moreover, the results suggest a robust and versatile fabrication process avoiding etching processes.

Nanoindentation is usually used to investigate local elastic properties and hardness of materials. In this paper, the nanoindenter served as a loading tool to perform micro scale bending tests and measure the global response of micro-scale specimens. For testing, cement paste cantilever beams with a square cross-section of 300 μm × 300 μm were fabricated using a micro dicing saw. Monotonic, cyclic and sustained loading bending tests were conducted on the beams using the nanoindenter. The load-deflection behaviours of micro-cantilever beams subjected to various loading conditions are presented in this paper. The interpretation of experimental results regarding the measured deflection of beam is discussed. With this micro-scale test method, the fracture strength as well as time-dependent responses of cement paste at the micrometre level can be assessed in a straightforward manner.

We report on the development of an ultrafast beam shaper capable of generating Bessel beams of high cone angle that maintain a high-intensity hot spot with subwavelength diameter over a propagation distance in excess of 8~mm. This generates a high-intensity focal region with extremely high aspect ratio exceeding 10~000:1. The absence of intermediate focusing in the shaper allows for shaping very high energies, up to Joule levels. We demonstrate proof of principle application of the Bessel beam shaper for stealth dicing of thick glass, up to 1~cm. We expect this high energy Bessel beam shaper will have applications in several areas of high intensity laser physics., Comment: 3 figures

The highly complex technology requirements of today's integrated circuits (ICs), lead to the increasingly use of several materials types such as metal structures, brittle dielectrics, porous low-k and ultra-low-k materials which are used in both front-end-of-line (FEOL) and back-end-of-line (BEOL) process for wafer manufacturing. In order to singulate chips from wafers, a critical laser-grooving process, prior to blade dicing, is used to remove these layers of materials out of the dicing street. The combination of laser-grooving and blade dicing allows to reduce the potential risk of induced mechanical defects such micro-cracks, chipping, on the wafer top surface where circuitry is located. Nevertheless, challenges related to unexpected drawbacks on process such as efficiency, quality and reliability still remain. To maximize control of this critical process and reduce its undesirable effects, numerical models of nano-second laser pulsed and multi-stack material interaction have been developed. The modeling strategy using finite elements formalism is based on the convergence of two approaches, numerical and experimental Validation. To evaluate this interaction, several laser grooved samples were performed using IBM 14 nm technology node wafer and were correlated with finite elements modeling. Three different aspects were studied; phase change, thermo-mechanical and optical sensitive parameters. The numerical model makes it possible to simulate groove profile (depth, width, etc.) of a single pulse or multi-pulses on BEOL wafer material. Moreover, the heat-affected zone (HAZ) has been estimated as a function of laser operating parameters (power, frequency, spot size, defocus, speed, etc.). After modeling validation and calibration, a reasonable agreement between experiment and modeling results has been observed in terms of groove depth, width and HAZ

This paper underlines the damages induced by probing on narrow pads reliability of specifically designed test structures placed on dicing streets and indicates that probing during electrical test steps provokes detrimental cracks diving from the passivation through the BEOL layers providing a path for moisture ingress.

Photoresist coating and patterning are the most repeated process steps in advanced packaging. Spin coating is still the prevalent method of coating planar surfaces and the patterning of thin films. However thick resist processing [1] and spray coating [2] are nowadays well established and commonly used for advanced patterning requirements. Thick resist processing is widely used for plating of interconnects [3] or LIGA fabrication. Spray coating is mainly used to efficiently protect or pattern severe topography and an essential process for packaging, plasma dicing, and MEMS.