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This paper presents a K-band FMCW radar transceiver IC, which is integrated in 0.13-μm CMOS technology. In the transmitter part, the class-C topology is adopted in the VCO block to achieve good phase noise performance. In the receiver part, the high gain of the LNA sufficiently suppresses the noise of the next stages to achieve a good noise figure in the receiver and the linearity of the receiver was improved by adoption of a gain control block, thereby achieving a wide dynamic range. As a result, a conversion gain of 35.7 dB, a P1dB of −12.7 dBm, and a DSB noise figure of 5.5 dB are achieved in the receiver part. The tuning range of 23.8∼24.5 GHz and the phase noise of −103.1 dBc/Hz @ 1MHz offset are achieved in the transmitter part. The transceiver chip consumes 181.5 mW from a 1.5 V power supply. Using this chip, the K-band FMCW radar module is implemented and verified by measurement of the distance of an object.

The 26 GHz and 79 GHz UWB frequency bands are used for short-range radar applications for automobile. In this paper, single chip front-end ICs for both frequency bands are presented. The pulsed oscillator at 26 GHz can produce UWB short pulses. It consumes power only during short duty cycles; thus, it allows a power-efficient radar. A stereo radar, which comprises two synchronized radars, is demonstrated with the ICs. Hybrid beam forming techniques based on base-band delay are also demonstrated. The pulsed front-end architecture of the proposed 79 GHz UWB pulse radar is discussed, which is expected to reduce power consumption. The performance of some circuit elements is also reported.

In this paper, a 79 GHz g m -boosted sub-harmonic mixer with high conversion gain is presented. As a g m -boosting technique, a transformer based feedback network with an NMOS bleeding path is proposed to achieve high conversion gain. The differential LO-driven sub-harmonic mixer has a simple structure and operates at low LO power. The measurement results show a conversion gain of 1.6 dB at a LO power of −5 dBm, a noise figure of 13 dB, and a 2LO-to-RF isolation of 38 dB. The power consumption of the sub-harmonic mixer is 12 mW. The circuit was fabricated using 65-nm CMOS technology with a chip area of 0.69×0.45 mm2.

Current–voltage and low frequency excess electrical noise characteristics of two different—Schottky diode and n-i-n diode—GaAs structures embedded with self-assembled In(Ga)As quantum dots are reported. We find the growth of quantum dots induces defects not only near the quantum dot but also extended to quite a distance toward the growth direction. In Schottky diode structure, comparing with the reference sample without the quantum dot layer, the current dependence of the low frequency noise spectral density indicated that the noise is from the generated interface states with the density increasing towards the band tail. Also the crystal quality of the Schottky diode including the quantum dot layer, deduced from the Hooge parameter, was slightly worse than that of the reference sample. For n-i-n diode structure, the current–voltage relation was linear, and a quadratic current dependence of the noise spectral density was observed. The Hooge parameter for the n-i-n structure was determined to be on the order of unity indicating the general degradation of the structure.

The purpose of this study is to investigate the effects of electrical stress on the 1/ f noise behavior in n-channel metal–oxide–semiconductor transistors with ultrathin gate oxides. Even under a weak electrical stress, the drain current noise (Sid) of the device with a 1.4-nm-thick oxide was found to increase abruptly beyond a certain critical gate bias. This deteriorated noise property was proven to be from simultaneous increases in gate current noise (Sig) and the correlation between Sid and Sig, which were directly related to oxide trap generation and gate/drain current (Ig/Id) ratio, respectively. Meanwhile, the increase in Sid in the device with a 2.3-nm-thick oxide after stress, with a comparable transconductance degradation, was relatively insignificant because of the device's smaller Ig/Id ratio, even if the measured Sig was comparable to that of the thinner oxide device. Consequently, the 1/ f noise degradation could be much more significant than the accompanying DC characteristic degradations in the thin gate oxide below 1.5 nm.

We report some comparative results on the normal-incidence device characteristics accomplished with a couple of self-assembled InAs/GaAs quantum-dot infrared photodetectors (QDIPs) doped in InAs QDs and GaAs barriers. The peak values of responsivity and detectivity for the barrier-doped device are 650 mA/W and 3.2 × 108 cm Hz1/2/W (18 K) at λp ≅ 5 μm, respectively, which are approximately two and ten times higher than those for the QD-doped one. In addition, while there is no spectral response over 6 μm in the QD-doped structure, a strong photoresponse is extended up to around 10 μm in the barrier-doped one. Although the direct doping in InAs QDs is effective for blocking the dark current, the doping in GaAs barriers has better device performance of QDIP.

This work was supported by the Engineering Research Center (ERC) program of the government of Korea.

A 1.9-GHz CMOS differential power amplifier for polar transmitter applications was implemented with a 0.25 μm RF CMOS process. All of the matching components, input transformer, and output transformer are fully integrated with 50 Ω input and output matching. Each power transistor in each differential branch is split again and controlled separately to obtain a high power mode and a low power mode. The amplifier achieved a drain efficiency of 32% at the maximum output power of 29.5 dBm. The dynamic range is measured at approximately 27.5 dB with a supply voltage range of 0.7 ∼ 3.3 V. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 2053–2056, 2006; Published online in Wiley Inter-Science (www.interscience.wiley.com). DOI 10.1002/mop.21854

A digital 5-bit phase shifter at Ku-band is presented, which is implemented with 0.18-mum RFCMOS technology. n-MOSFET switches and top metal microstrip lines with a first-metal ground allow the phase shifter to have small insertion losses. The proposed 90deg phase shifter utilizing a parallel resonator exhibits broad-band characteristics. All of the circuit components are derived to obtain a minimum phase variation at the operation frequency band. A bridged-T type phase shifter is also analyzed in view of parallel resonance using an ideal equivalent-circuit model. The conditions of the circuit elements are derived in an analytic form, which are used to obtain the broad-band phase characteristics. The fabricated 5-bit phase shifter demonstrates an overall rms phase error less than 12deg from 9 to 15 GHz. Insertion losses of 14.5 dB plusmn 0.5 dB and return losses less than 14 dB are obtained for 32 states at 12 GHz. The proposed 90deg phase shifter has performed a phase shift of 92.3degplusmn3.2deg over 9-15 GHz

Fully integrated 10-, 20-, and 40-GHz frequency sources are presented, which are implemented with a 0.18-/spl mu/m CMOS process. A 10-GHz quadrature voltage-controlled oscillator (QVCO) is designed to have output with a low dc level, which can be effectively followed by a frequency multiplier. The proposed multipliers generate signals of 20 and 40 GHz using the harmonics of the QVCO. To have more harmonic power, a frequency doubler with pinchoff clipping is used without any buffers or dc-level shifters. The QVCO has a low phase noise of -118.67 dBc/Hz at a 1-MHz offset frequency with a 1.8-V power supply. The transistor size effect on phase noise is investigated. The frequency doubler has a low phase noise of -111.67 dBc/Hz at a 1-MHz offset frequency is measured, which is 7 dB higher than a phase noise of the QVCO. The doubler can be tuned between 19.8-22 GHz and the output is -6.83 dBm. A fourth-order frequency multiplier, which is used to obtain 40-GHz outputs, shows a phase noise of -102.0 dBc/Hz at 1-MHz offset frequency with the output power of -18.0 dBm. A large tuning range of 39.3-43.67 GHz (10%) is observed.

Presented is a digital-RF transmitter using multi-bit ΔΣ modulators with noise-shaped segmentation and butterfly shufflers for shaping mismatches between digital-to-RF converter (DRFC) cells. The segmented butterfly shufflers prevent mismatch errors of DRFCs from aggravating the linearity and the LO leakage of the transmitter. A prototype based on a digitally-intensive top-down design is fabricated in 90 nm CMOS process. Measurement results for wideband-code division multiple access demonstrate an adjacent channel leakage ratio (ACLR) (5 MHz/10 MHz) of -49.6 dBc/-53.9 dBc and an Error Vector Magnitude of 1.89% with a main channel output power of -0.1 dBm centred at 1.95 GHz.

Balanced and differential voltage controlled oscillators (VCOs) are investigated with analytic noise models. Fully integrated VCOs in Ku-band are implemented on an InGaP-GaAs heterojunction bipolar transistor technology. The balanced VCO has higher output power and lower phase-noise performance, while drawing lower current than the differential VCO. This coincides with the analytical expectation. The shot noise of collector current contributes less to the phase noise in the balanced VCO (B-VCO) than in the differential VCO. The B-VCO shows 2-3 dB lower phase-noise performances of 90.5, -113.8dBc/Hz at the offset frequencies 100 kHz, and 1-MHz offset at 13.5 GHz than the differential VCO, and figures of merit of 180.7 and -177.6dBc/Hz are achieved, respectively.

As a boron diffusion barrier, a 20 nm-thick Si0.8Ge0.2 layer was successfully utilized in n-channel MOSFETs for implementing a retrograded well structure. Compared with the conventional Si CMOS process, the developed n-channel MOSFET process provides an enhanced transconductance (7%) and lower sub-threshold swing which is nearly unchanged even at an increased drain-source voltage. Especially, because sub-threshold leakage current is one of the key issues in the MOS device scaling due to reduced threshold voltage, the usage of a Si0.8Ge0.2 layer in n-channel MOSFET was verified to be useful for low power and high performance even under aggressive scaling constraints.

The asymmetry between lower and upper intermodulation distortions (IMD) in a heterojunction bipolar transistor (HBT), which can be observed under certain baseband termination and bias conditions, is analyzed using a large-signal model. This approach enables harmonic balance analysis of IMD asymmetry in nonlinear circuits using HBTs and, therefore, overcomes the limitations of the conventional Volterra-series analysis. Closed-form expression derived from Volterra analysis is also employed to present comparisons with the large-signal model approach. Measurements indicate that the asymmetry is very sensitive to baseband termination, which varies with the envelope frequency of the input RF signal. Specifically, zero crossings of asymmetry are observed at each resonance frequency where the reactive part of baseband termination changes its sign rapidly. It is also found that the asymmetry is enhanced at a specific small bias current where the dominance of the 3rd order nonlinearity is greatly reduced by cancellation with the 2nd order nonlinearity. The bias condition for asymmetry occurrence is calculated, using a simple analytical equation, to be related to measurement data. All the measurements are verified successfully by nonlinear simulation using large-signal model. Finally, the advantage of the large-signal model approach compared to Volterra analysis for asymmetry prediction is discussed.

We present fully integrated high-performance voltage-controlled oscillators (VCOs) with on-chip microelectromechanical system (MEMS) inductors for the first time. MEMS inductors have been realized from the unique CMOS-compatible MEMS process that we have developed to provide suspended thick metal structures for high-quality (Q) factors. Fully integrated CMOS VCOs have been fabricated by monolithically integrating these MEMS inductors on the top of the CMOS active circuits realized by the TSMC 0.18-/spl mu/m mixed-mode CMOS process. Low phase noise has been achieved as -124 and -117 dBc/Hz at 300-kHz offset from carrier frequencies of 1 and 2.6 GHz, respectively, in the fabricated single-chip VCOs.

A large-signal modeling of power heterojunction bipolar transistor (HBT) is demonstrated for an accurate simulation of self-heating and ambient temperature effects and nonlinear behaviors such as output power, gain expansion, intermodulation distortion (IMD), and adjacent channel power ratio (ACPR). The physical relationship between the device current and the rate of change in the built-in potential with respect to the device temperature has been utilized for a fully electrothermal modeling. To enable an immediate use for a circuit design, the model extraction was done for in-situ output-stage device from two-stage power amplifier (PA) circuit. In each parameter extraction step, measurement data obtained under a consistent environment, which are current-voltage (I-V) at various temperatures and small-signal S-parameters under various bias conditions, have been carefully examined and utilized to relate the meaning of each parameter to the physical principle of the device. Measurements and simulations are compared for the verification of the model under dc condition at various temperatures.

A spline large-signal FET model is presented. This includes a quiescent bias dependency to predict nonlinear dynamic behavior of FETs in which self-heating and trap effects are present. The intrinsic device of the model represented by a parallel connection of current and charge sources and the model parameters are extracted from bias-dependent pulsed I-Vs and S-parameters, respectively. The validity of the model is demonstrated by comparing the simulated small-signal S-parameters over a wide bias range with measured data. Nonlinear behaviors of FETs such as P/sub in/ - P/sub out/, third-order intermodulation distortion, and efficiency are also compared.

Long wavelength infrared absorption characteristics of an In0.3Ga0.7As/GaAs quantum well infrared photodetector (QWIP) employing an n-i-p-i-n camel diode structure were compared with those of a conventional n-QWIP. The QWIPs showed a photocurrent response peak at the wavelength of approximately 10 μm due to electronic intersubband transitions in quantum wells. The QWIP employing the camel diode structure showed a reduced dark current, an increased responsivity, and thus an improved detectivity compared with those of the conventional n-QWIP due to the presence of the n-i-p-i-n camel barrier. The results indicated the potential of the QWIP employing an n-i-p-i-n camel diode structure for use in infrared detectors operating at elevated operating temperature.

This paper presents CMOS front-end ICs with 13.3 dBm output power for K-band FMCW radar, which is integrated in 0.13-μm CMOS technology. The transmitter consists of a voltage controlled oscillator, divider chain, power amplifier, and additional buffers. The receiver consists of a low-noise amplifier, IQ mixers, an IQ generator, and buffers. The leakage problem can be mitigated by adopting differential topology and ground shielding. As a result, the receiver achieves a conversion gain of 35.7 dB, a P1dB of -31.6 dBm, and a DSB noise figure of 5.5 dB. The transmitter achieves the tuning range of 23.8~24.5 GHz and the phase noise of -104 dBc/Hz @ 1MHz offset. The receiver and transmitter chips consume 121.5 mW and 373.5 mW from a 1.5 V power supply, respectively. Using these two chips, the K-band FMCW radar module is implemented and verified by measuring the distance of an object.

We have designed and fabricated a quantum dot infrared photodetector which utilizes the lateral transport of photoexcited carriers in the AlGaAs/GaAs two-dimensional (2D) channels. A photocurrent signal has been observed in the range of 9.5-11 pm with a peak at 10.5 μm due to the bound-to-continuum intersubband absorption of the normal incidence radiation in the self-assembled InAs quantum dots. The peak detectivity was measured to be 1 x 10 9 cm Hz 1 2 / W at 220 K. The high detectivity is realized mainly by low dark current, high mobility and a long lifetime of photoexcited carriers in the modulation doped 2D channels.

A InGaP/GaAs heterojunction bipolar transistor structure is proposed in which the base epi-layer underneath the extended ledge works as a base ballast resistor. The structure eliminates the critical alignment for a passivation ledge formation as well as additional process steps for external base ballast resistors. Both ballasted and unballasted devices were fabricated and compared. A small signal equivalent circuit gives us the magnitude of the effective ballast resistance. The thermal characteristics, including gain-collapsed I-V and V/sub be/ regression curve are shown and modeled. The temperature dependency of base sheet resistance and its influence on the device performance are also discussed.

This letter presents an injection-locked CMOS power amplifier for pulse width modulation (PWM) digitized polar transmitter. A power oscillator combined with injection-locking technique reduces the required driving power and provide high drain efficiency in the power stage. The switched power oscillator is proposed for PWM digitized polar transmitter. To achieve differential to single output and impedance transformation, a lumped element balun, employing a minimum number of discrete components, is used. The power amplifier achieved a power-added efficiency of 70.7% at a maximum output power of 29.05 dBm. The measured drain efficiency in the power stage was 72.7% at 820 MHz. The chip is implemented with a 0.18 μm CMOS process. The total chip size is 0.48 mm2.

A CMOS power amplifier (PA) for a UHF (860-960 MHz) stationary RFID reader is presented. To design a high power and power efficient CMOS PA, quasi four pair structure and integrated passive device (IPD) transformers are used. An amplitude modulation is performed through the cascode gate with a pulse shaping filter. The chips are fabricated in a 0.18 ?m CMOS process and IPD. Measurements show output power of 32.8-33.37 dBm and the power added efficiency (PAE) of 51.8-56.1% with the supply voltage 3.0 V.

An ultrawideband common-gate low noise amplifier with tunable interference rejection is presented. The proposed LNA embeds a tunable active notch filter to eliminate interferer at 5-GHz WLAN and employs a common-gate input stage and dual-resonant loads for wideband implementation. This LNA has been fabricated in a 0.18-?m CMOS process. The measured maximum power gain is 13.2 dB and noise figure is 4.5-6.2 dB with bandwidth of 3.1-10.6 GHz. The interferer rejection is 8.2 dB compared to the maximum gain and 7.6 dB noise figure at 5.2 GHz , respectively. The measured input P1dB is -11 dBm at 10.3 GHz. It consumes 12.8 mA from 1.8-V supply voltage.

A predistortion linearization method using an envelope-feedback technique is proposed and implemented in this paper. This linearizer compensates the gain and phase nonlinearity of power amplifier (PA) simultaneously by controlling both variable attenuator and phase shifter with the feedback of only the difference signal between input and output envelopes. A new carrier cancellation scheme composed of a minimization circuit, log detector, and vector modulator is also presented. This circuit achieves adaptive control of the linearizer by enabling direct measurement of out-of-band power. It is well suited to a multichannel system where the allocated channels are time variant. The principle of the proposed linearizer is described and simple AM-AM distortion analysis is presented analytically and graphically based on the conceptual schematic diagram. A two-tone test for a class-A PA at 1.855 GHz with frequency spacing of 1 MHz showed intermodulation-distortion reduction of maximum 16 dB and stable operation over 5-dB output power variation up to 4-dB backoff from the saturation power level. The proposed linearizer is also applicable to class-AB PA's without further special adjustments. The adaptation circuit is fully implemented with analog integrated circuits, which can further extend its applicability with the integration technology.

This work is partially supported by the Ministry of Information and Communication and by the Korea Science and Engineering Foundation under the contract OERC- 1997G0202. The authors would like to thank Mr. E. Park and J. Park for their help in device fabrication.

A fully integrated CMOS power amplifier for 5 GHz WLAN applications is implemented using 0.18 μm CMOS technology. An on-chip transmission-line transformer is used for output matching and voltage combining. An input balun, interstage matching components, an output transmission-line transformer, and RF chokes are fully integrated in the amplifier, and thus no external components are required. The power amplifier occupies a total area of 1.7 mm × 1.2 mm. At a 3.3 V supply voltage, the amplifier exhibits a 22.6 dBm output 1 dB compression point, 23.8 dBm saturated output power, and 25 dB power gain. The power added efficiency (PAE) is 21% at maximum, 19% at P1dB. When a 54 Mbps/64 QAM OFDM signal is applied, the PA delivers an average power of 12 dBm at an EVM of −25 dB. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2551–2553, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24683

This article presents the design of a 6-bit phase shifter in a 0.18-μm CMOS technology for X-band phased array radar application. Meandered microstrip lines and compact circuit designs techniques yield a chip with 1.9 mm2 die area. The fabricated phase shifter demonstrates a typical 15.7 ± 1.1 dB insertion loss and a 4° rms phase shift error at 9.5 GHz. To the author's knowledge, this is the first demonstration of a 6-bit phase shifter using CMOS switches with the lowest die area among reciprocal digital phase shifters at X-band. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2404–2406, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24663

A power up-mixer is proposed in this letter. A merged CMOS linear power amplifier (PA) and mixer allows low current consumption and smaller chip size than a conventional integrated transmitter including a mixer and a CMOS linear PA. The chip is fabricated in a 0.18 mum CMOS process and in an integrated-passive-device. Measurements show a drain efficiency of 27% at 27.2 dBm of 1 dB compression point (P1dB) output power from 1.75 to 1.95 GHz. Power conversion gain is 26.4 dB and LO leakage is -43 dBc.

A CMOS injection-locked frequency divider (ILFD) with high division ratios and high frequency operation is presented. It consists of a ring oscillator and injection capacitors. An input signal is directly injected through the capacitors into the feedback nodes of the ring oscillator. The proposed ILFD is fabricated in a 0.18 mum CMOS process and has a chip core size of 68 mum times 70 mum. It shows multiple division ratios of 3, 6, and 9. The operation frequency is from 2.2 to 30.95 GHz. At the maximum operation frequency, the ILFD has a locking range of 260 MHz with an input power of less than 0.25 dBm, a division ratio of 9, and a power consumption of 12.5 mW. The locking range increases up to 3.2 GHz as the division ratio and the operation frequency decrease.

A high gain CMOS down conversion mixer with a gain enhancement technique is presented. This technique includes negative resistance generation, parasitic capacitance cancellation and current-injection. These are implemented with an additional circuitry. This mixer has a conversion gain of 9.12 dB, input 1 dB compression point of -11 dBm at 24 GHz, while consuming 16.2 mW from 1.8 V supply. Between 22 and 26 GHz, the LO-to-RF and RF-to-LO isolations are better than 35 dB and 26 dB, respectively.

A K-band voltage controlled delay line based on a left-handed transmission line (LHTL) with cascaded metal-oxide-semiconductor (MOS) varactors and shunt inductors using CMOS technology is demonstrated for the first time. A variable time delay can be obtained by changing the capacitance of MOS varactors without any power consumption. The figure of merit is 10.9deg/dB at 18 GHz. This result is better than other variable LHTL in similar frequency band. A time delay ranging from 56.8 ps to 76.4 ps is achieved at 18 GHz. It allows about 30 times longer time delay than that of a traditional right-handed one with the same length. The chip size, including the pads, is 410 mum times 640 mum.

A CMOS radio frequency (RF) polar transmitter architecture for a UHF (860-960 MHz) RF identification (RFID) reader is proposed, which consists of a switch-mode CMOS power amplifier (PA) and an analog pulse-shaping filter implemented in 0.25-mum CMOS process. The amplitude modulation of a amplitude shift keying signal is performed by simply switching the common gate transistor of a cascode power amplifier. Extremely low power consumption is achieved when the PA is switched off. The power efficiency of the transmitter is enhanced not only by using switching power amplifier but also by employing this architecture.

A fully integrated complementary metal oxide semiconductor (CMOS) cascode LC voltage controlled oscillator (VCO) with Q-enhancement technique has been designed for high frequency and low phase noise. The symmetrical cascode architecture is implemented with negative conductance circuit for improving phase noise performance in 0.18 mum CMOS technology. The measured phase noise is -110.8 dBc/Hz at the offset frequency of 1 MHz. The tuning range of 630 MHz is achieved with the control voltage from 0.6 to 1.4 V. The VCO draws 4.5 mA in a differential core circuit from 1.8 V supply.

An active balun with a single-ended input and a pair of differential outputs is presented for the input stages of differential circuits. The active balun, which is composed of an input resonator and cascaded common-gate amplifiers, was implemented using 0.18-mum CMOS technology and bond wire inductors. A body-source cross-coupled configuration was used to enhance the gain of the active balun. The gain is 9.3 dB at 1.8 GHz, and the phase and the amplitude error are less than 2deg and 1 dB, respectively, in the frequency range of 1 to 2 GHz, even for a P1dB of -2.7 dBm. The balun consumes 9 mA for 3-V supply voltage.

A calibration method is proposed for a range finder with a six-port phase frequency discriminator. Calibration equations are derived that include phase errors resulting from both the imperfections in a six-port network and the different diode characteristics. The equations allow a simple and accurate calibration of the range finder with the six-port network. Calibration parameters are calculated from dc outputs, which are measured as the output frequency is varied. The maximum error of a distance measurement from 0.5 to 3 m is ~ 2%.

In this letter, a two-stage 900-MHz CMOS differential power amplifier (PA) is designed and implemented in a 0.18-mum radio frequency CMOS process. A transmission line transformer on a printed circuit board is used as an output power combiner and matching circuits of a class-E power stage. To drive the power stage effectively, cascaded class-D amplifiers are used as driver amplifiers. The PA delivers an output power of 31.7dBm and a power-added efficiency of 62.4% with a power gain of 30.3dB, including the losses of the bond-wires and the output transformer

A 1.9-GHz CMOS power amplifier for polar transmitters was implemented with a 0.25-mum radio frequency CMOS process. All the matching components, including the input and output transformers, were fully integrated. The concepts of mode locking and adaptive load were applied in order to increase the efficiency and dynamic range of the amplifier. The amplifier achieved a drain efficiency of 33% at a maximum output power of 28dBm. The measured dynamic range was 34dB for a supply voltage that ranged from 0.7 to 3.3V. The measured improvement of the low power efficiency was 140% at an output power of 16dBm

A power-cell for RF power applications is designed using 0.35-μm standard CMOS technology. An interdigitated body contact method is proposed and applied to a RF power-cell. A total gate width of the designed power-cell is 3.2 mm. The proposed RF power-cell has a higher junction breakdown voltage than that of a conventional RF power-cell. The breakdown voltage of the proposed CMOS power-cell at zero gate voltage was found to be ∼8 V. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 3085–3087, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22908

A 2.4-GHz fully integrated CMOS receiver front-end using current-reused folded-cascode circuit scheme is presented. A configuration utilizing vertically stacked low-noise amplifier (LNA) and a folded-cascode mixer is proposed to improve both conversion gain and noise figure suitable for sub-mW receiver circuits. The proposed front-end achieves a conversion gain of 31.5dB and a noise figure of 11.8dB at 10MHz with 500-/spl mu/A bias current from a 1.0-V power supply. The conversion gain and noise figure improvements of the proposed front-end over a conventional merged LNA and single-balanced mixer are 11dB and 7.2dB at 10MHz, respectively, with the same power consumption of 500/spl mu/W.

A semi-empirical CAD model of ferroelectric capacitor for circuit simulation as well as for device characterization is proposed. The model can successfully describe the followings with only 5 parameters(Vc, Vo, Ps, Co, τ which have definite meanings. These are 1) hysteresis of charge vs. voltage (Q-V) relationship and capacitance vs. voltage (C-V) relationship, including partial polarization switching by minor voltage sweep. 2) characteristic time dependent polarization reversal (switching) current.

This paper describes a novel active inductor using a common-source cascode FET with an inductive feedback. A compact lossy active inductor, which consists of a common-source FET and a feedback resistor, was used as the feedback inductor to achieve high Q-factor and tunability, as well as reduce the chip size. The fabricated active inductor achieved more than 100 Q-factors with the maximum value of 3400 over the frequency range of 200 MHz, in the vicinity of 1.7 GHz. Inductance was tuned from 9.6 to 56 nH at 1.7 GHz by the variation of the feedback resistance of the lossy active inductor. Using this active inductor (as a frequency-selective element in the resonator), a monolithic inductance-controlled FET oscillator was fabricated, which demonstrated an 18% frequency-tuning range from 1.73 to 2.07 GHz, with an output power range from -9.3 to -6.3 dBm.

A simple Flash memory cell model for circuit simulation is presented. The proposed model gives an excellent fitting of dc and transient data and does not require additional simulation time comparing with that of a MOSFET transistor. Effective control-gate voltage method and ideal current-mirror technique are introduced to calculate floating-gate voltage. These allow macro modeling of a Flash memory cell in a circuit simulator.

A quantum-well infrared phototransistor with a pseudomorphic high-electron mobility transistor (pHEMT) structure is presented. The proposed phototransistor uses four periods of a GaAs/Al/sub 0.3/Ga/sub 0.7/As (50 /spl Aring//120 /spl Aring/) quantum-well absorption region, as well as an In/sub 0.15/Ga/sub 0.85/As quantum well conducting channel under the absorption layer. The phototransistor shows a large responsivity of 140 A/W around 6 /spl mu/m at 23 K (for a cutoff wavelength of 7.5 /spl mu/m). The relation between the photoconductive gain and the transconductance of the pHEMT structure is also investigated.

An X-band quadrature voltage-controlled oscillator (QVCO) is fabricated using 0.18-μm CMOS technology. The high impedance of a current source allows a highly effective Q-factor of the LC tank 1. The proposed X-band CMOS quadrature VCO has low phase noise of −117.5 dB/Hz at 1-MHz offset frequency, despite the absence of a current source, because a transformer can separate the gate bias of series-connected transistors from cross-coupled RF feedback. The VCO can operate under 1.8 V of power supply. The figure of merit (FOM) is 187.5 dB at a 10.3-GHz oscillation frequency, which is the best value among X-band VCOs. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 44: 305–307, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20618

Highly integrated front end module (FEM) with selectively anodized aluminum substrate was proposed and designed from 2.3 GHz to 2.5 GHz for WiMAX/Wibro applications. It consists of a MMIC power amplifier (PA), a MMIC SPDT switch, and a LPF with integrated passive device (IPD) on the substrate. The PA and the SPDT switch were designed with 2 μm GaAs HBT process and 0.5 μm InGaAs pHEMT process, respectively. The performance of the PA is comparable with commercial WiMAX products. The FEM has the gain of 30.3 dB and EVM of 2.6 % at 23 dBm FEM linear output power with the help of aluminum substrate's good thermal dissipation, and its compact size is 4 × 5 mm2.

A fully integrated dual-mode CMOS power amplifier (PA) with nonlinear MOS capacitance compensation is presented using 0.18-μm RF CMOS process. The proposed technique is used to implement dual mode structure as well as reduces AM-PM distortion. Dual-mode output matching network using transmission line transformer (TLT) is implemented for efficient dual mode operation. With a supply voltage 3.5V, the PA has the power gain of 26.2 and 14.2dB in low power mode (LPM) and high power mode (HPM), respectively. The quiescent current is only 28mA at LPM. The maximum linear output power satisfying 3GPP WCDMA modulated signal is 28/16.3dBm with a PAE 33.8/10.2% in the HPM/LPM.

A 77GHz CMOS 4-channels receiver, transmitter with 3-outputs and array antenna architecture is proposed for low cost/small size automotive radar system, and implemented by using 65nm CMOS and LTCC substrate respectively. Measured performance of CMOS transceiver, which included useful functions such as dual operation of long/short range detection, I/Q signal process and gain attenuation when near target detection, shows comparable performances to that of commercial SiGe chips. Especially, the transmitter consumes one third lower power compared to SiGe chips. These results confirm that it may be a promising candidate for low cost and small size car radar system.

A 77 GHz CMOS medium power amplifier (PA) with high efficient matching networks based on transformer is presented. The unit transistor size of a power cell is selected by analyzing its maximum available gain. The broadside-coupled Transmission-Line Transformers (TLTs) are implemented as matching networks for low insertion loss and wide band matching characteristics. The PA is fabricated using a 65-nm RF CMOS process. The saturated output power and the peak power-added efficiency at 76.5GHz is 12.8 dBm and 8%, respectively. The DC power consumption is 236 mW with a supply voltage of 2.0V.

This paper presents a CMOS RF programmable-gain driver amplifier (RF PGDA) for wireless transmitters. Digital-step differential attenuators precede a programmable-gain amplifier in order to enhance the dynamic range and to save power consumption, especially at low gain region. The RF PGDA fabricated in 0.13-μm CMOS technology with a 1.2 V supply voltage achieves a dynamic range of 49 dB with a step error of less than 0.5 dB and highly-linearized output satisfying the WCDMA/LTE specifications.