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In Nanomagnet Logic, an electronic read-out device converts magnetization to electronic signals. A giant magnetoresistance (GMR) stack, with simple deposition procedures, is a good candidate for this purpose. In this paper, the authors propose a way to pattern GMR films with the help of a CO2 snow-jet to simplify device fabrication procedures. A scanning electron microscope and a vibrating sample magnetometer were used to characterize the devices and verify the feasibility of the fabrication method. Results have shown that the CO2 snow-jet process can remove sidewalls of nanopillars that are formed after lift-off of sputtered films, and the nanopillars are uniform in shape and size. This method presents a new way to fabricate electronic readout devices for Nanomagnet Logic circuits. [ABSTRACT FROM AUTHOR]

We demonstrate that in circuits and systems that comprised of nanoscale magnets, magnet-shape-dependent switching properties can be used to perform Boolean logic. More specifically, by making magnets with slanted edges, we can shift the energy barrier of the device (i.e., so that it is not at a maximum when a device is magnetized along its geometrically hard axis). In clocked systems, we can leverage this barrier shift to make and or or gates that are not majority based. Advantages include reduced gate footprint and interconnect overhead as we eliminate one gate input. In this paper, we report and discuss micromagnetic simulations that illustrate how magnet shape can facilitate nonmajority-gate-based, reduced footprint logic; preliminary fabrication and testing results that illustrate that shape engineering can induce energy barrier shifts; and additional micromagnetic simulations that show other ways in which we might leverage shape in circuits made from nanoscale magnets. [ABSTRACT FROM PUBLISHER]

We present simulations of, and design alternatives for, an interface between nanomagnet logic (NML) and electrical circuitry. We propose using the fringing fields from a nanomagnet to help set the state of the free layer of a magnetic tunnel junction (MTJ). Our first magnetic–electrical interface design (MEI-1) assumes an MTJ stack layout, commonly seen in commercial magnetoresistive random access memory (MRAM). Our second design (MEI-2) is also based on a traditional MRAM process flow, but layers of the MTJ are deposited in reverse order. In MEI-2, the NML devices have the same thickness as the MTJ free layer. Simulations for MEI-2 suggest that the layer thickness and size are important design parameters, when considering realistic implementations of this MEI. By comparison, MEI-2 is applicable for the present process technology, while MEI-1 would be more easily fabricated with further technology development. [ABSTRACT FROM PUBLISHER]

Dependency of errors in nanomagnet logic datalines on the dipole coupling strength is investigated. Evolution of different types of errors at different coupling strengths is studied. Dipole coupling strength in datalines is varied by changing the inter-magnet spacing from 30nm to 10 nm and the aspect ratios of the 20-nm-thick Supermalloy (Ni79Fe16Mo5) dots from 90×60 nm² to 120×60nm². An error rate improvement up to 46% is observed for inter-magnet space reduction from 30 nm to 10nm. Error rates in datalines with larger spacing are dominated by premature switching, whereas a new type of error, due to the stronger influence of the driver magnets, dominates in datalines with tighter (sub-20-nm) spacing. For same spacing, datalines with lower aspect ratio magnets show higher error rates compared to those with higher aspect ratio. [ABSTRACT FROM AUTHOR]

Deep random forest (DRF), which combines deep learning and random forest, exhibits comparable accuracy, interpretability, low memory and computational overhead to deep neural networks (DNNs) in edge intelligence tasks. However, efficient DRF accelerator is lagging behind its DNN counterparts. The key to DRF acceleration lies in realizing the branch-split operation at decision nodes. In this work, we propose implementing DRF through associative searches realized with ferroelectric analog content addressable memory (ACAM). Utilizing only two ferroelectric field effect transistors (FeFETs), the ultra-compact ACAM cell performs energy-efficient branch-split operations by storing decision boundaries as analog polarization states in FeFETs. The DRF accelerator architecture and its model mapping to ACAM arrays are presented. The functionality, characteristics, and scalability of the FeFET ACAM DRF and its robustness against FeFET device non-idealities are validated in experiments and simulations. Evaluations show that the FeFET ACAM DRF accelerator achieves ~106x/10x and ~106x/2.5x improvements in energy and latency, respectively, compared to other DRF hardware implementations on state-of-the-art CPU/ReRAM. [ABSTRACT FROM AUTHOR]

The article presents information on the nanomagnet logic devices that do not require a magnetic field for clocking and requires support circuitry to re-evaluate a circuit when new inputs are available. Topics include torques generated by the spin Hall effect, magnetic field and potential energy reductions associated with spin-Hall-effect clocking. Other topics include complete energy analysis.

Hyperdimensional computing (HDC) is a brain-inspired computational framework that relies on long hypervectors (HVs) for learning. In HDC, computational operations consist of simple manipulations of hypervectors and can be incredibly memory-intensive. In-memory computing (IMC) can greatly improve the efficiency of HDC by reducing data movement in the system. Most existing IMC implementations of HDC are limited to binary precision which inhibits the ability to match software-equivalent accuracies. Moreover, memory arrays used in IMC are restricted in size and cannot immediately support the direct associative search of large binary HVs (a ubiquitous operation, often over 10,000+ dimensions) required to achieve acceptable accuracies. We present a multi-bit IMC system for HDC using ferroelectric field-effect transistors (FeFETs) that simultaneously achieves software-equivalent-accuracies, reduces the dimensionality of the HDC system, and improves energy consumption by 826x and latency by 30x when compared to a GPU baseline. Furthermore, for the first time, we experimentally demonstrate multi-bit, array-level content-addressable memory (CAM) operations with FeFETs. We also present a scalable and efficient architecture based on CAMs which supports the associative search of large HVs. Furthermore, we study the effects of device, circuit, and architectural-level non-idealities on application-level accuracy with HDC. [ABSTRACT FROM AUTHOR]

Nearest neighbor (NN) search computations are at the core of many applications such as few-shot learning, classification, and hyperdimensional computing. As such, efficient hardware support for NN search is highly desired. In-memory computing using emerging devices offers attractive solutions for NN search. Solutions based on ternary content-addressable memories (TCAMs) offer high energy and latency improvements for NN search at the expense of accuracy. In this work, we propose a novel distance function that can be natively evaluated with multi-bit content-addressable memories (MCAMs) based on ferroelectric FETs (FeFETs) to perform a single-step, in-memory NN search. We evaluate the efficacy of FeFET MCAMs in the context of few-shot learning applications with different datasets. As an example, we achieve a 78.54% accuracy for a 5-way, 5-shot classification task for the mini-ImageNet dataset (only 1.5% lower than software-based implementations) when using a 3-bit MCAM for NN search. We consider the effects of FeFET threshold voltage variations on the application accuracy and analyze the area and search energy requirements of FeFET MCAMs for accurate operations. Our results indicate that MCAMs require 2× lower area and search energy than TCAMs to achieve the same accuracy. Furthermore, we experimentally demonstrate a 2-bit implementation of FeFET MCAM using AND arrays from GLOBALFOUNDRIES to further validate the design concept. [ABSTRACT FROM AUTHOR]

Content-addressable memories (CAMs) are widely used for data-centric applications where one must search for data patterns. CMOS CAMs can incur large areas and, hence, power consumption. Nonvolatile (NV) devices, such as ferroelectric field-effect transistors (FeFETs) and resistive random access memories, have been used in the design of NV CAMs to improve both logic density and power consumption. To further improve logic density, this article proposes a compact, multistate CAM (MCAM) that can store 3 bits in a cell using just one FeFET and three FinFETs per cell. Moreover, the proposed MCAM does not require a precharging phase for search as is typical with other CAM designs, which can lead to improved performance. Simulations with experimentally calibrated 22-nm FeFET and 22-nm FinFET technology models suggest that the proposed 3T1Fe-MCAM can perform up to 7.1× faster search operations with up to 28.8× lower area–energy–delay product compared with state-of-the-art ternary/analog CAM designs. To show that the proposed MCAM array can accurately detect all worst case matches/mismatches, we design an MCAM array with 11 cells per row (to represent a 32-bit number). We also study how the nonidealities related to programming/search voltages impact performance metrics and show that the proposed MCAM can tolerate up to 15-mV noise during programming and up to 20-mV noise on search voltages even in a worst case match/mismatch. [ABSTRACT FROM AUTHOR]

Brain-inspired hyperdimensional (HD) computing emulates cognitive tasks by computing with long binary vectors—also know as hypervectors—as opposed to computing with numbers. However, we observed that in order to provide acceptable classification accuracy on practical applications, HD algorithms need to be trained and tested on nonbinary hypervectors. In this article, we propose SearcHD, a fully binarized HD computing algorithm with a fully binary training. SearcHD maps every data points to a high-dimensional space with binary elements. Instead of training an HD model with nonbinary elements, SearcHD implements a full binary training method which generates multiple binary hypervectors for each class. We also use the analog characteristic of nonvolatile memories (NVMs) to perform all encoding, training, and inference computations in memory. We evaluate the efficiency and accuracy of SearcHD on a wide range of classification applications. Our evaluation shows that SearcHD can provide on average 31.1 × higher energy efficiency and 12.8 × faster training as compared to the state-of-the-art HD computing algorithms. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistors (FeFETs) are being actively investigated with the potential for in-memory computing (IMC) over other nonvolatile memories (NVMs). Content addressable memories (CAMs) are a form of IMC that performs parallel searches for matched entries over a memory array for a given input query. CAMs are widely used for data-centric applications that involve pattern matching and search functionality. To accommodate the ever expanding data, it is attractive to resort to analog CAM for memory density improvement. However, the digital CAM design nowadays based on standard CMOS or emerging NVMs (e.g., resistive storage devices) is already challenging due to area, power, and cost penalties. Thus, it can be extremely expensive to achieve analog CAM with those technologies due to added cell components. As such, we propose, for the first time, a universal compact FeFET-based CAM design, FeCAM, with search and storage functionality enabled in digital and analog domains simultaneously. By exploiting the multilevel-cell (MLC) states of FeFET, FeCAM can store and search inputs in either digital or analog domain. We perform a device-circuit codesign of the proposed FeCAM and validate its functionality and performance using an experimentally calibrated FeFET model. Circuit level simulation results demonstrate that FeCAM can either store continuous matching ranges or encode 3-bit data in a single CAM cell. When compared with the existing digital CMOS-based CAM approaches, FeCAM is found to improve both memory density by 22.4× and energy saving by 8.6 ×/3.2× for analog/digital modes, respectively. In the CAM-related application, our evaluations show that FeCAM can achieve 60.5×/23.1× saving in area/search energy compared with conventional CMOS-based CAMs. [ABSTRACT FROM AUTHOR]

When exploring computing elements made from technologies other than complementary metal-oxide-semiconductor, it is imperative to investigate circuits and systems assuming realistic physical implementation constraints. This paper looks at molecular quantum-dot cellular automata (QCA) devices within this context. With molecular QCA, physical coplanar wire crossings may be very difficult to fabricate in the near to midterm. Here, we consider how this will affect inter-connect. We introduce a novel technique to remove wire crossings in a given design in order to facilitate the self-assembly of real circuits—thus, providing meaningful and functional design targets for both physical and computer scientists. The proposed methodology eliminates all wire crossings with minimal logic gate/node duplications. Simulation results based on existing QCA circuits and other benchmarks are presented, and suggest that further investigation is needed. [ABSTRACT FROM AUTHOR]

Lifelong on-device learning is a key challenge for machine intelligence, and this requires learning from few, often single, samples. Memory-augmented neural networks have been proposed to achieve the goal, but the memory module must be stored in off-chip memory, heavily limiting the practical use. In this work, we experimentally validated that all different structures in the memory-augmented neural network can be implemented in a fully integrated memristive crossbar platform with an accuracy that closely matches digital hardware. The successful demonstration is supported by implementing new functions in crossbars, including the crossbar-based content-addressable memory and locality sensitive hashing exploiting the intrinsic stochasticity of memristor devices. Simulations show that such an implementation can be efficiently scaled up for one-shot learning on more complex tasks. The successful demonstration paves the way for practical on-device lifelong learning and opens possibilities for novel attention-based algorithms that were not possible in conventional hardware., (© 2022. The Author(s).)