Search

This paper presents a simulation-based methodology for extracting a simplified view of a design's input-output behavior. Such a simplified design view can be used to facilitate test pattern justification from the outputs of the module to the inputs of the module. In this paper, extraction of a design simplification view is formulated as a learning problem. With a learning scheme for learning word-level functions, the core of the problem becomes developing an efficient Boolean learner. We discuss the implementation of such a Boolean learner and compare its performance with the one of best-known Boolean learning algorithms, the Fourier analysis based method. Experimental results are presented to illustrate the implementation of the simulation-based methodology and its usage for extracting a simplified functionality view from Open RISC 1200 datapath

Multi-million gate System-on-Chip (SoC) designs increasingly rely on Intellectual Property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP blocks has risen thus leading to possible thermal runaway. In IP-based design there has been a disconnect between system level design and physical level steps such as floorplanning which can lead to failures in manufactured chips. This necessitates coupling between system level and physical level design steps. The leakage power of an IP-block increases with its temperature which is dependent on the SoC's floorplan due to thermal diffusion. We have observed that different floorplans of the same SoC can have up to 3X difference in leakage power. Hence the system designer needs to be aware of this design space between floorplans and leakage power. We propose a leakage aware exploration (LAX) framework which enables the system designer to create this design space early in the design cycle and provides an opportunity to make changes in the system design. We show the size of the design space generated by applying LAX on ten industrial SoC designs from Freescale Semiconductor Inc. and observe that the leakage power can vary by as much as 190% for 65% difference in the inactive area.

As the timing behavior of the good and defective chips become statistical, the traditional notion that there exists a one-dimensional timing boundary to separate the good and defective behavior may no longer be true. This paper studies issues in test optimization for screening statistical delay defects. After the first silicon tapeout, test data learning based on silicon samples can be utilized to optimize the test set for mass production. This approach depends on the availability of known good and known defective samples. This paper focuses the discussion on silicon sample based test optimization. We relate this problem to binary classification and pattern selection to the feature selection problem in statistical learning. Experimental results are presented to explain the methodologies and the new concepts.

Multi-processor systems-on-chip pose a great challenge to validation due to their size and complexity. We approach the problem of MP SoC validation through a tool that uses a reusable scheme to effectively leverage a simulation-based abstraction scheme. Our tool checks an abstract representation of the system across traces obtained by simulating a system level implementation and analyzes the results for correctness. We have effectively used the tool on various live MP SoC design projects.

The purpose of statistical timing simulation is to assess the impact of process variations on pattern delays. In this paper, we propose a novel hazard-aware statistical timing simulator. Our simulator characterizes timing hazards in terms of uncertainty windows whose widths are computed as random variables. Given a 2-pattern vector, the simulator estimates the transition times and uncertainty windows at each circuit output as two separate random variables. We demonstrate that this simulator achieves much higher accuracy and robustness than its predecessor. With this improved statistical timing simulator, we study its applications from three perspectives: (1) improving test effectiveness through pattern selection (2) enhancing defect detection by using multiple test frequencies (3) extending defect coverage for different voltages and temperatures. Experimental results are presented to demonstrate the benefits as well as the limitations of using the statistical timing simulator in the context of screening frequency-dependent defects

We present a latch mapping methodology that judiciously leverages structural and functional analyses on digital sequential circuits. We make use of functional design constraints in a way to get latch correspondence information. For scanable latches we use a technique based on scan chain analysis to obtain latch correspondences. We also provide an effective heuristic for finding latch correspondences for latches (potentially nonscanable) in complex state machines having cyclic dependencies. Our methodology not only answers latch correspondence, but also provides polarity of the correspondence. This is a major advantage over earlier latch mapping algorithms. Experimental results obtained on embedded circuits from live PowerPCreg design projects have shown that our technique fares better than a leading vendor tool in mapping latches - in both quantitative (more latches mapped) and performance (time/memory used) aspects

A zero-suppressed binary decision diagram (ZBDD) based method is presented to identify a small set of gates so that every critical path contains at least one of the selected gates. All paths above a threshold D/sub th/ are stored in a ZBDD. Static implications are used to eliminate unsensitizable paths. A min-cut method on the ZBDD is then used to identify a small set of gates in the circuit for buffer insertion or resizing to optimize delay of the whole circuit. It is observed that the methodology identifies a very small set of gates and its effectiveness demonstrated experimentally on ISCAS'85 and ITC99 benchmarks.

Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and efficient statistical timing models (STM). Among many types of parameters required to be carefully modeled in an STM, spatial delay correlations are recognized as having significant impact on SSTA results. In this work, we assume that exact modeling of spatial delay correlations is quite difficult, and propose an experimental methodology to resolve this issue. The modeling accuracy requirement is relaxed by allowing SSTA to impose upper bounds and lower bounds on the delay correlations. These bounds can then be refined through learning the actual delay correlations from path delay testing on silicon. We utilize SSTA as the platform for learning and propose a Bayesian approach for learning spatial delay correlations. The effectiveness of the proposed methodology is illustrated through experiments on benchmark circuits.

As VLSI designs grow in complexity and size, errors become more frequent and difficult to track. Recent developments have automated most of the verification tasks but debugging still remains a resource-intensive, manually conducted procedure. This paper bridges this gap as it develops robust automated debugging methodologies that complement verification processes. Unlike prior debugging techniques, the proposed one exploits the hierarchical nature of modern designs to improve the performance and quality of debugging. It also formulates the problem in terms of Quantified Boolean Formula Satisfiability to obtain dramatic reduction in memory requirements, which allows for debugging of large designs. Extensive experiments conducted on industrial and benchmark designs confirm the efficiency and practicality of the proposed approach

Embedded memories form a crucial part in the design of modern high performance microprocessors. The number of transistors in memories forms a majority of the transistors in a typical high performance microprocessor. Therefore, modeling embedded memories is an important challenge in high performance microprocessor design. A typical design process involves a multiplicity of interacting methodologies - simulation, formal verification, design for test, emulation etc. Memory models are needed for each of these methodologies. This complicates the process of modeling memories. The authors present a tool called MemGen that automates memory model generation for all methodologies. It has been used in-house in Motorola Inc. and then later in Freescale Semiconductor Inc. in all high performance design projects. The authors present result obtained by using MemGen-generated embedded memories in real life design projects of PowerPCreg G2 and G4 microprocessors

The delay variations of a pattern set can come from two sources: (1) Different patterns sensitize different parts of the circuit and result in different delays. (2) The same pattern, applied on different chips, results in different delays because of process variations. For structural delay testing, these pattern variations may result in difficulty for finding an optimal test clock setting, which may significantly impact the defect screening effectiveness. This paper investigates the possibility of applying statistical timing analysis techniques to reduce pattern variations for structural delay testing. We develop an efficient statistical pattern-based timing simulator and devise pattern selection algorithms for reducing such variations. By constructing pattern sets with smaller variations, we show that higher screening effectiveness can be achieved. We present experimental results to demonstrate the advantages of our techniques based on benchmark circuits.

Design flow, RTL-verification, simulation-based techniques, basic concepts of equivalence checking, combinational equivalence checking, ATPG-based techniques, compare point matching, mitering, don't cares, solver overview (structural verification, BDD-based solvers, SAT-based solvers), decision diagrams (BDDs, zBDDs, word-level DDs). Also covered are concepts in SAT solvers (backtrack-search algorithm, effective techniques, including nonchronological backtracking & Boolean constraint propagation), new EDA-related techniques (covering immediate implications, partial-clauses, local decisions & partial clauses). Finally, the tutorial gives an overview of various commercially available tools, & their applicability. Also discussed are future challenges, such as design for verifiability & potential new directions.

Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean satisfiability. This formulation takes advantage of modern Boolean satisfiability solvers that handle large circuits in a computationally efficient manner. An extensive suite of experiments with large sequential circuits confirm the robustness and efficiency of the proposed approach. The results further suggest that Boolean satisfiability provides an effective platform for sequential logic debugging.

Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. This is performed with a simple hardware construction and a sequence of simulation/ATPG-based steps. Experiments on benchmark circuits demonstrate the competitiveness of the proposed method.

This paper presents the reasoning behind eliminating full-chip gate/switch-level simulations for microprocessors/digital system designs and utilizing RTL models for the purpose, provided formal boolean equivalence between RTL and gate/switch-level models have been established using symbolic simulation for all blocks that comprise the chip. No logic bug should go undetected if only RTL models are used for full chip simulations provided existing design methodologies are enhanced to incorporate a constraints checking flow coupled with a rigorous circuit metastability/contention prevention flow.

In Motorola's High Performance Design Center, two verification flows are often used to verify correctness of custom designed blocks. The first is an equivalence checking flow, and the second is a manufacturing test pattern generation/simulation flow. The two flows are often disconnected resulting into silicon failures on manufacturing test vector suites. Our aim is to analyze the disconnect and to arrive at a technique that bridges the gap between the two verification flows by validating the correctness of manufacturing test patterns. This reduces time to market by cutting down on precious silicon debug time by eliminating redundant defect fixes. Our experimental results were obtained from a set of custom designed circuits of a Motorola MPC74XX microprocessor.

There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates against the leakage power measured using SPICE simulations on industrial array designs belonging to the e5001 processor core. The comparison shows that the models are accurate with an error margin of less than 21.5% and thus can be used in high-level power-performance exploration. Interestingly, in array designs with dual threshold voltage technology, we observed that contrary to the general expectation, the array memory core contributes to just 9% and the address decoder contributes to as much as 62% of the total leakage power.

This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between delay defect diagnosis and traditional logic defect diagnosis. We propose different diagnosis algorithms, and evaluate their performance via statistical defect injection and statistical delay fault simulation. With a statistical timing analysis framework developed in the past, we demonstrate the new concepts in delay defect diagnosis, and discuss experimental results based upon benchmark circuits.

In this paper, we presented a new transition ATPG methodology flow for scan-based design using broad-side test format. A replicate and reduce (RR) circuit transform is introduced, which maps the two time frame processing of transition fault ATPG to a single time frame processing on duplicated iterative blocks with reduced connection. A complete ATPG methodology flow is proposed to generate high coverage transition test patterns both fast and efficiently. Experimentation results on several circuits from next generation Motorola microprocessor design are presented to show the effectiveness of our approach.

In the past, Symbolic Trajectory Evaluation (STE) was shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD sizes would often blow up. In this paper, we propose using a "dual-rail" symbolic simulation scheme to facilitate the application of STE proof methodology for verifying array systems. The proposed scheme implicitly partitions a given design into control domain and data-path domain, and symbolic simulation is carried out on both domains. With this scheme, the run-time OBDD sizes during the symbolic simulation for each domain can be limited. We demonstrate the effectiveness of our approach by verifying the Memory Management Unit (MMU) in Motorola high-performance microprocessors. The verification of MMU as a whole was not possible before because of the OBDD size blow-up problem when an ordinary symbolic simulator was used in the STE proof process.

Equivalence checking between Register Transfer Level (RTL) descriptions and transistor level descriptions of custom memories is an important step in the design flow of high performance microprocessors. Equivalence checking can be done with or without the knowledge of state mapping between the two descriptions. We present evidence that because of state mapping, our verification technique exercises system behavior that exposes hard-to-detect bugs that might otherwise go undetected. This paper defines Crossover Bugs (CB's) that can be present in scan-based custom designs and that are inherently hard-to-detect without state mapping. We demonstrate that such bugs can be missed by equivalence checking techniques that do not have state mappings between the two descriptions. By identifying the state correspondences between the RTL and the transistor implementation of custom memories, a more rigorous equivalence check can be performed compared to traditional equivalence checking methods such as product machine constructions. We also compare the time and memory complexities of crossover bug detection capability of the two equivalence checking approaches. We conclude with experimental results of CB detection on some of the custom designed embedded memories of Motorola's MPC 7455 microprocessor (compliant with IBM's PowerPC instruction set architecture).

Technology dependent logic optimization is usually carried through a sequence of design rewiring operations. In Veneris et al (Proc. Asian-South-Pacific Design Automation Conf., pp. 479-484, 2001), a new design rewiring method is proposed that combines error diagnosis and correction techniques with ATPG. In this work, we examine its complexity and we arrive to a new set of results with interesting theoretical and practical applications. We also present experiments that confirm the competitiveness of the approach and motivate future work in the field.

When testing high-performance custom designs, the implementation models for these designs can often be missing or only available late in a design cycle. To facilitate test preparation for these designs and to ensure their test quality, this paper studies ATPG approaches whose resulting test quality are less design model dependent. These ATPG approaches do not depend on the internal implementation structure of a design and utilizes multiple detection techniques to achieve the desired test quality. As a result, test quality results are transferable from one model representation to another. For high-performance custom designs, we discover that without explicit testing of the internal faults, an ATPG is able to deliver better quality performance than traditional model-dependent approaches. Experience and experimental results from a recent Motorola high-performance microprocessor is reported and discussed.

Testing of modern microprocessor designs remains a challenging problem. At Motorola's Somerset Design Center, we rely heavily on Design-For-Test (DFT) to address these challenges. To date our efforts have been very successful. This paper reviews our DFT methodology and how the DFT group is dealing with the new challenges that are facing PowerPC/sup TM/ microprocessor designs.

Custom circuits, in contrast to those synthesized by automatic tools, are manually designed blocks of which performance is critical to the full chip operation. Testing these block represents a major challenge and hence, a crucial time-to-market factor in micro-processor design flow. This paper investigates various methodologies for testing custom blocks. Issues of efficiently obtaining proper circuit model for ATPG tools as well as producing quality tests are analyzed and discussed. Tradeoffs among various methods are analyzed and compared. Experience and results based on recent PowerPC microprocessors will be reported.

We present a formal logic verification methodology for combinational circuits. The method uses simulation, logic diagnosis and ATPG to identify circuit lines that implement equivalent logic functions efficiently. One advantage of the proposed technique is that it identifies line equivalences under controllability and observability don't care conditions, while not suffering from false negatives. The method is easy to implement, and, due to its general nature, existing techniques can benefit from ideas described here. We also give implementation details and present experiments to confirm its potential.

Custom VLSI design at the switch level is commonly applied when a chip is required to meet stringent operating requirements in terms of speed, power, or area. ATPG requires gate level models, which are verified for correctness against switch level models. Typically, test models are created manually from the switch level models - a tedious, error-prone process requiring experienced DFT engineers. This paper presents an automated flow for creating gate level test models from circuits at the switch level. The proposed flow utilizes Motorola's Switch Level Verification (SLV) tool, which employs detailed switch level analysis to model the behavior of MOS transistors and represent them at a higher level of abstraction. We present experimental results, which demonstrate that the automated flow is capable of producing gate models that meet the ATPG requirements and are comparable to manually created ones.

The tradeoff between peripheral I/O format die (for wire bonding, tape automated bonding, or peripheral flip chip bonding) and area array I/O format die (for flip chip bonding) is examined as a function of partitioning a fixed functionality into a variable number of die. The comparison is made in the context of a multichip module (MCM). The automated analysis approach concurrently considers module size, thermal and electrical performance, and cost (including module level test and network) to assess the overall applicability of one bonding format over the other. >

In this paper we discuss the methodology used on PowerPC RISC microprocessors to verify the correctness of embedded array blocks. The functional behavior of these blocks cannot be verified using traditional functional simulators since the search space is too large. Our methodology combines the use of equivalence checking formal methods, simulation using ATPG test vectors, and symbolic trajectory evaluation We discuss how these techniques are applied to verify the operation of an array in during design representation formats. We also discuss how these techniques can be used for checking the consistency of different design representations.

The cost and quality of a multichip assembly is highly dependent upon the cost and quality of the incoming die. In the case of a bare die assembly, it is often highly desirable to use either Known Good Die (KGD) or die that have been burned-in and tested to the same level of quality and reliability as their packaged die equivalents. However, performing full bare die burn-in and test may not always be cost effective. This paper examines the question of whether it is always necessary to use KGD to produce a cost-effective multichip module (MCM) of acceptable quality. A process-flow based cost model is used to compare the cost and quality of MCMs assembled with KGD to MCMs assembled with die that have received wafer-level test only. In addition to test effectiveness at the wafer, die, and module level, factors that are considered include die complexity (size and I/O), number of die per MCM, the cost of producing the KGD, and rework costs and effectiveness. The cost model captures inputs from wafer fabrication through MCM assembly and rework. Monte Carlo simulation is used to account for uncertainty in the input data. The resulting sensitivity analyses give final MCM cost and quality as a function of the various factors for both KGD and die that have received wafer-level test only

Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. At Somerset, validation of array designs relies on both formal verification and vector simulation. Although several methods for army design validation have been proposed and had great success, little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, the authors propose a way of measuring the effectiveness of different validation approaches based on automatic design error injection and simulation. The technique provides a systematic way for the evaluation of the quality of various validation approaches at both logic and transistor levels. Experimental results using different validation approaches on PowerPC microprocessor arrays will be reported.

We present a methodology in which the behavior of custom memories can be abstracted by a couple of artifacts-one for the interface and another for the contents. Memories consisting of several ports result into several user-provided abstract specifications, which in turn can be converted to simulation models. We show that (i) a simulation model is an approximation of the corresponding abstract specification and (ii) the abstracted memory core can be composed with the un-abstracted surrounding logic using a simple theory of composition. We make use of this methodology to verify equivalence between register transfer level and transistor level descriptions of custom memories.

Logic optimization is the step of the VLSI design cycle where the designer performs modifications on a design to satisfy different constraints such as area, power or delay. Recently, ATPG-based design rewiring techniques for logic optimization have gained increasing popularity. In this paper we propose a novel ATPG-based design rewiring methodology that borrows from previous design error diagnosis and correction techniques. We also present examples and experiments that indicate the added potential of our approach which is expected to provide a "powerful" route to design optimization.

Static timing analysis sets the industry standard in the design methodology to gage the speed of high performance microprocessors. Unfortunately, not all the paths identified using such analysis can be sensitized. This leads to a pessimistic estimation of processor speed, and the engineering efforts spent optimizing such paths can not improve the performance of the chip. In the past, we demonstrated initial results of how ATPG technique can be used to eliminate false paths efficiently. Due to the gap between the physical design on which the static timing analysis of the chip is based and the test view on which the ATPG technique is applied to eliminate false paths, in many cases only sections of some of the paths in the full-chip were analyzed in our initial results. In this paper, we fully analyze all the timing paths using the ATPG technique overcoming the gap between the testing and timing analysis techniques. We applied our method on the second G4 PowerPC/sup TM/.

This paper describes the use of Symbolic Trajectory Evaluation (STE), a modified form of symbolic simulation, to verify the equivalence between RTL and transistor-level representations of on-chip custom memories for the latest PowerPC microprocessor. The validation of embedded memories and their associated control logic poses a special problem for traditional formal equivalence checking tools due to the inherently sequential and self-timed nature of the internal control logic and the large number of state-holding elements. The use of the VERSYS STE engine to validate these custom memories is illustrated. We present our array verification methodology, discuss some of the results of our approach, and outline plans for future development.

A well-known problem in timing verification of VLSI circuits using static timing analysis tools is the generation of false timing paths. This leads to a pessimistic estimation of the processor speed and wasted engineering effort spent optimizing unsensitizable paths. Earlier results have shown how ATPG techniques can be used to identify false paths efficiently, as well as how to bridge the gap between the physical design on which the static timing analysis is based and the test view on which ATPG technique is applied to identify false paths. In this paper, we will demonstrate efficient techniques to identify more false timing paths by utilizing information from an ordered list of timing paths according to the delay information. More than 10% of additional false timing paths out of the total timing paths analyzed are identified compared to earlier results on the MPC7455, a Motorola processor executing to the PowerPC/spl trade/ instruction set architecture.

We present a methodology in which the behavior of a switch level device is specified using abstract parameterized regular expressions. These specifications are used to generate a finite automaton representing an abstraction of the behavior of a blockof memory comprised of a set of such switch level devices. The automaton, in conjunction with an Efficient Memory Model [1], [2] for the devices, forms a symbolic simulation model representing an abstraction of the array core embedded in a larger design under analysis. Using Symbolic Trajectory Evaluation, we checkthe equivalence between a register transfer level description and a schematic description augmented with abstract specifications for one of the custom memories embedded in the MPC7450 PowerPC processor.

Hybrid techniques are effective for exploring interesting corner cases, coverage holes, invariant variations, and so forth, in the general area of directed functional validation. However, despite the emergence of several effective hybrid validation techniques, several questions still remain. The five articles in this special issue help explain some of the different facets of this area.

For verifying complex sequen tialbloc ks such as microprocessor embedded arrays, the formal method of symbolic trajectory ev aluation (STE) has achieved great success in the past [[3], [5], [6]]. P ast STE methodology for arrays requires manual creation of “assertions” to which both the RTL view and the actual design should be equivalent. In this paper, w e describe a novel method to automate the assertion creation process which improves the efficiency and the quality of array verification. Encouraging results on recent P owerPC arrays will be presented.

Functional validation is one of the most complex and expensive tasks in the current processor design methodology. A significant bottleneck in the validation of processors is the lack of a golden reference model. Thus, many existing approaches employ a bottom-up methodology by using a combination of simulation techniques and formal methods. We present a top-down validation approach using a language-based specification. The specification is used to generate the necessary reference models for processor validation using symbolic simulation. We applied our methodology for property checking as well as equivalence checking of microprocessors.

This paper presents an overview of the problem of testing semiconductor random access memories (RAMs). An important aspect of this test procedure is the detection of permanent faults that cause the memory to function incorrectly. Functional-level fault models are very useful for describing a wide variety of RAM faults. Several fault models are &scussed throughout the paper, including the stuck-at-0/1 faults, coupled-cell faults, and single-cell pattern-sensitive faults. Test procedures for these fault models are presented and their fault coverage and execution times are discussed. The paper is intended for the general computer scmnce audience and presupposes no background in the hardware testing area.

The use of functional vectors has been an industry standard for speed binning purposes of high performance ICs. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural testing an effective alternative to functional testing for speed binning, structural patterns need to correlate with functional test frequencies closely. We investigate the correlation between functional test frequency and that of various types of structural patterns on MPC7455, a Motorola processor executing to the PowerPC/spl trade/ instruction set architecture.

In the past, symbolic trajectory evaluation (STE) has been shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD (ordered boolean decision diagrams) sizes would often blow up. In this paper, we propose the use of both an ATPG-based justification engine and symbolic simulation to facilitate the application of STE proof methodology for array systems. Our method translates a given verification problem instance into ATPG justification objectives, and partitions a given design into ATPG and symbolic simulation domains. Then, by developing a scheme that enables the ATPG justification engine to work closely with the symbolic simulator, the runtime OBDD sizes during each symbolic simulation run can be limited. We demonstrate the effectiveness of our approach by verifying the memory management units (MMU) in Motorola high-performance microprocessors. The verification of a MMU as a whole was not possible before because of the OBDD size blow-up problem when symbolic simulation is used in the STE proof process.

This work proposes a wafer probe parametric test set optimization method for predicting dies which are likely to fail in the field based on known in-field or final test fails. Large volumes of wafer probe data across 5 lots and hundreds of parametric measurements are optimized to find test sets that help predict actually observed test escapes and final test failures. Simple rules are generated to explain how test limits can be tightened in wafer probe to prevent test escapes and final test fails with minimal overkill. The proposed method is evaluated on wafer probe data from a current automotive IC with near zero DPPM requirements resulting in improved test quality and reduced test cost.

Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. At Somerset, validation of array designs relies on both formal verification and vector simulation. Although several methods for array design validation have been proposed and had great success [Ganguly et al. 1996; Pandey et al. 1996, 1997; Wang and Abadir 1997], little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, we measure the effectiveness of different validation approaches based on automatic design error injection and simulation. The technique provides a systematic way to evaluate various validation approaches at both logic and transistor levels. Experimental results on recent PowerPC microprocessor arrays will be discussed and reported.