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A type of multilayer microstrip diplexer with highlyselectivewidebandfiltering channels is reported. Its closely-spaced fourth-order passbands are attributed to two circuit parts: (i) two third-order quasi-elliptic-type microstrip-to-microstrip wideband vertical transitions and (ii) a shunt two-stub dual-band bandpass filter (BPF) junction printed on the top layer. The two microstrip vertical transitions are developed by means of open-/short-circuitended microstrip lines and slotline stepped-impedance resonators (SIRs), respectively, and they correspond to the constituent lower and upper channels. The shunt dual-band BPF junction produces one additional transmission pole and one more pair of close-topassband transmission zeros (TZs) for each channel to further increase their filtering selectivity. The RF theoretical foundations and design procedure of the engineered broadband diplexer are detailed. For practical-validation purposes, a proof-of-concept prototype of two-layer fourth-order microstrip wideband diplexer is simulated, manufactured, and tested. Its measured lower and upper channels has two closely-spaced sharp-rejection passbands with center frequencies of 1.496 GHz and 2.759 GHz and 3-dB fractional bandwidths of 62.83% and 24.83%, respectively, while featuring power-isolation levels above 27.39 dB from 0.5 to 4 GHz., European Commission, Agencia Estatal de Investigación

Logic locking has emerged as a prominent key-driven technique to protect the integrity of integrated circuits. However, novel machine-learning-based attacks have recently been introduced to challenge the security foundations of locking schemes. These attacks are able to recover a significant percentage of the key without having access to an activated circuit. This paper address this issue through two focal points. First, we present a theoretical model to test locking schemes for key-related structural leakage that can be exploited by machine learning. Second, based on the theoretical model, we introduce D-MUX: a deceptive multiplexer-based logic-locking scheme that is resilient against structure-exploiting machine learning attacks. Through the design of D-MUX, we uncover a major fallacy in existing multiplexer-based locking schemes in the form of a structural-analysis attack. Finally, an extensive cost evaluation of D-MUX is presented. To the best of our knowledge, D-MUX is the first machine-learning-resilient locking scheme capable of protecting against all known learning-based attacks. Hereby, the presented work offers a starting point for the design and evaluation of future-generation logic locking in the era of machine learning., Comment: Accepted at IEEE TCAD 2021

Silicon-based optical media present several desirable properties for a wide range of applications. Herein, we propose a novel hybrid integration scheme that combines a silicon photonics platform and a 5.5%--silica planar-lightwave circuit (PLC) platform. By exploiting the performance advantages of each platform, we fabricated a polarization-insensitive low-crosstalk 8 8 silicon photonics switch butt-jointed with a compact 5.5%--silica PLC-based 100-GHz 8-channel arrayed waveguide grating (AWG). The device was driven by a smartphone-sized (9 cm 13.5 cm) control board. The fabricated device exhibits a fiber-to-fiber insertion loss of 12.6 dB, an average polarization-dependent loss of less than 0.57 dB, and less than -40 dB leakage to non-target output ports. We also demonstrate two uses of the proposed device. The first is the DEMUX and Switch operation, in which the spectrally divided light by the AWG is routed to an arbitrary output port by a subsequent switch. The second is the Switch and MUX operation, in which arbitrary wavelengths from arbitrary input ports are merged by the AWG. No spectral degradation was observed in either operation. These results demonstrate the potential of the 5.5%--PLC/silicon photonics hybrid platform for compact, low-power, and fast-switching applications.

This paper presents a selective laser melting (SLM) 3-D printed Ku-band diplexer using dual-mode resonators with high thermal stability. The diplexer is designed using dual-mode dimpled ellipsoid resonators which enables the diplexer mechanically self-supported in fabrication. Hence, the design has higher compatibility with the SLM printing process and the design can be extended to multiplexers with more channels. The excellent thermal stability is benefited from both the 4J36 invar alloy material with a lower coefficient of thermal expansion (C.T.E) as well as the tailored SLM printing process. Electrical and thermal performances of the diplexer are measured, showing that the fabricated diplexer is with average insertion losses of 0.69dB/0.42dB, return losses of >14dB, and centre frequency shifts of 5.62MHz/3.75MHz (

New transmission techniques for short-reach optical transmission applications especially datacenter interconnections are highly expected to break current bandwidth bottleneck, among which mode division multiplexing (MDM) based on few-mode fiber (FMF) is promising by exploring different linearly-polarized (LP) modes or mode groups as spatial transmission channels. However, it has been a great challenge to deal with degenerate modes in FMFs. In this paper, a FMF design utilizing multiple ring perturbations in fiber core to suppress modal crosstalk during fiber transmission is firstly proposed and a 6-LP-mode double-ring-core (DRC) FMF is fabricated with a high minimum refractive index difference (min|neff|) of 1.4910-3 among all the modes. Secondly, a novel degenerate-mode-selective coupler (DMSC) converting each degenerate LPmn mode into the LP11 mode in a two-mode fiber is proposed. Then intensity-modulation/direct-detection (IM/DD) MDM transmission scheme without any digital signal processing (DSP) can be realized utilizing mode multiplexer/demultiplexer (MUX/DEMUX) consisting of cascaded mode-selective couplers (MSC) and DMSCs, in which each degenerate or non-degenerate LP mode is considered as an independent transmission channel. Then based on the proposed DRC-FMF and mode MUX/DEMUX, we demonstrate a 4-LP-mode prototype system using commercial single-mode 10 Gbps SFP + modules and 4K video transceivers without any hardware or software modifications. Finally, the intra-LP-mode dispersion (ILMD) effect in a weakly-coupled FMF is analyzed and a modified fixed-analyzer method is proposed for its measurement. Experimental results show that it may be one of the major impairments for IM/DD MDM transmission.

This article presents a new compact multiplexer structure and its design approach, based on a novel resonant manifold. Different from typical transmission-line-based manifold multiplexers, the proposed manifold junction is formed of coupled resonators, so that the manifold also contributes to the filtering poles and selectivity in the passbands. The all-resonator configuration achieves a more compact footprint than the conventional manifold. This multiport filtering network can be represented by a single coupling matrix which can be obtained by using a robust optimization-based method. Tailored channel frequency allocation schemes are presented for the proposed multiplexers with a different number of channels. To validate the proposed concept, a triplexer and a five-channel multiplexer, both at X-band, are designed and tested using rectangular waveguide technology. Good agreements have been achieved between the measurement and simulations. Comparisons have been made with conventional multiplexers.

To cancel the multipath self-interference at the receiver of a wideband in-band full-duplex (IBFD) multiple-input multiple-output (MIMO) radio-over-fiber (RoF) transmission system, a photonic-assisted approach is proposed and experimentally demonstrated. A multipath optical tunable delay line (MOTDL) module with a large adjusting arrangement and high tuning precision is designed to manipulate the local reference signals, which are modulated onto several optical wavelengths and then poured into the MOTDL via a dense wavelength division multiplexer (DWDM). By tuning the time delay and attenuation of each path in the MOTDL, all the self-interference signals can be cancelled from other local transmit antennas of the MIMO RoF transmission system, and the desired radio frequency (RF) signal can be recovered. A proof-of-concept experiment is carried out to verify the feasibility. Results show that at the receiver of a 3 3 MIMO RoF transmission system, the multipath self-interference cancellation depths of 30.18 dB, 24.9 dB, 22.7 dB, and 20.88 dB at 16.6 GHz are achieved for the bandwidths of 100 MHz, 500 MHz, 1 GHz, and 2 GHz, respectively.

This paper reviews the latest developments in microwave acoustic wave devices. After an introduction and brief history of bulk acoustic wave (BAW) and surface acoustic wave (SAW) devices, a review is given for guided SAWs and XBARs - two new technologies, which are promising for future 5G applications. Following this, we discuss recent simulation techniques, such as 3D finite element method (3D FEM) and simulation of nonlinearities, as well as filter synthesis. Next, a review on tunable and reconfigurable acoustics is given. Finally, we present the latest developments in microwave acoustics for millimeter-wave (mm-wave) operation as well as BAW oscillators.

Introduction This study aims to investigate the possibility of driving multiple NFC antennas with a single NFC-controller by using a multiplexer. An artifact was developed and experiments were conducted in order to evaluate the design choice and in addition, to observe the impact of a multiplexer in an NFC system with respect to the number of successful tag detections, bit error rate (BER), the utilization of automatic antenna tuning (AAT) and the physical distance to the NFC tag. Data collected from the experiments was analyzed, and the results were discussed. The purpose of the thesis was concretized by formulating three research questions: [RQ1] How can the design proposed in the problem statement be implemented? [RQ2] How does the multiplexer impact the system’s ability to detect an NFC tag and read its contents at different distances? [RQ3] To which degree does the AAT-technology compensate for the issues caused by the multiplexer? Method This research has been conducted according to the design science research (DSR) methodology. DSR is a well-established methodology and suits the nature of this research, therefore it is used to answer the research questions. Findings The thesis demonstrates a viable solution using a multiplexer in NFC systems, with reduced detection distance as a factor to consider. The impact of AAT remains inconclusive, requiring further research. Implications This study shows that using a multiplexer in NFC systems can save costs and space, leading to more affordable and compact devices. It enables scalable, advanced NFC devices for diverse applications, encouraging wider adoption. However, developers must consider the impact of a multiplexer on detection distance when designing NFC-based applications Limitations This study has certain limitations. It focuses on a particular multiplexer and NFC antenna type, and specific testing conditions. It does not delve into the potential profitability, diverse applications, security or encryption concerns, compatibility with other devices, compliance with regulations, or hands-on verification of part connectivity.

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experience problems caused by technology scaling. In fact, due to their lower logic density and the need to provide interconnect programmability, rising wire resistance impacts the performance of FPGAs particularly negatively. This is further complicated by the traditional problem of reconfigurable architecture design: exact critical paths are not known at fabrication time. For FPGAs to deliver what is expected from them, they must continue to adapt to new technological and application realities. Local optimization of programmable interconnect around a known prior solution, which, for the past two decades, has been ensuring that performance increase of moving to the next technology node is achieved on time, no longer yields the expected results. Since technology scaling has moved away from a predictable trajectory driven by geometric shrinking, into the realm of an ever-increasing number of one-off scaling boosters, it is now harder than ever to develop a lasting intuition about how to escape these local optima. Coupling this with an ever-increasing number of different applications that require FPGA acceleration in a variety of different device integration and use contexts, we believe that the only real solution to this issue is to use design automation to seek new local optima. The problem with this, however, is that design automation algorithms comparable to those that exist in a standard Application-Specific Integrated Circui} (ASIC) flow have so far not been developed---riding the wave of Moore's law in the past decades made tackling the hard combinatorial optimization problems that arise in designing programmable interconnect unattractive. Where ASIC CAD algorithms, once developed, could be used to produce thousands of different circuits, basic economy behind FPGA's success meant that in every generation, only a handful of device families with shared programmable fabric architecture were produced. As a result, a large number of algorithms exist for transforming an ASIC described at a high level of abstraction using a hardware description language into a highly optimized netlist of gates, while programmable interconnect architectures still have to be described entirely by specifying every single wire and switch that comprise them---this would be equivalent to specifying an ASIC design by listing every single logic gate and all connections between them. Well, if such a specification has to be made only once per FPGA generation---or better yet, only once for a number of generations, as has largely been the case over the past two decades---maybe the effort of developing a set of algorithms that could do this automatically is not easily justified. The problem today, as we already mentioned, is that scaling time-tested designs with only minor modifications no longer yields the required results, while manually specifying a new design at this level of abstraction is hardly feasible after the stark increase in the number of variables that have to be taken into account due to technological and application changes. In this thesis, we address the issue by developing new algorithms for automated design of several important aspects of programmable interconnect.

We use material-distribution-based topology optimization to design a three-port frequency dividing multiplexer at microwave frequencies. That is, by placing a good electric conductor inside the design domain, we aim to design a passive device that splits the incoming signal’s frequencies into two frequency bands and transmits them to their respective output ports. The Helmholtz equation models the time-harmonic wave propagation problem. We solve the governing equation using the finite element method. The adjoint variable method provides the required gradients, and we solve the topology optimization problem using Svanberg’s MMA algorithm. In this study, we present a technique for modeling the distribution of a good electric conductor within the design domain. In addition, we derive a power balance expression, which aids in formulating a series of three objective functions. In each successive objective function, we add more information and evaluate its impact on the results. The results show that by selecting a suitable objective function, we achieve more than $$93.7\,\%$$ 93.7 % transmission for both the frequency bands. Moreover, the numerical experiments suggest that the optimization problem is self penalized and is sensitive to the initial design.

Mode-locked lasers with low noise performance, such as low timing jitter and relative intensity noise are essential for high-precision applications. In this letter, we demonstrated a 122-MHz all-polarization-maintaining mode-locked Er-doped fiber laser based on a nonlinear amplifying loop mirror. A hybrid component integrating a wavelength division multiplexer and a phase shifter is applied to increase the repetition rate. The relative intensity noise is 0.004% and 0.76% rms (integrated from 1 MHz to 100 Hz) from two output ports. The timing jitter characteristic is measured by the delayed optical heterodyne method. The timing jitter is ~1.9 fs rms (integrated from 1 MHz to 10 Hz) of both two output ports. The origin of the timing jitter of this laser is analyzed numerically based on the well-established theoretical model using the laser’s repetition rate, cavity dispersion, etc.

This article presents a 220-GHz four-channel, noncontiguous, and manifold-coupled waveguide multiplexer for future terahertz (THz) multichannel communication application. The multiplexer is composed of four Chebyshev bandpass filters based on metal waveguide technology. Through a unique design in which the tuning dimensional variables are reduced to 14 and a co-design of low-order electromagnetic (EM) distributed models and full-wave EM models, the design optimization is achieved with a good computational efficiency and design accuracy. The proposed multiplexer is fabricated by high-precision computer numerical control (CNC) milling technology, in which the fabrication errors are evaluated to be within ±3 μm. The measured results exhibit 1.7 dB of in-band insertion loss and better than 15 dB of average common-port return loss for each of the channel filter. The measured results are all in good agreement with the simulated ones, thereby validating the complete design procedure.

In this article, the quantum phase slip junction (QPSJ) based full adder, multiplexer, and demultiplexer memoryless circuits for superconducting digital applications are designed for the first time. Generally, the memoryless circuits are implemented by interconnection of the basic gates (i.e., AND, OR, NOT). So in this article, the structures of the QPSJ-based AND and OR gates are also modified in order to reduce the complexity of their connections to the other gates by removing or changing the location of the clock pulse from their output branches. When a gate is connected to the next one, the elements of the second gate are loaded to the circuit of the first gate. The output current of the first gate will be affected due to this loading and no Cooper pair may be produced at its output and the next connected gate will not be switched. Therefore, the main tip in designing of these circuits is that each constituent gate must provide the necessary output current to drive the next connected gates, since each gate is driven by one Cooper pair. In this article, providing sufficient output current for each gate has been observed by 1) selecting proper critical voltages of the QPSJs and 2) by adding extra elements to or removing some elements from the connected gates in the proposed memoryless circuits.

We design and experimentally demonstrate an ultra-compact dual-mode mode-division multiplexing (MDM) photonic integrated circuit (PIC), which supports on-chip optical signal mode-order-based routing and mode-independent broadcasting. The MDM circuit is composed of inverse-designed three multiplexers, one 3-dB power splitter, three bends and one crossing based on photonic-crystal-like subwavelength structure. The measured excess loss and crosstalk of the fabricated MDM circuit are lower than 5.9 dB and −13 dB over a 60 nm observable wavelength span, respectively. The experiment results of single-channel 25 Gbit/s optical signal transmission show that only 1.2-dB power penalty is introduced through the MDM circuit at a bit-error-rate of 10−9.

Mode division multiplexing (MDM) has attracted great attention in recent years to increase the network capacity. To apply MDM in data center applications, a low-cost and low power consumption system is desired. In this letter, we utilize 850-nm single-mode VCSEL as the laser source and report mode division multiplexed transmission over a standard single-mode fiber, which is two-mode at 850 nm. Due to the small spot size and low numerical aperture, single-mode VCSEL can be coupled into single-mode fibers with low loss. The mode multiplexer and de-multiplexer devices are designed and fabricated based on fiber mode selective couplers using Hi780 fiber as the 850-nm single-mode launch and receiving fiber and standard single-mode fiber as the few-mode transmission fiber. The MDM system supports two channels, corresponding to the LP01 and LP11 mode in the few-mode transmission fiber. Detailed characterizations of the multiplexer and de-multiplexer are conducted including the insertion loss and crosstalk measurements. System transmission at 25 Gb/s shows error free performance over 1-km standard single- mode fiber for both channels. The utilization of VCSEL and standard single-mode fiber can potentially provide a low-cost solution for MDM systems in data center applications.

The development of devices for communication networks to transmit information has become an active and growing field of research. Multiplexer/demultiplexer (M/D) is one of the basic devices in this field. In this paper, an M/D design is introduced based on the surface plasmon resonance in optical ring resonators. The number of inputs and outputs of M/D is 3 × 1 and 1 × 3, respectively. All parameters of the structure, including radius and width of ring resonators and waveguides, have been evaluated to obtain the optimal response. Also, we used the nonlinear gold property to expand the range of M/D performance and simulated the results for intensities less than 100 MW/cm2. Selectivity in the number of inputs and outputs, controllability using several parameters, all optically, selectivity in operation frequency, nanoscale size, reconfigurability, and integrated capability are the features of this design. In our simulation, we consider transmission and reflection of light in each port based on the finite difference time domain for evaluation of results.

In-Memory computation has received considerable attention in the light of recent advances made in the memristor-based design. Non-volatile memristor devices are compatible with both the crossbar structure, CMOS technology, and can perform logical operations when subjected to suitable voltages. In this work, a generalized synthesis technique is presented to implement the logic functions inside pure memristive-crossbar. To initiate the process, two novel memristive-designs are proposed for 2:1 multiplexer (MUX) that follow Memristor Aided loGIC (MAGIC) design style. Experimental results showed that each design is at least 68.05 %, 35.92 % more energy-efficient than their existing IMPLY, MAGIC-based designs, respectively. One of our proposed MUX designs is optimized in memristor-count, and the other is latency-optimized. The latency-optimized design offers 20 % improvement in performance compared to its existing IMPLY, MAGIC-based peers. Based on the simulation methodology presented in this work, the memristive-MUXes are simulated in Cadence Virtuoso. Subsequently, our proposed MUX designs are used for the technology mapping of the nodes of the Binary Decision Diagrams (optimized in terms of node, path counts) for the logic functions. Our proposed technique optimizes the implemented logic circuits in terms of memristor-count, step-count, and provides the details for – latency, required memristors, energy, area. Comparison of the synthesis results showed that the circuits generated using our proposed MAGIC-MUXes, are at least 82.21 %, 44 % more energy-efficient, and can offer 18.94 %, 18.92 % more performance-improvements than their peers, realized using the existing IMPLY, MAGIC-MUX designs, respectively. Also, our proposed-MUX based circuits need at least 56.73 % lesser crossbar-areas than their existing MAGIC-MUX based peers, which indicates the scope for large scale parallel processing inside a given memristive-memory.

A 3D architecture made up of a CMOS layer combined with a 3D stack of bipolar memristor crossbar arrays provides an innovative approach to hardware support for utilizing the strength of CMOS combined with the strength of memristors. Memristors have been evaluated for implementing a broad spectrum of applications such as memory, computations, hardware-based security primitives, cryptography, etc., and numerous studies have shown that memristors are desirable candidates for such applications. This paper proposes a novel 3D memristive crossbar architecture (i.e., a stack of memristive crossbar arrays built on top of CMOS substrate) with a specific focus on the way of connecting the crossbar arrays to the CMOS layer. The proposed architecture is configurable and allows restructuring crossbar arrays and creating 1D arrays with adjustable sizes. The proposed architecture enables parallel and pipeline computations where data can move or be processed in planes perpendicular to the stacked crossbar arrays. In addition, the proposed architecture is scalable meaning that stacks of crossbar arrays can be connected without additional overhead. This paper shows examples of implementing a full adder, a 4-bit look-ahead carry generator, and an 8-bit multiplexer. Simulations and area, delay, and power analysis demonstrate the behavior of the proposed 3D circuit.

This article presents a hardware- and power-efficient RRAM-based neural network capable of online learning. The network is modularized in consideration of scalability and consists of 11 modules. Each module comprises two 25 × 25 RRAM crossbar arrays, four analog multiplexers, and one neuron chip. A stochastic neuron that performs both quantization and activation of the column current flowing through the RRAM array is used to perform online learning without using the high-resolution analog-to-digital converters and digital-to-analog converters. The impact of the initialization of the RRAM device on the network performance is analyzed and a fast yet effective method of initialization is also presented. The network consists of three fully connected layers with 100 input and 10 output neurons. The two hidden layers are made up of 50 and 25 neurons, respectively, and a total of 13 × 103 synapses are implemented by combining 21 RRAM arrays. The neuron chip, which includes 32 neurons, is fabricated through a 0.18-μm standard CMOS process. The network achieves a classification accuracy of 93.4% for the reduced Modified National Institute of Standards and Technology database (MNIST) dataset and the energy efficiency of 38.1 teraoperations per second per Watt (TOPS/W), the highest efficiency among recently reported state-of-the-art RRAM-based neural networks.

Here a 1×5 microfluidic optical switch using double drives is proposed. It has a simple structure and ignorable polarization dependent loss. First, the switch with the straight waveguide structure ...

A novel approach to de‐embed the frequency response of filters connected to a 2‐channel multiplexer without the need for unplugging is proposed. The technique to manifold coupled multiplexers with arbitrary number of filters is also theoretically generalised. In multiplexer tuning, there are practically important circumstances in which it is advantageous to de‐embed the frequency response of filters in multiplexers without detaching them. The authors show that using a novel technique and reasonable approximations, all filters of a multiplexer can be modelled by simple microwave networks, and then, the equivalent rational function of the channel filters can be estimated appropriately by the rational H2 approximation; extraction of this model facilitates tuning of the filters using the coupling matrix method. The impact of mechanical tolerances on the accuracy of the proposed technique is also studied. Next, this method is examined on a 2‐channel multiplexer and its application in de‐embedding and tuning of its connected filters is verified. Provided that the mechanical tolerances of the structure are sufficiently small, this technique is a powerful engineering solution towards tuning of manifold‐coupled multiplexers.