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One of the greatest challenges in the field of printed electronics is the performance stability of the devices fabricated by the different printing technologies e.g. inkjet or gravure printing technology. The performance instability can be defined in terms of the device breakdown or by other effects like the emergence of leakage current under the constant high voltage inputs (especially the dielectric within the transistor architecture). The reasons behind this phenomenon can be various, but the most prominent indication can be detected from the materials used and the deposition methodology. For this purpose the herein work is presented, targeting on the all inkjet-printed organic thin film transistor (OTFT), but keeping the focus on the basic building block for fabricating inkjet-printed OTFTs. In this case it is the metal-insulator-metal (MIM) layer structure. Herein, the MIM structures are inkjet-printed, and then characterized optically and electrically. The dielectric layers for the MIM structures are printed using three different dielectric ink materials either individually 1) Single component system; or in combination with each other as in form of bi-layer stack 2) Multiple component system. The thickness of the printed dielectric layers is varied for these MIM structures. The electrical characterization is performed with respect to current vs. applied voltage and is done for a large number of iterations. The leakage current is of interest and shows a negative and positive trend towards the single component system and multiple component system for the dielectric layers in the MIM characterization structures respectively.

Printed electronics technologies add new fabrication concepts to the classical set of microelectronic processes. Among these, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to make use of such a property: (1) wiring new metallic layers on top of circuits to build programmable logic array-like circuits, (2) programming OTP ROM like memories, and (3) building inkjet-configurable gate arrays. The capability of building an individual circuit with technological steps simpler than photolithographic ones opens a concept similar to the successful field programmable gate array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the drop-on-demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by two different DoD technologies: inkjet and superfine jet, and have been compared to mask-based photolithography technology with promising results. acceptedVersion

Search, retrieval, and management of multimedia contents are challenging tasks for users and researchers alike. The aim of e-sentencias Project is to develop a software-hardware system for the global management of the multimedia contents produced by the Spanish Civil Courts. We apply technologies such as the Semantic Web, ontologies, NLP techniques, audio-video segmentation and IR. The ultimate goal is to obtain an automatic classification of images and segments of the audiovisual records that, coupled with textual semantics, allows anefficient navigation and retrieval of judicial documents and additional legal sources.

Reconfigurable MPSoCs (Multiprocessor System-on-Chip) could be viable for certain applications niche where the flexibility of FPGAs (Field-Programmable Gate Array) and software is needed, and a small number of units dismiss other silicon options. However, their design complexity is very high, and raises additional problems, i.e. the definition of a suitable programming model, an efficient memory organization, and the need for ways to optimize application performance. In this paper, we propose a complete development process, which addresses these problems by complementing the current SoC (System-on-Chip) development process with additional steps to support parallel programming and software optimization. This work explains systematically problems and solutions to achieve a FPGA-based MPSoC following our systematic flow and offering tools and techniques to develop parallel applications for such systems.

The present work explores the effect of introducing stereoscopic depth to two specific examples of applications. The utilized depth has both an aesthetic and utilitarian function. One case explores a 3D garment catalog, and gives the user the task to rate garments. The second use case is a ‘Pairs’ game in which completing the game itself is the task. In total, effectiveness, efficiency, usability, desirability and gaze patterns were compared between monoscopic and stereoscopic versions of both applications. Time to complete the relevant task did vary, but efficiency, usability, and visual perception did not change. Desirability and eye patterns did differ. This behavior is important to acknowledge in order to better design experiences that utilize stereoscopic images.

Final Report, Keep-in-Touch Project n° 96106

Test generation for logic faults can also be used to enable Iddq sensing devices detect a large number of Iddq-testable faults such as stuck-on transistors and line bridging. However, there are some of these faults not covered by the stuck-at fault model that need particular attention. In this paper, we present a method to generate test patterns for short-circuit faults with difficult equivalence for the gate-level stuck-at model. A symbolic simulation of a circuit having been injected a set of faults is performed to obtain its functional response, which is given as a set of functions in terms of input and fault-selection Boolean variables. Such functions are operated to obtain a minimal set of appropriate test vectors, which can be directly used as part of the final test set, or fed into a gate-level ATPG to improve the switch-level fault coverage of its resulting test patterns.

Application specific printed electronic circuits (ASPECs) are the corresponding term with application-specified ICs for printed electronics. The same as any new technology, printed electronics is suffering from some restrictions in design and process technology aspects. An important stage in the ASPEC design is the final wiring of the organic thin-film transistor arrays or gate arrays to customize it to implement any specific target application that fits in their structure. In this paper, we evaluate two additive manufacturing technologies: aerosol jet using Optomec M3D and electrohydrodynamic printer using superfine inkjet. Both techniques are based on direct-writing of the pattern corresponding to any individual circuit being fabricated (digital printing) enabled by the mask-free noncontact deposition of materials. Finally, these structures will be compared with the corresponding photolithography mask technology. Some parameterized test vehicles, with different instantiations for the variation of line widths and separations, have been designed to be wired using the target technologies. These test vehicles have been fabricated at the Centre for Process Innovation by a five masks lithography and subtractive patterning technology. Results show that both direct printing technologies are feasible for the fabrication of the gate-array customization, thus allowing individual personalization of every circuit what can produce added value functionalities at low cost such as the equivalent effect of having an ROM memory which final contents could be customized at home by using low-cost digital printing technologies. Further interactions between transistor bulk and wiring technologies can improve the obtained performance in order to end up in an industrialized process.

This paper presents two main contributions toward efficient very large scale integration circuits mapped with simple cells: 1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and 2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. An effective pattern-based algorithm to identify XORs/XNORs on and-inverter graphs is also presented. We show that efficient implementations in terms of inverter count, transistor count, area, power, and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while: 1) optimizing the number of added inverters and 2) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation, and delay up to 48%, 4%, 8%, 14%, and 16%, respectively.

Most published chaining algorithms require a previous pairing step. Since an heuristical approach is used for pairing, the optimal pairing is not always found. A new algorithm is presented that combines pairing and chaining into one single step. This approach is based on Chi-Yi-Hwang et al.'s (1990) algorithm. Extended definitions are given to introduce the new features. A new upper bound on the number of possible abutments reduces the search tree. Optimal results are always reached and execution time is maintained low.

In this paper we present the chromatic neural-like network. It is a two-layer network architecture used in an image analysis system to learn objects classification tasks. Each processing unit in the hidden layer is considered as a network which codifies the color information at pixel level. The output layer makes a features analysis from the hidden layer responses in every window of the image. The architecture and operation of this network are extracted from the studies of biologic visual neural systems behavior and it is a model to be used in an artificial vision system. The learning methodology is an unsupervised, fuzzy and adaptive one and lets a faster training for image processing than other algorithms. It combines the thresholding in features spaces technique and the fuzzy Kohonen clustering nets approach with a gaussian membership function. Experimental results of the net performance with real images are shown. >