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A novel method to efficiently and accurately prognosticate the pattern count at different input compression ratios with the Embedded Deterministic Test (EDT) compression technology is proposed. With this method the total ATPG run time can be significantly reduced compared to the currently used trial-and-error method.

This paper proposes an innovative design methodology for layout-friendly decompressor used in EDT compression architecture. A segmented decompressor architecture is proposed, in which each segment drives a subset of scan chains. The EDT input channel injectors are carefully selected to maximize the encoding capacity for all scan chains. Experimental results with several large industrial designs demonstrate that using the proposed technology, the routing congestion introduced by EDT decompressor is reduced significantly with negligible impact on test coverage and improved pattern count.

There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of $2\times $ – $4\times $ compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

This paper presents Star-EDT—a novel deterministic test compression scheme. The proposed solution seamlessly integrates with EDT-based compression and takes advantage of two key observations: 1) there exist clusters of test vectors that can detect many random-resistant faults with a cluster comprising a parent pattern and its derivatives obtained through simple transformations and 2) a significant majority of specified positions of ATPG-produced test cubes are typically clustered within a single or, at most, a few scan chains. The Star-EDT approach elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. Experimental results obtained for large industrial designs, including those with a new class of test points aware of ATPG-induced conflicts, illustrate feasibility of the proposed deterministic test scheme and are reported herein. In particular, they confirm that the Star-EDT can act as a valuable form of deterministic BIST.

This paper presents a novel scan-based design for test (DFT) paradigm. Compared with conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage or allows applying a much larger number of vectors within the same time interval. An equally important factor is the toggling activity during test—with this scheme, it remains similar to that of the mission mode. Several techniques are introduced that allow integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. The experimental results obtained for large and complex industrial application-specific IC designs illustrate the feasibility of the proposed test scheme despite additional costs and efforts entailed in consolidating architectural changes and operations across a DFT flow.

Test points are known to improve the fault coverage in BIST applications. This article discusses a new class of test points used to improve the ATPG pattern count in designs that employ embedded deterministic test.

As cars become increasingly computerized and their safety functions are evolving rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing more than a hundred embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. The paper presents a scan-based LBIST scheme optimizing test time and area overhead during in-system test applications for automotive ICs. It ensures highly reliable operations of ICs for the duration of their lifespan. The proposed scheme works with observation test points that capture faulty effects every shift cycle into separate observation scan chains. To reduce area overhead, the scheme takes advantage of a procedure allowing one to share flip-flops among control points. It is also shown how test points can enhance test coverage in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine observed faults are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in quality of test over traditional BIST schemes.

The semiconductor industry ramping up design capabilities for emerging technologies is facing unprecedented test quality and yield management challenges. To facilitate diagnosis of yield issues and to enable repair processes, an accurate defect isolation is needed with support of more advanced test, diagnostic, and yield analysis tools. Scan remains instrumental in developing more advanced DFT technologies, including logic BIST and on-chip test data compression. Its reliable operations are essential for test pattern bring-up, failure analysis, and yield learning. This paper demonstrates how to re-architect on-chip test data compression environment to enable multiple and repeated scan integrity tests for advanced test procedures, including various forms of stroboscopic electron-beam imaging and laser voltage imaging. The presented approach avoids the repetitive loading of scan chains and therefore reduces significantly test time and may support advanced diagnostic techniques. The new solution has virtually no area overhead, and does not compromise the performance of the original test logic.

This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies. Focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeting small-delay defects of FinFET transistors, and a new DOT method which explicitly targets chip layout dependent cell-neighborhood defects. Test results from traditional Stuck-at/Transition patterns, from traditional CAT patterns, from TA-CAT patterns, and as well from cell-neighborhood patterns, applied to FinFET technology designs, will be presented in this paper. In addition, a correlation to System-Level-Test fails will be discussed.

With the growing number of very complex safety-critical components used in advanced driver assistance systems and autonomous vehicles, integrated circuits in this area must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This, in turn, requires advanced test solutions that have to respond to challenges posed by automotive parts. This paper presents Stellar BIST - a deterministic two-level compression scheme for in-system automotive test. The proposed solution seamlessly integrates with any sequential test compression scheme and takes advantage of the fact that certain clusters of test vectors detect many random-resistant faults where a cluster consists of a parent pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant trade-offs between area and time, critical for in-system automotive applications. Experimental results obtained for large industrial designs with stuck-at and transition faults illustrate feasibility of the proposed test scheme and are reported herein.

This is the extended summary of the PhD thesis on new test point insertion techniques. The thesis provides a comprehensive study of innovative DFT schemes going far beyond traditional logic BIST-based applications of test points. The proposed methods visibly decrease pattern counts, reduce test generation and test application times, and increase test coverage by means of algorithms capable of identifying and resolving conflicts between circuit’s internal signals. In particular, it is shown that new test points provide, on the average, 2x-3x increase in test compression for stuck-at, transition and cell-aware patterns. Furthermore, it is demonstrated that test-point-centric DFT logic can be successfully used to lock a circuit or hide its functionality. As a result, this approach improves the overall hardware security against reverse engineering, IC cloning, and IP theft.

The paper presents a novel test data compression scheme. This low-silicon-area solution builds on the isometric compression paradigm, but makes it more flexible, elevates encoding efficiency to values unachievable through any conventional type of sequential compression, and ensures high test coverage due to programmable selection of full toggle scan chains. The presented approach follows from a fundamental observation that only a few specified positions in test cubes are necessary to detect faults, while the remaining ones have alternative sites. Such test cubes are used to form circular test templates which synergistically control a decompressor and guide ATPG to find assignments yielding highly compressible test cubes. A redesigned decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. Experimental results obtained for large industrial designs confirm superiority of the proposed scheme over state-of-the-art techniques and are reported herein.

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SoC) designs with embedded test data compression. These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with embedded deterministic test-based test data compression. The same solutions allow efficient handling of physical constraints in realistic applications. Finally, state-of-the-art SoC test scheduling algorithms are rearchitected accordingly by making provisions for: 1) setting up time-effective test configurations; 2) optimization of SoC pin partitions; 3) allocation of core-level channels based on scan data volume; and 4) more flexible core-wise usage of automatic test equipment channel resources. A detailed case study is illustrated herein with a variety of experiments allowing one to learn how to tradeoff different architectures and test-related factors.

This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that addresses stringent test requirements of certain application domains such as the fast-growing automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage of conventional BIST schemes. Alternatively, one may consider applying a much larger number of vectors within the same time interval. Although the new scheme may resemble traditional BIST logic, it is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid test points that creates this new synergistic LBIST paradigm. The hybrid observation points, inserted at the most suitable locations, capture faulty effects every shift cycle into dedicated flip-flops that form separate scan chains. Their content is gradually shifted into a compactor, which is shared with the remaining scan chains that still deliver test responses captured once the entire test pattern has been shifted-in. Experimental results obtained for industrial designs illustrate feasibility of the proposed BIST scheme in terms of test time, test coverage, and area overhead, and they are reported herein.

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.

This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

In this study the authors show how the interface between automatic test equipment (ATE) and on-chip decompression logic can be improved by a smart reuse of the scan chains. Storing the parent patterns of a modular decompression scheme in groups of scan chains avoids multiple loads from the ATE and thus reduces the test time. The presented algorithm for scan chain selection allows a flexible bandwidth management while preserving encoding efficiency and fault coverage.

This paper presents preemptive test application schemes for system-on-a-chip (SoC) designs with embedded deterministic test-based compression. The schemes seamlessly combine new test data reduction techniques with test scheduling algorithms and novel test access mechanisms devised for both input and output sides. In particular, they allow cores to interface with automatic test equipment through an optimized number of channels. They are well suited for SoC devices comprising both nonisolated cores, i.e., blocks that occasionally need to be tested simultaneously, and completely wrapped modules. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application schemes and are reported herein.

Recent reverse-engineering attempts to steal a competitive design intellectual property (IP) or to identify the device technology in order to counterfeit integrated circuits (ICs) have raised serious concerns in the IC design community. This paper demonstrates that test points - industry-proven design-for-test technology used to enhance the overall design testability - can also be deployed in the mission mode to obfuscate the circuit's structure, and thus to improve the hardware security against reverse engineering, IC cloning, and IP theft. In particular, it is shown how test points can facilitate the hiding of design functionality from adversaries. As a result, not only the overall design testability is improved, but also effective protection against reverse engineering and other forms of attacks is ensured.

Logic built-in self-test (LBIST), originally introduced for board, system, and in-field tests, is now being increasingly used with on-chip test compression. This hybrid approach allows LBIST to become a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs that are targeted for safety-critical and automotive systems. Test points are common in BIST-ready designs where they play a key role in reducing both test application time given a test coverage goal and the overall silicon overhead so that one can get a desired coverage with the minimal number of patterns. Unfortunately, these test points are typically dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG-based test pattern counts cannot guarantee desired random testability. Incompatibility of both types of test points has motivated research presented in this paper. We present a novel hybrid test point technology designed to both reduce deterministic pattern counts and improve fault detection likelihood by means of the same minimal set of test points. Experimental results obtained for large industrial designs illustrate feasibility of the proposed hybrid test points and are reported herein.

Conflict-aware test points, introduced recently, facilitate significant reductions in deterministic test pattern counts. However, dedicated flip-flops driving control points increase test logic area. This paper presents a method to minimize silicon area needed to implement conflict-aware test points by reusing functional flip-flops as drivers of control points. Conflict analysis is applied during the test point selection process, and ATPG verification is run for every potential candidate. Experimental results show that functional flip-flops can be reused as drivers for more than 90% of the control points with the average of 5% penalty in pattern count increase as compared to methods using only dedicated flip-flops. After replacing dedicated flip-flops with functional flip-flops, conflict-aware test points can still achieve remarkable pattern count reductions.

The gradual change in consumer mindset from considering horsepower, style, and reliability as key factors when buying automobiles, to better energy efficiency, lower emissions, and advanced driver assistance systems (ADAS) is resulting in an exponential growth in the amount of electronics that is being added into cars today. Whether it is the desire to safely access contents in the car for infotainment, or the need for advanced driver assistance for a safer drive, or vehicle-to-vehicle communication for getting alerts from highway sensors or transportation authorities, electronics is the key for making these features a reality. As the number of electronic components in cars is on the rise, the standards driving safety and reliability (such as ISO 26262) in the automotive space are applicable to the ICs that are being used in cars as well. It is not only important to guarantee very high quality for the semiconductor devices being used, it is equally important to constantly test and monitor the health of such devices during its normal operation. Consequently, ICs manufactured for automotive applications pose some unique challenges in the area of VLSI testing -a)How to improve test quality to reduce the overall DPPM targets to single digits?b)How to test a device in-system when it is idle but the system is in operation?In this tutorial, we will present recent advances in digital testing that enables manufacturing of high quality ICs being used for various automotive applications. Multi-core designs, heterogeneous component integration, and sophisticated packaging techniques aggravate the challenge of testing such devices effectively. We will discuss some of the advanced fault models such as n-detect, timing aware, and cell-aware that are gaining traction and being deployed for manufacturing test of such designs in the automotive space. Numerous case studies and results based on silicon experiments will be presented.

The embedded deterministic test-based compression uses cube merging to reduce a pattern count, the amount of test data, and test time. It gradually expands a test pattern by incorporating compatible test cubes. This paper demonstrates that compression ratios can be order of magnitude higher, if the cube merging continues despite conflicts on certain positions. Our novel solution produces test clusters, each comprising a parent pattern and a number of its derivatives obtained by imposing extra bits on it. In order to load scan chains with patterns that feature original test cubes, only data necessary to recreate parent patterns as well as information regarding locations and values of the corresponding conflicting bits are required. A test controller can then deliver tests by repeatedly applying the same parent pattern, every time using a different control pattern to decide whether a given scan chain receives data from the parent pattern, or another pattern is used instead to recover content of the original test cube. Compression of incompatible test cubes preserves all benefits of continuous flow decompression and offers compression ratios of order 1000× with encoding efficiency much higher than 1.0. We also demonstrate that test clusters make it possible to deliver test patterns in a flexible power-aware fashion. This framework achieves significant reductions in switching activity during scan loading as well as additional test data volume reductions due to encoding algorithms employed to compress parent and control vectors.

Unknown (X) states are increasingly often identified as having potential for rendering semiconductor tests useless. One of the key requirements for a reliable test response compactor is, therefore, to preserve observability of any scan cell for a wide range of X-profiles while maintaining very high-compaction ratios, providing ability to detect a variety of failures found in real silicon, and assuring design simplicity. We have proposed a fully X-tolerant test response compaction scheme which is based on a flexible scan chain selection mechanism. This new approach delivers extremely high compression of test results by observing that X states are typically not randomly distributed in test responses. Identical or similar patterns of correlated X states let the proposed scheme reduce the size of a scan chain selector and the amount of test data used to control it. It handles, moreover, a wide range of unknown state profiles such that all X states, including those being clustered and of high density, are suppressed in a per-cycle mode without compromising the test quality.

This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during all phases of scan test: loading, capture, and unloading. In particular, we introduce a new on-chip continuous-flow decompressor. Its synergistic use with a power-aware scan controller allows a significant reduction of toggling rates when feeding scan chains with decompressed test patterns. While the proposed solution requires minimal modifications of the existing design for test logic, experiments indicate that its use results in a low switching activity which reduces power consumption to or below a level of a functional mode. It resolves problems related to power dissipation, voltage drop, and increased temperature. Our approach integrates seamlessly with test logic synthesis flow, and it does not compromise compression ratios. It fits well into various design paradigms, including modular design flow where blocks come with individual decompressors and compactors.