Search

A negative feedback circuit using one operational amplifier has its Q factor enhanced through the introduction of an additional voltage amplifier with positive finite gain in the feedback loop. The new network has two useful outputs. If a twin-T is connected in cascade with the network input terminals the overall circuit is suitable for the realization of biquadratics or third-order low-pass elliptic functions. The network sensitivity is very low.
It is well known that the main problem with most active networks is their sensitivity to variations in their component values. Certain negative feedback active networks have low sensitivity but suffer from low selectivity for a practical range in the values of their components. This disadvantage prevents the use of these networks in the realization of high selectivity filters. It is possible to improve the selectivity of such circuits by introducing positive feedback (Geffe 1968), but this method also results in higher network sensitivities. In this paper the selectivity of a well-known second-order active section is increased without the use of positive feedback and without de-rating the network sensitivity. Although the resulting section is not completely new, it is thought that the method of deriving it is new and very useful, and that its features and use in the realization of third-order elliptic filters and biquadratic functions are worth mentioning. Experimental results are also included. [ABSTRACT FROM AUTHOR]

Amplifiers with a single twin-T in the feedback path are analyzed using root locus methods. A design approach has been suggested for realizing high-Q transistorized active filters resulting in a three-transistor configuration with a stable Q of 200. The behavior of parallel and cascade configurations of two twin-Ts are studied with a view to realizing stagger tuned band-pass characteristics. It is found that frequencies of selection of the system are much different from the null frequencies of the two twin-Ts. This behavior is explained using root locus techniques. The difference frequencies for various separations and loop gains have been tabulated. Finally it is concluded that stagger tuning can be realized only by connecting separate high-Q filters in cascade.
The conditions under which the twin-T operates efficiently as the feedback network in transistor circuitry has been analyzed An approach to the design of high-Q transistorized active filters has been suggested resulting in the development of a three-transistor circuit having a Q of over 200 at 10 kc/s.
It has been proved, using the root locus method, that parallel or cascade configurations of two symmetric, balanced twin-Ts in the feedback path of an amplifier, do not result in a double hump type of bandpass characteristic. Such a characteristic is found to be realized only by connecting in cascade separate high-Q selective filters which have been slightly stagger tuned. This results in a characteristic with a very sharp fall and steep skirts. [ABSTRACT FROM AUTHOR]

An analytical criterion for the optimization of the small-signal settling time in three-stage amplifiers is carried out. The criterion is based on making equal the two exponential decays of the step response. Including slew-rate effects, a useful design strategy for the design of three-stage operational transconductance amplifier is provided. Extensive time-domain simulations on a transistor-level design in a 65-nm CMOS process confirm the validity of the proposed approach. [ABSTRACT FROM AUTHOR]

In this paper, we provide a new procedure that allows to design a generic three-stage amplifier from settling-time specifications. The procedure analyze the settling-time of pure two- or three-pole amplifiers (i.e., with no zeros) and extends the results to a generic amplifier that includes one or two zeros even placed in the right-half plane. The validity of the proposed approach is demonstrated through a design example of a three-stage CMOS amplifier suitable for switched-capacitor applications. [ABSTRACT FROM AUTHOR]

This letter comments on the recently published paper in [] which provides realizations of minimum component quadrature sinusoidal oscillators. On re-examination of the 'Type 3' oscillator circuits in [], it has been found that the circuits actually suffer from 'latch up' problem due to use of incorrect polarity of the CCII based negative-impedance convertor. This problem has been corrected (without altering the characteristic equation) by swapping the impedances at y and x terminals. Explicit quadrature current outputs are derived similarly as done in []. [ABSTRACT FROM AUTHOR]

In a recently published paper (Abuelma'atti, Analog Integr Circuits Signal Process 65:419-428, 2010) the start-up conditions for a class of sinusoidal RC oscillators are discussed. In this context, the validity of the well known Barkhausen condition for oscillation is challenged. In this comment some of the author's conclusions are critically reviewed and the applicability of the Barkhausen criterion is demonstrated. [ABSTRACT FROM AUTHOR]

We present the results of measurements of the scattering parameters of microstrip amplifiers (MSAs) based on the dc superconducting quantum interference device. The amplifier input impedance is poorly matched to typical transmission line impedances, resulting in high input return loss around -2 dB. We show that negative feedback can lower the MSA input impedance to achieve a robust match to 50 Ω. In the presence of capacitive and inductive feedback, the input return loss of the MSA can be reduced below -10 dB, opening the door to the practical use of the MSA for a variety of demanding applications. [ABSTRACT FROM AUTHOR]

We propose and demonstrate the scheme to combine a two-staged amplifier with a fixed gain flattening filter and two parallel optical feedback loops. This amplifier all-optically controls constant signal gain and gain level through all C-band with a dynamic input power range of up to -1 dBm while input signals are dynamically changed between one channel and 40 wavelength-division-multiplexing channels. The transient effects of each channel and their wavelength dependency are investigated. It is shown that the amplifier can be used in real field applications through transmission experiments, in which the amplifier performance is kept unchanged under wide dynamic traffic variance. [ABSTRACT FROM PUBLISHER]

A wideband low-noise amplifier (LNA) with shunt resistive-feedback and series inductive-peaking is proposed for wideband input matching, broadband power gain and flat noise figure (NF) response. The proposed wideband LNA is implemented in 0.18-mum CMOS technology. Measured results show that power gain is greater than 10 dB and input return loss is below -10 dB from 2 to 11.5 GHz. The IIP3 is about +3 dBm, and the NF ranges from 3.1 to 4.1 dB over the band of interest. An excellent agreement between the simulated and measured results is found and attributed to less number of passive components needed in this circuit compared with previous designs. Besides, the ratio of figure-of- merit to chip size is as high as 190 (mW-1 /mm2 ) which is the best results among all previous reported CMOS-based wideband LNA. [ABSTRACT FROM PUBLISHER]

The effect of channel add/drop response on a new and novel type of narrowband ASE feedback EDFA is investigated. This gain-clamped amplifier utilizes multiple fiber Bragg gratings (FBGs) in a simulated eight-channel WDM network. This experiment demonstrates that in order to minimize variation of surviving-channel power to less then 0.28 dB for channel add/drop, the ASE feedback attenuation level and pump power are critical. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 45: 307–309, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20805 [ABSTRACT FROM AUTHOR]

A highly linear BiCMOS double balanced mixer for direct conversion applications is described and optimized. Based on the combination of active and resistive concepts, and modeled as a variable feedback amplifier, it achieves a high linearity and a good conversion gain. The performances achieved are; a conversion gain up to 12 dB, an output P-1 dB of -5 dBm, and a high linearity, with an OIP3 of about +23 dBm and an OIP2 not less than +54 dBm, while requiring a local oscillator power no more than +4 dBm. As it covers a broadband RF spectrum, it can be used for receiving all communication networks located from 0.9 GHz until 2.2 GHz. When active, it drains 6 mA from 3.6 V. [ABSTRACT FROM PUBLISHER]

Exact formulae are presented for both maximum available gain (Gma) and unilateral gain (U), which include both the magnitude and phase angle of the S21 parameter. The result for Gma is not unique since there are many possible solutions to simultaneously match S11 and S22 when k>1. For the phase angle of U, the result tends to become 180° when using the topology of a variable coupler, a line stretcher, and a feedback amplifier. From the verifications, an amplifier using the unilateralizing technique will achieve 4-6 dB higher gain than that of the Gma amplifier. [ABSTRACT FROM PUBLISHER]

Provides information on a study which presented a universal biquadratic filter configuration using two current-feedback amplifiers. Methodology of the study; Results and discussion on the study; Conclusion.

A novel approach to achieve high‐efficiency dual‐band power amplifier (PA) is presented. Owing to the contradictions among the control of harmonics, most reported dual‐band or multi‐band PAs are intentionally avoiding the case when the higher‐frequency band overlaps the second harmonics of the lower‐frequency band, especially when fhigher=2flower. By introducing lower‐frequency feedback technique a method is proposed, make a compromise between high‐efficiency and power gain fluctuant, high‐efficiency dual‐band PA at the above condition can be achieved. To verify, a dual‐band PA operating at 1.7 and 3.4 GHz is fabricated and measured. The peak output powers of the dual‐band are 40.1 and 40.7 dBm with small signal gains 25 and 17 dB, and the drain efficiency at the peak output power reached 80.2 and 78.5%, respectively. [ABSTRACT FROM AUTHOR]

Extends the applicability of K.S. Yeung's approach for analyzing feedback circuits by proposing two transformations necessary for voltage-series and current-shunt feedbacks. Description of Yeung's procedure for analyzing feedback amplifiers; Characterization of the current-shunt feedback.

Describes the neural network detector with its training procedure and shows its detection performance in comparison with an multi-level decision feedback equalization (MDFE) detector. Structure of the neural network detector and a processing unit; Results and discussion; Conclusion.

Focuses on a novel representation for two-pole feedback amplifiers, emphasizing the necessity of the representation as it pertains to pedagogical an design purposes. Assessment of the closed-loop amplifier and its open-loop transfer function.

Circulators are often used in RF systems; however, their size, cost, and weight increase greatly at lower frequencies (<300 MHz). The development of a load‐insensitive active quasi‐circulator is presented as an alternative for the traditional circulators to be used in low‐frequency systems such as Doppler ultrasound. Major challenges to these active devices are limited power and low isolation between non‐consecutive ports. The use of current‐feedback operational amplifiers allowed higher‐power delivery to the load. Simulations using Monte Carlo method showed an isolation >19 dB for 20% of variation of the load impedance. The circuit was implemented and tested with an ultrasound probe in a water tank. The results show that the circuit was able to send and receive signals simultaneously from a single ultrasound transducer element. [ABSTRACT FROM AUTHOR]

A 60 GHz low-noise amplifier (LNA) using standard 65 nm CMOS technology is presented. A gain of the 60 GHz amplifier was boosted by using a transformer feedbacked capacitor neutraliser. To stabilise the process variations caused by the positive feedback system, the body node of the triple well was adjusted to tune the capacitor value. The theory, simulation and measurements are presented. An implementation prototype is evaluated using on-wafer proving. The LNA showed a measured peak gain of 30 dB and a measured noise of 4.6 dB under 8.9 mW power consumption with a 1 V supply voltage. The measured IIP3 was -26 dBm. This is believed to be the first CMOS 60 GHz LNA to compensate the overlap capacitor with a single-ended structure. [ABSTRACT FROM AUTHOR]

A class EF2 power oscillator designed in standard 130 nm CMOS at 2.5 GHz frequency is presented. The oscillator relies on a direct path based on a power amplifier and a feedback path based on passive elements and an MOS varactor. Class EF2 is used to reduce voltage stress across the switch, enabling a higher output power for modern transistors with low breakdown voltage. The measurement on a class EF2 power oscillator at radio frequency (RF) is presented for the first time. The circuit achieves 17.65 dBm output power from a 2.5 V supply voltage with 27.1% DC‐RF efficiency and presents a 150 MHz tuning range. The measured phase noise is −101.6 dBc/Hz at 1 MHz offset. The circuit was implemented in standard 130 nm CMOS technology and consumed a total area of 1.95 mm2. To the authors' knowledge this class EF2 power circuit has never been presented either at RF frequencies or in an integrated technology. [ABSTRACT FROM AUTHOR]

A compact reconfigurable CMOS low‐noise amplifier (LNA) is presented for applications in DCS1800, UMTS, WLAN‐b/g and Bluetooth standards. The proposed LNA features first a current reuse shunt‐feedback amplifier for wideband input matching, low‐noise figure and small area. Secondly, a cascode amplifier with a tunable active LC resonator is added for high gain and continuous tuning of bands. Fabricated in a 0.13 μm CMOS process, the measured results show >20 dB power gain, <3.5 dB noise figure in the frequency range of 1.8–2.4 GHz, return losses S11 and S22 lower than −12 and −14 dB, respectively, with a moderate IIP3 of −11.8 dBm at 2.4 GHz. It consumes 9.6 mW from a 1.2 V supply voltage, while occupying an active silicon area of only 0.052 mm2. [ABSTRACT FROM AUTHOR]