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To develop efficient Li-ion powered systems, Cell testing and charactering are required to evaluate cell performance. However, testbenches are really expensive and test procedures provided are not the ones expected. In this article, we propose a testbench design based on Instrumentation software and hardware co-design. An efficient charging and discharging hardware has been proposed and developed by using a remotable laboratory supply as main virtual component. Software mechanisms are explained where the test procedures are detailed. in a second part. Acquisition constraints for measuring equipment are also specified in order to obtain relevant and valid data.

The cell management is as much important as the cell charge method. In order to manage effectively cell, a good knowledge of cell behaviors is required. Behaviors - electrical and thermal - are captured by the cell model. Cell modeling is very common in literature, but parameters extraction is not precisely explained. This paper will deal at first with an electro-thermal model based on extended Kalman filtering (EKF), which can allow to extract parameters, and in a second time with a fast and accurate measurement procedure.

Power production based solar cells are sensitive to temperature. In real conditions, the effective Photovoltaic (PV) module operating temperature is affected by randomly varying of solar radiation, ambient temperature and wind speed. Thus, the energy balance of photovoltaic (PV) cells and the associated power production is mainly modeled based on climate variables. This paper investigates the experimental influence and relationship of the temperature and solar radiation changing effects on the system performance in terms of power production of PV cells. An experimental approach leading to an expression models the energy transfer processes and electrical energy production for one specific site is studied. The proposed gait is reproducible and suitable on different site. Our study is based on experimental results set up of 6 PV (1 kW) multicrystallin silicon panels under existing conditions and not indoor conditions. 2 with a temperature of 25˚C. However, in the real world, these conditions are constantly changing. Therefore, the panel output is different from the laboratory conditions. Thereby, most previous works in the literature mainly have studied the thermal model in order to modeling and characterizing the behaviors of the various thermal effects and exchanges (through radiation, convection, conduction) of the PV cells (usually amorphous silicon area) in order to knowing the energy production according to climate conditions. However, few of them model the prediction of energy production from trend of thermal behaviors in function of the prediction prevailing weather conditions and surrounding environment. Therefore for determination of the expected energy production from exact temperature of PV cells, It is necessary to provide a suitable real model of the PV cells behaviors in order to predict electrical energy that can be supplied. To develop efficient renewable and sustainable energy for power production systems, the strong understanding of electro-thermal behaviors of the PV is required. Indeed, a behavior model compared to experimental measurement results contributes to predict the current and power production variations which must be taking into account in the sizing installation and manufacturing of solar energy production system, and energy distribution network based on PV. This paper investigates the experimental relationship of the temperature conditions (and thus solar radiation changing effects) on the system performance in terms of power production of PV cells in order to predict the potential of electric production for a given specific PV cell technology and according to the site of solar exposure .In this paper, we focus this work mainly on experimental observations of the temperature influence (5, 6) on the global efficiency (7), and thus on electrical power production. Thus, an experimental approach leading to an expression models the energy transfer processes and electrical energy production for one specific site and varying the time is studied. The rest of this paper is organized as follows. Section II presents the temperature effect on electrical current and power production. Section III describes the experimental PV modeling based on parameter value extraction depending temperature influence of real PV silicon cells varying in the time for one specific site. The details of the procedure measurement for determining the PV characteristics through experimental results are given in this section. In this Section, experimental measurements under real conditions are performed to quantify the relationship influence of the temperature in term power production. Finally, a conclusion is given in section IV.

Communication in networked systems must be reliable during run time data exchanges. Therefore, their specifications and designs must be clear, understandable and follow specific rules. Indeed, these systems must guard against potential failures in preventing faults and associated errors, failures or allowing a degraded operating modes in order to protect against global system failures while maintaining a minimum of functionality in the case of irreversible failures, thanks to fault tolerant and security mechanisms. Given challenges of verification by simulation of these complex systems have made the huge number of possible states of carrying operation, and to ensure reliability requirements, we propose a formal proof verification as an alternative operation and validation blocks against defects through one proposed self-adaptive fault tolerance paradigm suitable for occurred errors of networked embedded systems. The formalization process based on an incremental and validated correct-by-construction development of the proposed reliability mechanisms are designed and proved in order to ensure accuracy operating required related dependability of communication wireless networked systems.

International Conference on Control, Decision and Information Technologies (CoDIT), Ecole Natl Ingenieurs Metz, Metz, FRANCE, NOV 03-05, 2014; International audience; The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. So the current challenge is to design of new digital architectures, in addition to its ability to take over of many functions. In this paper we have identified similarities between the despreader units in Rake receiver and the processor element in FFT-SDF (Fast Fourier Transform-Single path Delay Feedback) to propose a generic architecture shared between the two algorithms widely used. This Smart architecture is interconnected with similar modules by a 3D Network-on-Chip for implementation of Rake receiver (used in WCDMA system) and FFT receiver (in OFDM system). We present in this paper a 3D-NoC with half layer-layer connection, this architecture uses a modified XYZ routing algorithm. The proposed architectures are coded using VHDL onto a Virtex 5 Field-Programmable Gate Array (FPGA) device and results are compared with similar works. The implementation demonstrates that the proposed architectures can deliver a high reduction of the FPGA logic requirements with high maximum frequency.

This paper concerns the design and the implementation of a transimpedance amplifier (TIA) dedicated to detector of Near Infrared spectroscopy (NIRS). To reduce the effect of the input capacitance on the bandwidth, a bias circuit with low input impedance is connected to input stage. A single ended common source common gate input stage based on a cascode structure is used to get a higher gain bandwidth closed loop transimpedance amplifier. In addition, a higher open loop gain is got by adding second active load. To increase noise circuit performance, a feedback single transistor technique is considered. The TIA is implemented in 0.18 mu m CMOS process. Simulation results show a transimpedance gain of 104.2 dB Omega, -3dB bandwidth of 19 MHz and an equivalent input noise current spectral density of 446 fA/root Hz. A comparative study confirms the feasibility of our proposal.

In this paper, a self-organized reliability technique is presented to test the Network on Chip (NoC) parts of networked reconfigurable MPSoC. We propose a new mechanism based on delocalized offline tests to detect and locate permanent errors in the NoC through networked multi-nodes system. Concepts and mechanisms of the proposed approach are detailed in the case of a network system based on Zigbee wireless communication where error detections and timing performance are giving.

Like all semiconductor devices, solar cells are sensitive to temperature. In actual installations the cell temperature rises leading to a total efficiency reduction, which cannot be overlooked. This paper investigates the influence of the temperature and solar radiation changing effects on the system performance. Our study is based on experimental results set up of 6 PV multicrystallin silicon panels under existing conditions and not indoor conditions.

Nowadays, the current challenge in the wireless digital systems is to design new digital, generic and “universal” architectures, take charge of functionalities previously managed by different circuits. Moreover, these ones must be sufficiently flexible to support multiple transmission standards and easily adaptable for future evolutions. In this work, we propose a digital architecture for modulation and demodulation using LFSR registers. The architecture was implemented on Xilinx Virtex series field programmable gate arrays (FPGA). The implementations demonstrate that our proposed architecture can deliver a high reduction of the FPGA logic requirements and consumption power when compared with the Velcro architecture.

Li-ion rechargeable batteries present an useful energy, low battery effect, and slow Self-discharge loss of charge when not in use. In this paper, we describe a VHDL-AMS model describing coupled electrical and thermal behaviors of a Li-Ion cell. This model relies on the experimental extraction of real characteristic parameters by using an efficient and low-cost test bench. Therefore, it allows to predict the realistic voltage variations by taking into account the state of charge and heating of the Li-ion cell, in order to design a battery system according the required capacity and electric power for the current electrical applications.

This paper proposes a new reliable router allowing accurate online error detections in dynamic Network on Chip (NoC). The proposed router has the capability to detect and localize accurately inner or outer data packet errors of the router while distinguish between temporary and permanently errors. The error detection mechanisms of the proposed switches and advantages with regards to the other main already proposed router approaches are detailed while proving the feasibility and efficiency through several simulations online detection cases. Performance evaluation and FPGA implementation results are also given.

This paper presents a self-organized reliability technique to efficiently handle error localization in a Wireless Networked MPSoC. The wireless multi-node system consists of several nodes integrating MPSoC based Network-on-Chip (NoC) and communicating through ZigBee communication. We focus on the error detection and localization in NoCs located in each node of the wireless multi-node system. We propose a new offline test mechanism to efficiently detect and locate permanent errors in the networked NoCs. The proposed mechanism relies on delocalized tests performed through ZigBee wireless communication. We give the basic concepts of the proposed approach and timing estimations.

We propose in this paper a new hardware architecture for implementing the hyperchaotic Lorenz generator using FPGA technology. The goal is to design a new complex chaotic system which can be used as an unidentifiable key generator in embedded cryptosystems. The proposed architecture provides good performances in terms of throughput and resources cost required for highly secure communications between embedded systems.

In this paper, a new robust additive hyperchaos masking algorithm for secure digital chaotic communications is proposed and implemented in FPGA technology. Through the hardware implementation, we determine the experimental conditions to ensure hyperchaotic synchronization and robust securing of embedded communications. The obtained real-time results under these conditions confirm the effectiveness of the proposed solutions.

A critical process in real-time optical microscopy applications, such as cancer cells detection, is the determination of a cells position in the histopathological image. Aiming at low-cost and efficiency, a proof-of-concept study was done to distinguish between normal and abnormal cells based on optical microscopy at the LICM laboratory. A snake/active contour method was developed in which several curves move within images to find normal/abnormal cell boundaries. Abnormal cell identification typically takes more than one hour, however an implementation on FPGA technology solves this problem. A novel embedded architecture of the snake method was developed for an efficient and fast computation of active contour used in high throughput image analysis applications, where time performance is critical. This architecture allows for a scalable and a totally embedded processing on FPGA of a large number of images. The architecture of the snake method was able to detect objects from images which have irregular shapes, such as carcinoma cell types. To demonstrate the effectiveness of the approach, the architecture was implemented on Xilinx ISE 12.3-FPGA technology using VHDL structural description. It shows the possibility of using the snake method implementation on FPGA technology to detect abnormal cells in real time.

The parameters extraction defined by Haralick in textural analysis of bio-images often precedes a decision step to be able to distinguish normal or defective tissues, healthy or pathological biological cells and the types of defects. In this paper, we focus on the textural analysis of medical images, in order to detect abnormal blood cells using grey-level co-occurrence matrix (GLCM). The textural analysis is performed by quantifying correlations and relationships between grey levels of pixels depending on the distance. Our purpose is to develop a method based on the computation of Haralick's textural parameters in order to characterise and analyse blood cells by statistical methods. The main goal is to provide textural analysis to help haematologists to make a precise diagnosis allowing to identify anomalies by distinguishing healthy and abnormal cells which can be considered as potential cancerous cells. The results described in Figures 3-7 show one set of significant experimental results which are useful to differentiate between healthy and abnormal cells, and where the strong main parameter is the energy.

In this paper, a model is proposed to perform the Self-Organized Systems (RSS) by using the reconfigurable hardware architectures in a Wireless Sensor Network (WSN) environment. The evaluation performance provide information on the utilization of auto-reconfigurable architecture in WSN using the ZigBee Protocol. The proposed system is designed to study at each level, parameters that influence performance. Thereby, the evaluation platform is described in order to provide data on expected performance and finally the timing analysis shows the limitation in terms of networked computation. Index Terms - FPGA, WSN, Self-organized system, Zigbee.

In this paper, we present a comparative analysis of FPGA implementation performances, in terms of throughput and resources cost, of five well known autonomous continuous hyperchaotic systems. The goal of this analysis is to identify the embedded hyperchaotic generator which leads to designs with small logic area cost, satisfactory throughput rates, low power consumption and low latency required for embedded applications such as secure digital communications between embedded systems. To implement the four-dimensional (4D) chaotic systems, we use a new structural hardware architecture based on direct VHDL description of the forth order Runge-Kutta method (RK-4). The comparative analysis shows that the hyperchaotic Lorenz generator provides attractive performances compared to that of others. In fact, its hardware implementation requires only 2067 CLB-slices, 36 multipliers and no block RAMs, and achieves a throughput rate of 101.6 Mbps, at the output of the FPGA circuit, at a clock frequency of 25.315 MHz with a low latency time of 316 ns. Consequently, these good implementation performances offer to the embedded hyperchaotic Lorenz generator the advantage of being the best candidate for embedded communications applications.

In this paper, we evaluate the broadcast delivery of Scalable Video Coding (SVC) stream over the DVB-T2 system, using differentiated robustness for each SVC layer based on the DVB-T2 MPLP mechanism. Laboratory measurements and field tests are done for this concept. Mobile reception is evaluated both in laboratory conditions using the TU6 channel and in the field at a limited speed which the current receiver's implementation can support. Fixed reception is evaluated in laboratory conditions using the Rice channel. For the laboratory and field tests and for the two considered reception profiles (mobile and fixed), we compare the results in the case of SISO, SFN and Alamouti MISO network configurations by considering two antennas. Coverage areas for the field measurements have been predicted for each reception profile and each layer, based on the laboratory sensitivity measurements. The field tests allowed experimenting the receiver switching from enhancement layer to base layer and vice-versa, leading to a change of image quality and resolution depending on the reception area and on the channel characteristics in the studied area. Therefore, the receiver decodes always an image but with different quality and format. We also experiment SISO, SFN and MISO networks configurations, and show a differentiated impact on the coverage area or on the performance gain.

The automatic recognition and classification of biomedical objects can enhance work efficiency while identifying new inter-relationships among biological features, in this paper Haralick's features based GLCM are applied for classification of cancer cell of textured bio-images. The objective of this work is the selection of the most discriminating parameters for cancer cells. A new approach aiming to detect and classify colon cancer cells is presented. Our detection approach was derived from the "Snake" method but using a progressive division of the dimensions of the image to achieve faster segmentation. The time consumed during segmentation decrease to more than 50%. The efficiency of this method resides in its ability to segment Carcinoma (Ca) type cells that was difficult through other segmentation procedures. Classification of three cell types was based on five Haralicks features, only three Haralicks features were used to assess the efficiency classifications models, including Benign Hyperplasia (BH), Intraepithelial Neoplasia (IN) that is a precursor state for cancer, and Ca that corresponds to abnormal tissue proliferation (cancer). The analysis results show that three parameters (correlation, entropy and contrast) were found to be effective to discriminate between the three types of cells. The results obtained show the efficacy of the method.

Image analysis in cancer pathology applications has evolved considerably in the last years [1]. The areas concerned were particularly those in which the diagnosis was based on the medical image processing and analysis. Few studies have successfully investigated the automatic classification of colonic pathology images if they contain healthy cells or cancerous cells. The objective of this work is the multispectral images classification of healthy and cancerous cells in order to accelerate the operations of classification between different types of cancerous cells. Our detection approach was derived from the "Snake" method but using a progressive division of the dimensions of the image to achieve faster segmentation. The time consumed during segmentation was decreased to more than 50%. We extract several Haralick's coefficients to detect the type of cells were made segmentation are applied to the multispectral image. The experimental results obtained on several multispectral images show that the method is efficient for the classification of cancer cells of type Carcinoma (Ca), Intraepithelial Neoplasia (IN) and Benign Hyperplasia (BH).

This paper proposes a new Cryptosystem for encryption of the real-time embedded applications. The proposed hardware architecture is based on a chaotic rule switching of several three-dimensional continuous chaotic data generators. The originality of the proposed approach is a new stream chaotic key generator used for real time data encrypt and decrypt. Our architecture, implemented in Virtex Xilinx FPGA technology, is particularly attractive since it provides a very low-cost security solution while holding or increasing the throughput rate encryption. Moreover, the application and experimental results for speech encrypted signal effectively hides the original speech signal after synchronization between the transmitter and the receiver which decrypted recovers the original speech signal with reasonable inteligibility.

We present a new reliable high-performance interconnection approach destined for complex System on Chip based on the network-centric approach. The originality of our approach is to avoid the lost of data packets, detect routing errors and reduce data packets latency by emptying output buffer when the neighbour router is unavailable. We present the basic concepts of the reliability communication technique and FPGA implementations.

In this paper, we evaluate and compare the performances of different network combinations from the usage of coded MISO (Multiple Input Single Output) in a Single Frequency Network (SFN) for DVB-T2. We address classical SFN and different MISO-SFN network combinations. We mean by different combinations, the organization and position of antennas where some of them transmit the same symbols and others transmit modified symbols as defined by the DVB-T2 standard for Alamouti MISO. The number of combinations depends on the number of transmitters. Evaluations of the path loss are also given in this paper. We also propose an additional table of these combinations in the T2-Gateway. The simulations are done for three and four transmitters where there are four combinations for three transmitters and eight combinations for four transmitters. The results show clearly that the performances of the received signals depend on the network combinations and the difference can be higher than 2 dB.

In this paper, we present a new reliable and dynamic NoC-based communication approach called RCuNoC designed for the FPGA-based reconfigurable systems. The originality of the RCu routers are the online capacity to detect data packet errors and localize if the errors come from input ports or inside of the routers while distinguish between temporary and permanently errors. Our reliable router which requires a low-area architecture is based on the centralization of the buffer, routing logic and error detection/correction/localization blocks. We present the basic concept of the RCu switches, its main advantages and with regards to the other main already proposed dynamic NoC approaches and we prove its feasibility on examples through the simulations. Performance evaluation and FPGA implementation results are also given.

In this paper we present an alternate Network-on-Chip switch incorporating a new on-line routing error detection technique. This router implements an adaptive routing algorithm suitable for MPSoC architectures in which dynamic and partial reconfiguration is allowed. The originality of the detection mechanism resides in the capacity to distinguish routing errors from adaptive decisions (to bypass faulty or reconfigurable areas). Moreover, the mechanism is able to detect the failing directions in the faulty switches allowing to not disconnect the entire faulty router. Here, we present the new proposed RTL router architecture with the corresponding error detection algorithm, several study cases being detailed. The implementation results clearly show the pertinence of the approach, an effective tradeoff between hardware overhead and failure detection capacity being reached in this new reconfigurable NoC.

DVB-T2, second generation of terrestrial digital video broadcasting standard, promises performance gains because of improved coding, modulation and multiple antenna technologies. This paper proposes a simulation and evaluation performance of the DVB-T2 in order to address the improvement of DVB-T2 compared with DVB-T in a single frequency network (SFN) transmission for receiving signals having the same data rate. These simulation results are obtained from the CSP DVB-T2 platform by using a model of an SFN network transmission based on two, three and four antennas. The obtained results with our considered configuration show clearly that in the case of two, three or four transmission antennas, the performance of SNR is average increased about 10 dB compared to DVB-T with the same data rate. This improvement allows to reduce the transmission power compared to DVB-T transmission or to increase the coverage of the receive area of an SFN network.

In this paper we present a new efficient online routing error detection approach dedicated to fault tolerant routing algorithms for the 2-D mesh reconfigurable Network-on-Chip interconnections. The main contribution is to distinguish a routing error due to switching failure from an adaptative routing decision (bypassing a faulty area or reconfigurable region in the NoC). The originality of our approach is that it can be applied to all adaptative routing based on modified turn model and well known XY algorithm, and allows the routing of messages in the networks incorporating the regions not necessarily rectangular.

This paper proposes a new and efficient way to deal with the chaotic synchronization for embedded hardware cryptosystems and its FPGA implementation for designing a real time image secure symmetric encryption scheme. The implementation and experimental results mapped on two Xilinx FPGA Virtex technology platforms demonstrate the feasibility and the usefulness of our secure solution. The originality of this new scheme is that it allows a low cost image encryption for embedded systems while still providing a good trade-off between performance and hardware resources. Thorough experimental tests are carried out with detailed analysis, demonstrating the high security and fast encryption speed of the new scheme while still able to resist statistical analysis attack.

This paper proposes a new approach for the utilization of reconfigurable hardware in a self-organized context. A concept and a system are presented under the form of Reconfigurable Self-Organized Systems (RSS). The goal is to study the impact of FPGA based systems in a self-organized networked environment. Partial Reconfiguration is used to implement hardware accelerators at runtime. The proposed system is designed to study at each level, parameters that influence performance. As results, first timing measurements of partial reconfiguration are proposed. They are seen from the software point of view and show effects of partial reconfiguration technology on the general performance of RSS.

This paper proposes a new approach for real time FPGA implementation of a new chaotic generator characterized by a new three-scroll chaotic attractor. The originality of this chaotic generator is that is obtained with some bifurcation parameters of Duffing's chaotic oscillator. Our new chaotic attractor shows the richness chaotic behavior of the Duffing's oscillator. In addition, its hardware implementation using Virtex Xilinx FPGA technology is particularly attractive since it provides good performances in terms of throughput and resources cost required. This particularity allows lowing power consumption especially for embedded applications.

International audience; In this paper, we present a new deadlock-free fault-tolerant adap-tive routing algorithm for the 2D mesh NoC interconnections. The main contribution of this routing algorithm is that it allows both, routing of messages in the networks incorporating the regions not necessarily rectangular, and routing to all nodes which are not completely blocked by faulty nodes. The proposed routing algorithm is based on a modified turn model and well known XY algorithm. We detail the basic principle of this routing algorithm, prove its deadlock freeness, its feasibility and efficiency through the simulation results.

In this paper, we present a new approach for realtime FPGA implementation of the random key based Lorenz's chaotic generator for data stream encryption. We propose a structural hardware architecture designed for a small chip area and high speed performance. This architecture is particularly attractive since it provides a low-cost security telecommunication solution while holding or increasing the encryption throughput rate. We show its feasibility through implementation which is detailed and presented using Virtex Xilinx FPGA. This architecture employs only 1926 slices and allows achieving a random key throughput rate of 124 Mbps by using a low system clock with a frequency of up to 15,5 MHz allowing low power consumption especially for embedded applications.

The growing complexity of integrated circuits imposes to the designers to change and direct the traditional bus-based design concepts towards NoC-based. Networks on-chip (NoCs) are emerging as a viable solution to the existing interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in the literature are destined to System-on-chip (SoCs) designs. For a FPGA-based system, in order to take all benefits from this technology, the proposed NoCs are not suitable. In this paper, we present a new paradigm called CuNoC for intercommunication between modules dynamically placed on a chip for the FPGA-based reconfigurable devices. The CuNoC is based on a scalable communication unit characterized by unique architecture, arbitration policy base on the priority-to-the-right rule and modified XY adaptive routing algorithm. The CuNoC is namely adapted and suited to the FPGA-based reconfigurable devices but it can be also adapted with small modifications to all other systems which need an efficient communication medium. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main already proposed NoC approaches and we prove its feasibility on examples through the simulations. Performance evaluation and implementation results are also given.

The MPEG transport stream is an extremely complex structure using interlinked tables and coded identifiers to separate the programs and the elementary streams. Quality management is therefore a complicated issue and the need to identify the degree of coding degradations in terms of coding and/or transmission errors or system failures is becoming an important criterion for the evaluation of the quality of the MPEG streams. A theoretical decoder (T-STD) defines the verification process based on the proper fill level of an MPEG decoder buffers whose size is defined by the standards in order to obtain an evaluation of the MPEG stream quality. This paper describes a new embedded and programmable solution capable of analysing MPEG streams in real time. The proposed hardware architecture provides a real time continuous buffer analysis of the MPEG stream components and is composed of several modules allowing for simultaneous modeling of the various buffers of the T-STD components (video, audio or system). Real time errors flags are generated when the buffers filling level becomes illegal (overflow, empty buffer, transfer delay, etc.). The architecture has been modeled, validated and simulated using the SystemC and VHDL languages in combination with real MPEG DVB-T streams. A VHDL synthesisable model of our architecture allows an implementation on an field-programmable gate array circuit based on Altera APEX20K1000. The hardware implementation of this configurable T-STD allows a data rate of 232 Mbps and requires only 9738 logical cells and 4,7 kB memory.

Chaos-based encryption has suggested a new and efficient way to deal with the problem of fast and highly secure image encryption. In this paper, a new chaotic key generator for image encryption and its FPGA implementation based on a chaos switching rule between Lorenz's and Lm's non-linear systems is proposed for designing a real-time secure symmetric encryption scheme. The originality of this new scheme is that it allows a low cost image encryption for embedded systems while still providing a good trade-off between performance and hardware resources. Our experimental results have demonstrated the feasibility and the efficiency of our secure solution on Xilinx FPGA virtex technology. Thorough experimental tests are carried out with detailed analysis, demonstrating the high security and fast encryption speed of the new scheme while still able to resist statistical and Key analysis attacks.

Reconfiguration latency is an important factor which impacts the system performance in the reconfigurable computing design. In this paper, a framework is proposed that presents a novel approach for an optimal implementation of algorithms on FPGA based reconfigurable system. The method optimizes the temporal partitioning by performing a similar-rate-computing-based architectural synthesis. It gives the possibility to merge the related partitions during the implementation of a target architecture by the architectural synthesis based on reusing of the common task. Our approach proposes a final solution based on the computation of the mutual similar rate (M.S.R.) for a RTR implementation with a synthesis option. The proposed approach attempts to reduce the number of the temporal partitions for minimizing the overall execution time. An example is presented to illustrate this novel approach. With the architectural synthesis, the number of partition was decreased. The results demonstrate that are capable and efficient for an optimized implementation in the reconfigurable design.

Networks on chip (NoCs) present viable interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in literature are mostly destined to system-on-chip (SoCs) designs. For a FPGA-based reconfigurable system, the proposed NoCs are not suitable. In this paper, we present a new high-performance interconnection approach destined for FPGA-based reconfigurable system. Our proposed NoC is based on a scalable communication unit characterized by its particularly architecture, an arbitration policy based on the priority-to-the-right rule and high performances. We present the basic concept of this communication approach and we prove its feasibility on examples through the simulations. Implementation results are also detailed.

In this paper, we propose a VLSI architecture and an FPGA implementation of a hybrid message-embedding (HME) self-synchronizing stream cipher encryption based on a switched linear congruent pseudo-random generator. This encryption, which is based on a chaotic scheme, is particularly attractive since it provides the same security as any conventional self-synchronizing stream cipher requiring only additions, subtractions, multiplications and word-switch operations. We show its feasibility and its implementation which are presented and detailed by using Altera FPGA technology for a set of parameter numbers (switching and key component number). We also show the parametrable of the HME in order to obtain the appropriate security and a the best trade off between the smallest FPGA logical area and the best throughputs rate for embedded applications.

Over the last decade, major advances have occurred in face recognition and a large number of algorithms have been proposed to achieve acceptable recognition rates under controlled conditions. However, a successful application under real world conditions remains a challenge. To address this problem, a new method for face recognition is presented and is based on Subclass Discriminant Analysis with a Directional Filter Bank pre-processing. Experimental results show that the DFB preprocessing step improves the original SDA method and attractive recognition rates are achieved.

In this paper, we propose a hardware preemptive multitasking mechanism which uses scan-path register structure and allows identifying the total task's register size for the FPGA-based reconfigurable systems. The main objective of this preemptive mechanism is to suspend hardware task having low priority, replace it by high-priority task and restart them at another time (and/or from another area of the FPGA in FPGA-based designs). The main advantages of the proposed method are that it provides an attractive way for context saving and restoring of a hardware task without freezing other tasks during pre-emption phases and a small area overhead. We show its feasibility by allowing us to design a simple computing example as well as the implementation of AES-128 encryption algorithm which are presented in and detailed on the Xilinx Virtex FPGA technology.

International audience; In this article, we present CuNoC, a new paradigm for intercom-munication between modules dynamically placed on a chip for FPGA-based reconfigurable devices. The CuNoC is based on scal-able communication unit called CU which allows the simultaneous communication between several processing elements placed on the chip. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main NoC approaches already proposed.

In this paper, we propose an FPGA implementation of a hybrid message-embedding (HME) self-synchronizing stream encryption based switched linear congruent pseudo-random generator. This encryption method is particularly attractive since it provides a low-cost security communication solution while increasing the throughput rate and decreasing the area of the FPGA circuit. This technique only requires addition, subtractions multiplication and word-shift operations and does not require the usually costly operations such as exponentiations. We propose an architecture using feedback logic, designed for small chip covered area and high speed performance. We show its feasibility through implementation which are presented and detailed by using Xilinx FPGA technology. This architecture employs only 162 slices with an achieved throughput equalling 659 Mbps by using a system clock with frequency up to 82. 3 7 MHz, a switching number of 4 and a number of key component equal to 2.

This paper presents a strategy for the optimal implementation of algorithms on reconfigurable system based on FPGA technology. The advantage and the originality of our approach are that the implementation obtained combines the execution of algorithm in dynamic reconfiguration realized by temporal hardware partitioning and/or architectural synthesis based on the re-using of the operators. Our approach starts from a CDFG (control-data flow graph) description of an algorithm, and proposes a final implementation based on the computation of the mutual exclusion rate (M.E.R.) parameter for choosing the algorithm parts based on RTR (run time reconfiguration) or AS (architectural synthesis) execution. We also give a general description of the approach. We motivate the effectiveness of this approach by presenting the implementation results of the AES encryption algorithm.

The data security is a significant subject for which various solutions algorithms were proposed. In 2001, Advanced Encryption System (AES) was accepted like a standard FIPS. AES is a symmetrical algorithm of encoding intended to replace DES which had already shown certain faults of safety in the data protection. Since then, of many achievements on hardware and software were proposed by combining various architectures. The throughput reached go from 20 Mbps to 70 Gbps according to technology and architecture used. This article presents an architecture which can be implemented on the FPGA Xilinx XC2V6000, by applying dynamic reconfiguration and reaching a speed of execution of 43 Gbps. This architecture employs only 2xxx CLB' S allowing a considerable economy of the resources.

We have proposed, synthesised an implemented on FPGA a new real time architecture to model the operations of the video stage of a hypothetical decoder T-STD