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Implementation of Universal Digital Architecture using 3D-NoC for Mobile Terminal
- Source :
- CoDIT, The 2014 International Conference on Control, Decision and Information Technologies (CoDIT’14), 2014 INTERNATIONAL CONFERENCE ON CONTROL, DECISION AND INFORMATION TECHNOLOGIES (CODIT), Kacem, I and Laroche, P and Roka, Z. 2014 INTERNATIONAL CONFERENCE ON CONTROL, DECISION AND INFORMATION TECHNOLOGIES (CODIT), Nov 2014, Metz, France. The 2014 International Conference on Control, Decision and Information Technologies (CoDIT’14), pp.595-600, 2014, 〈http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6996962〉, 2014 INTERNATIONAL CONFERENCE ON CONTROL, DECISION AND INFORMATION TECHNOLOGIES (CODIT), Université de Lorraine, METZ, Nov 2014, Metz, France. pp.595-600
- Publication Year :
- 2014
- Publisher :
- HAL CCSD, 2014.
-
Abstract
- International Conference on Control, Decision and Information Technologies (CoDIT), Ecole Natl Ingenieurs Metz, Metz, FRANCE, NOV 03-05, 2014; International audience; The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. So the current challenge is to design of new digital architectures, in addition to its ability to take over of many functions. In this paper we have identified similarities between the despreader units in Rake receiver and the processor element in FFT-SDF (Fast Fourier Transform-Single path Delay Feedback) to propose a generic architecture shared between the two algorithms widely used. This Smart architecture is interconnected with similar modules by a 3D Network-on-Chip for implementation of Rake receiver (used in WCDMA system) and FFT receiver (in OFDM system). We present in this paper a 3D-NoC with half layer-layer connection, this architecture uses a modified XYZ routing algorithm. The proposed architectures are coded using VHDL onto a Virtex 5 Field-Programmable Gate Array (FPGA) device and results are compared with similar works. The implementation demonstrates that the proposed architectures can deliver a high reduction of the FPGA logic requirements with high maximum frequency.
- Subjects :
- RTL modeling
Computer science
Orthogonal frequency-division multiplexing
[SPI] Engineering Sciences [physics]
Common Operators
02 engineering and technology
Generic hardware architectures
FFT- SDF
[SPI]Engineering Sciences [physics]
Gate array
VHDL
[ SPI ] Engineering Sciences [physics]
0202 electrical engineering, electronic engineering, information engineering
Generic hardware architectures, Rake receiver, FFT- SDF, Common Operators, 3D-Network on chip, RTL modeling
Field-programmable gate array
computer.programming_language
Virtex
business.industry
020208 electrical & electronic engineering
020206 networking & telecommunications
Digital architecture
Rake receiver
Computer architecture
Embedded system
3D-Network on chip
business
Communications protocol
computer
Subjects
Details
- Language :
- English
- Database :
- OpenAIRE
- Journal :
- CoDIT, The 2014 International Conference on Control, Decision and Information Technologies (CoDIT’14), 2014 INTERNATIONAL CONFERENCE ON CONTROL, DECISION AND INFORMATION TECHNOLOGIES (CODIT), Kacem, I and Laroche, P and Roka, Z. 2014 INTERNATIONAL CONFERENCE ON CONTROL, DECISION AND INFORMATION TECHNOLOGIES (CODIT), Nov 2014, Metz, France. The 2014 International Conference on Control, Decision and Information Technologies (CoDIT’14), pp.595-600, 2014, 〈http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6996962〉, 2014 INTERNATIONAL CONFERENCE ON CONTROL, DECISION AND INFORMATION TECHNOLOGIES (CODIT), Université de Lorraine, METZ, Nov 2014, Metz, France. pp.595-600
- Accession number :
- edsair.doi.dedup.....dd9742d42ac21e9a94a003badc1fd9a5