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This paper reports on the capability of a nickel-tin (Ni-Sn) bond solder to be stable at high temperature application up to 600 $$^{\circ }$$ C. The Ni-Sn bond solder is fabricated using a transient liquid phase method of a 6 $$^{\prime \prime }$$ wafer-level bonding technique. The capability is determined by investigating the phase change of Ni-Sn compounds, which are grown within the bond solder, as well as the mechanical and electrical stability of the bond solder before and after annealing (in vacuum at 600 $$^{\circ }$$ C for 24 h). After annealing, the Ni-Sn phase has transformed to a new Ni-Sn phase with a higher re-melting temperature. A shear test has determined that the bond solder exhibits a relatively high bond strength before and after annealing. Using a daisy chain structure, the electrical resistance of the bond solder is determined and encounters a tolerable increase after annealing. Re-melting of the bond solder has not occurred during annealing. The daisy chain structure can be adapted for creating a bond solder which has a dense microstructure. [ABSTRACT FROM AUTHOR]

Successful direct wafer bonding between InP and silicon-on-insulator (SOI) wafers has been demonstrated by adopting a 20-nm-thick Al2O3 as the intermediate layer. A detailed investigation on the property of the bonding interface is carried out. Water contact angle test reveals an improved hydrophilicity for both the InP and the Al2O3/SOI wafers after oxygen plasma surface activation. X-ray photoelectron spectroscopy is employed to characterize the bonding interface before and after the wafer bonding process. It is found that oxides are formed on the bonding interface during bonding, which helps ensure high quality hydrophilic bonding. [ABSTRACT FROM AUTHOR]

To increase the yield of the wafer-level Cu-Cu thermo-compression bonding method, certain surface pre-treatment methods for Cu are studied which can be exposed to the atmosphere before bonding. To inhibit re-oxidation under atmospheric conditions, the reduced pure Cu surface is treated by H2/Ar plasma, NH3 plasma and thiol solution, respectively, and is covered by Cu hydride, Cu nitride and a self-assembled monolayer (SAM) accordingly. A pair of the treated wafers is then bonded by the thermo-compression bonding method, and evaluated by the tensile test. Results show that the bond strengths of the wafers treated by NH3 plasma and SAM are not sufficient due to the remaining surface protection layers such as Cu nitride and SAMs resulting from the pre-treatment. In contrast, the H2/Ar plasma-treated wafer showed the same strength as the one with formic acid vapor treatment, even when exposed to the atmosphere for 30 min. In the thermal desorption spectroscopy (TDS) measurement of the H2/Ar plasma-treated Cu sample, the total number of the detected H2 was 3.1 times more than the citric acid-treated one. Results of the TDS measurement indicate that the modified Cu surface is terminated by chemisorbed hydrogen atoms, which leads to high bonding strength. [ABSTRACT FROM AUTHOR]

This paper presents a fabrication method of capacitive micromachined ultrasonic transducers (CMUTs) by wafer direct bonding, which utilizes both the wet chemical and O2 plasma activation processes to decrease the bonding temperature to 400 °C. Two key surface properties, the contact angle and surface roughness, are studied in relation to the activation processes, respectively. By optimizing the surface activation parameters, a surface roughness of 0.274 nm and a contact angle of 0° are achieved. The infrared images and static deflection of devices are assessed to prove the good bonding effect. CMUTs having silicon membranes with a radius of 60 μmand a thickness of 2 μmare fabricated. Device properties have been characterized by electrical and acoustic measurements to verify their functionality and thus to validate this low-temperature process. A resonant frequency of 2.06 MHz is obtained by the frequency response measurements. The electrical insertion loss and acoustic signal have been evaluated. This study demonstrates that the CMUT devices can be fabricated by low-temperature wafer direct bonding, which makes it possible to integrate them directly on top of integrated circuit (IC) substrates. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart Cut™ technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer. [ABSTRACT FROM AUTHOR]

A fully integrated 3-D ultrasonic fingerprint sensor-on-a-chip is presented. The device consists of a 110\times 56 piezoelectric micromachined ultrasonic transducer (PMUT) array bonded at the wafer level to custom readout electronics fabricated in a 180-nm CMOS process with a HV (24 V) transistor option. With the 24 V driving signal strength, the sensor consumes 280 \mu \text{J} to image a 4.73 mm \times3.24$ mm section of a fingerprint at a rate of 380 fps. A wakeup mode that detects the presence of a finger at 4 fps and dissipates 10 \mu \text{W} allows the proposed sensor to double as a power switch. The sensor is capable of imaging both the surface epidermal and subsurface dermal fingerprints and is insensitive to contaminations, including perspiration or oil. The 3-D imaging capability combined with the sensor’s sensitivity to the acoustic properties of the tissue translates into excellent robustness against spoofing attacks. [ABSTRACT FROM PUBLISHER]

Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS) transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS) compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The twoMEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors. [ABSTRACT FROM AUTHOR]

GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge1-xSnx layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO2 on Ge1-xSnx, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge1-xSnx layer on GeSnOI substrate has a surface roughness of 1.90nm, which is higher than that of the original Ge1-xSnx epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge1-xSnx film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy. [ABSTRACT FROM AUTHOR]

Wafer bowing control is critical to improve epitaxial growth quality, especially for large wafers inside a metal-organic chemical vapor deposition reactor. An in-situ monitoring system was developed for real-time characterization of curvature mapping and epitaxial layer reflectance and temperature. Using deflectometry with parallel laser beams and position detector arrays, simultaneous curvature scans were conducted in two perpendicular directions over 4-in wafers. The developed system eliminated the effect of vibrations. Growth transients and curvature mappings are presented for the stages of epitaxial growth. Thermal and thickness gradient effects were analyzed to explain aspherical bowing. This technique appears suitable for closed-loop process optimization during light-emitting diode growth and other epitaxial growth processes. [ABSTRACT FROM AUTHOR]

This paper discusses the key technological aspects of via-middle Cu through-silicon vias (TSVs). The 3-D integration concept and the wafer front and backside process technology for realizing a 5- \mu \textm -diameter, 50- \mu \textm -deep Si TSV are described. Several options are shown for further, cost-effective, TSV scaling to 3- \mu \textm diameter, while maintaining a 50- \mu \textm Si thickness. Critical aspects for TSV reliability, such as barrier/liner integrity and Cu pumping, are discussed, and methods for a quantitative study are proposed. Finally, the impact of Cu via-middle TSVs on advanced electronic devices is discussed. A validated model for predicting the stress impact on devices and a method for defining possible keep-out zones are presented. [ABSTRACT FROM PUBLISHER]

We report the current status of the development of our new detectors for far-infrared (FIR) astronomy. We develop Blocked-Impurity-Band (BIB)-type Ge detectors to realize large-format compact arrays covering a wide FIR wavelength range up to 200 $$\upmu $$ m. We fabricated Ge junction devices of different physical parameters with a BIB-type structure, using the room temperature, surface-activated wafer bonding (SAB) method. We measured the absolute responsivity and the spectral response curve of each device at low temperatures, using an internal blackbody source in a cryostat and a Fourier transform spectrometer, respectively. The results show that the SAB Ge junction devices have significantly higher absolute responsivities and longer cut-off wavelengths of the spectral response than the conventional bulk Ge:Ga device. Based upon the results, we discuss the optimum parameters of SAB Ge junction devices for FIR detectors. We conclude that SAB Ge junction devices possess a promising applicability to next-generation FIR detectors covering wavelengths up to $$\sim $$ 200 $$\upmu $$ m with high responsivity. As a next step, we plan to fabricate a BIB-type Ge array device in combination with a low-power cryogenic readout integrated circuit. [ABSTRACT FROM AUTHOR]

In wafer polishing pad surface plays a crucial role in the polishing process. With the increase of friction time between pad and wafer, the pad becomes flattened or glazed with particles clogging the pores of the pad and forming a layer of slurry residue and wafer particles, leading to changes of COF, material removal rates and higher defects on the wafer surface. Thus, this study aims to determine the correlation between pad surface deformation, slurry adhesive rate and Coefficient of friction (COF) during friction between felt pad and single -crystal silicon, to analyze the relationship between pad condition and COF. The real-time COF between felt pad and single-crystal silicon wafer are tested which are sorted in groups depending on various loads and oscillation frequencies and surfaces of felt pads measuring by Scanning electron microscope (SEM) are compared. The correlation between pad surface deformation and abrasive adhesion and COF is evaluated through analyzing the experiment results. [ABSTRACT FROM AUTHOR]

The authors present a low-temperature wafer bonding process for the formation of electrically conductive n-GaSb/n-Ga0.79In0.21As and n-GaSb/n-Ga0.32In0.68P heterojunctions. The surfaces are deoxidized by sputter-etching with an argon-beam and bonded in ultrahigh vacuum. The sputtering behavior was investigated for each material, revealing a distinct selective sputtering characteristic for Ga0.32In0.68P. According to these findings, the settings for the bonding process were chosen. The mechanical and electrical properties of the wafer bonds were studied. Fully bonded 2 in. wafer pairs were found for both material combinations exhibiting high bond energies, which are comparable to the binding energies in the semiconductors. Furthermore, bond resistances below 5 mΩ cm2 could be reached, which are in the range of the lowest resistances that have been reported for wafer bonded heterojunctions. This speaks, together with the high bond energies, for a high amount of covalent bonds at the interfaces. These promising bond characteristics make the integration of antimonides with arsenides or phosphides by wafer bonding attractive for various optoelectronic applications such as multijunction solar cells. [ABSTRACT FROM AUTHOR]

SUMMARY Low-temperature bonding is an important fabrication technique for advanced microelectronics, microelectromechanical systems (MEMS), and optoelectronic devices. Recently, many low-temperature bonding techniques such as surface activated bonding have been studied in order to create unique device structures for a wide range of photonics applications. This paper focuses on low-temperature bonding techniques and reviews the state-of-the-art applications involving optoelectronic devices. [ABSTRACT FROM AUTHOR]

This paper reviews CMOS (complementary metal-oxide-semiconductor) MEMS (micro-electro-mechanical systems) fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator) CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered. [ABSTRACT FROM AUTHOR]

Two sapphire substrates were bonded using a fresnoite glass thin film as a sealant, by irradiation with a 1,064 nm ns laser. The sapphire close to the interface was examined by TEM, showing some structural defects due to the laser processing. Bond quality and strength were evaluated by scanning acoustic microscopy (SAM) and micro-chevron testing, respectively. Optimization of laser parameters lead to an improved processing speed (>1 mm/s) as well as an enhanced fracture toughness to 1.23 MPa m. [ABSTRACT FROM AUTHOR]

The low temperature joining of semiconductor substrates on wafer level by solid-liquid inter-diffusion bonding using the Cu/Ga and Au/In systems is investigated regarding the bonding parameters and their influence on bond interface properties. The focus is on temperature dependence and composition of interface. In the case of Cu/Ga bonding, a phase transition from CuGa2 to Cu9Ga4 was found to be primarily responsible for an increase in bonding strength. After the temperature treatment of 90°C, a shear strength of up to 90 MPa could be achieved. Furthermore, the combination of Au and In with composition ratios suitable for AuIn2 and AuIn intermetallic phase formation was investigated. In the case of AuIn shear strength, 96 MPa was achieved using a bonding temperature of 200°C. [2014-0325] [ABSTRACT FROM AUTHOR]

This paper reports on the extraction of residual stress in surface-micromachined nickel thin films of electrostatically actuated fixed-fixed beams using a wafer-scale technique. The distribution of residual stress for 87 beams on a 4-in quarter wafer piece is presented. The residual stress ( \sigma 0 ) is determined from the best fit of the displacement-voltage curves predicted by a computationally efficient model to the experimental data. The nondestructive and automated measurements are taken at room temperature and directly at the beam itself without any additional test structures. The model employed incorporates the nonideal effects of inclined supports, nonflat initial beam profiles, and fringing fields. The extracted residual stress values vary between −12.8 and 13.6 MPa (negative values are for compressive stresses and positive ones for tensile stresses). The residual stresses for these 87 beams follow a nearly normal distribution with a mean value of −1.7 MPa and a standard deviation of 5.9 MPa, which represents the variability of the residual stresses across the wafer. Detailed uncertainty analysis has been conducted, and it reveals that inaccurate modeling of the nonideal effects will result in significant errors in the extracted residual stress. Although demonstrated on nickel thin films, this technique can be applied to other metallic thin films. [2014-0344] [ABSTRACT FROM AUTHOR]

We have developed for the first time a 3-D integrated CMOS image sensor with pixel-parallel analog-to-digital converters (ADCs). Photodiode (PD) and inverter layers are prepared on separate silicon-on-insulator layers and directly bonded with damascened Au electrodes. The handle layer is then removed by grinding and XeF2 vapor phase etching to expose the PD surface. The developed process is suitable for pixelwise interconnection because it allows the damascened Au electrodes to be 1 \mu \textm in diameter or less. An ADC circuit is designed based on pulse frequency modulation where pulses are generated proportional to the illumination intensity, and contains a PD, inverters, a reset transistor, and counters. A prototype 3-D integrated CMOS image sensor is also developed with 64 pixels, which acquires video images without pixel defects. A wide dynamic range of >80 dB is confirmed for the incident light intensity. The experimental results demonstrate the feasibility of pixel-level 3-D integration for high-performance CMOS image sensors. [ABSTRACT FROM AUTHOR]

Wafer-level Cu-Sn SLID (Solid-Liquid Interdiffusion)-bonded devices have been evaluated at high temperature. The bonding process was performed at 553 K (280 °C) and the mechanical integrity of the bonded samples was investigated at elevated temperatures. The die shear strength of Cu-Sn systems shows a constant behavior (42 MPa) for shear tests performed from room temperature [RT-298 K (25 °C)] to 573 K ( to 300 °C). This confirms experimentally the high-temperature stability of Cu-Sn SLID bonding predicted from phase diagrams. The fractography of sheared samples indicates brittle-fracture mode for all samples shear tested from RT to 573 K (300 °C). The two dominating failure modes are Adhesive fracture between the Ti-W adhesion layer and the Si, and interface fracture at the original bond interface. This indicates that the bonding material itself is stronger than the observed shear strength values, and since these interfaces can be improved with process optimization even stronger bonds can be achieved. The presented work offers fundamental evidence of the Cu-Sn SLID bonding process for operating microelectronics and MEMS at high temperature. [ABSTRACT FROM AUTHOR]

Fabrication and characterization results of sealed cavities formed by adhesive wafer bonding with dry etched Cyclotene 3000™ are presented. The cavities were formed by patterning partially cured Cyclotene 3000™ on an SOI wafer. The cavities were sealed by bonding the patterned layer at low temperature (210 °C) to another partially cured thin Cyclotene 3000™ layer on a bare silicon wafer. The parameters for the vacuum bonding process were determined through an iterative process that involved optical and SEM inspection of the Cyclotene™ layers at the bonding surfaces to ensure a void and wrinkle free strong bond. The fabricated cavities were 28 µm wide and 800 nm high with a 10 µm wide supporting wall. Cavities of other dimensions can also be realized following the same procedure. The cavities can be used to realize MEMS microphones, MEMS pressure sensors, capacitive micromachined ultrasonic transducers (CMUT), resonant cavities, and also for protective encapsulation of MEMS and microelectronic dies. [ABSTRACT FROM AUTHOR]

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 \mu \textm top entrant critical dimension and 50 \mu \textm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 \mu \textm TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating. [ABSTRACT FROM AUTHOR]

This paper details an application where E-beam inspection (EBI) can be used for 100% full wafer inspection, generally considered a mythical target for EBI. For process layers where the line-widths and defects of interest are large, very large pixel size and high scan frequency can be used, thereby making full wafer inspection feasible. The metal layers in the back-end-of-line fit this bill when scanned in voltage contrast (VC) mode. Shorts or opens at any previous layer connected to the surface nodes can cause a VC signal, therefore the electrical health of each wafer is assessed for multiple layers simultaneously across the full wafer. The advantage of this scan is that failure sites can be identified and somewhat localized well before wafer final test. This application is more appropriate for semi-mature technologies where there are few defects per wafer, and therefore a full wafer scan is needed to catch a reasonable number of defects. The challenge with this type inspection is in identification of the root cause. A number of studies to map VC defect strength to types of physical defects are described. These studies demonstrated that this technique successfully finds yield limiting defects, but not all yield limiting defects will be detected. A plan for how to use the VC inspection to find root cause is presented. [ABSTRACT FROM AUTHOR]

A wafer temperature feedback control system during plasma processing with rapid, precise, and real-time temperature monitoring employing frequency-domain low-coherence interferometry was developed. To keep the temperature within a specific range, plasma was actively switched on and off, controlled by signals from a monitoring system. It was applied to an organic film etching process with an H2 and N2 mixture gas plasma. The organic material etching yield from atomic hydrogen has a relatively high sensitivity to temperature, and a constant temperature is required to achieve precise etching profiles. This system maintained the wafer temperature within a few degrees for H2/N2 plasma discharges. Duty ratios per discharge gradually decreased because the temperature of the chamber component parts around the wafer increased. The trench width etched in the organic film increased with increasing wafer temperature. This is because of a temperature dependence balance between the etching reaction and protection film formation on the trench sidewall. [ABSTRACT FROM AUTHOR]

We study covalent bonds between p-doped Si wafers (resistivity ∼10 Ω cm) fabricated on a recently developed 200 mm high-vacuum system. Oxide- and void free interfaces were obtained by argon (Ar) or neon (Ne) sputtering prior to wafer bonding at room temperature. The influence of the sputter induced amorphous Si layer at the bonding interface on the electrical behavior is accessed with temperature-dependent current-voltage measurements. In as-bonded structures, charge transport is impeded by a potential barrier of 0.7 V at the interface with thermionic emission being the dominant charge transport mechanism. Current-voltage characteristics are found to be asymmetric which can tentatively be attributed to electric dipole formation at the interface as a result of the time delay between the surface preparation of the two bonding partners. Electron beam induced current measurements confirm the corresponding asymmetric double Schottky barrier like band-alignment. Moreover, we demonstrate that defect annihilation at a low temperature of 400 °C increases the electrical conductivity by up to three orders of magnitude despite the lack of recrystallization of the amorphous layer. This effect is found to be more pronounced for Ne sputtered surfaces which is attributed to the lighter atomic mass compared to Ar, inducing weaker lattice distortions during the sputtering. [ABSTRACT FROM AUTHOR]

We propose a new pattern-transfer method comprising laser liftoff and wafer bonding process; the former was used to separate GaN-based epitaxial layers from patterned sapphire substrates (PSSs) with self-assembled surface nanodots, and the latter was used to combine the epitaxial layers with the Si substrate. The nanodots on the PSS surface were formed by dry etching with self-assembled Ag nanoislands as an etching mask. The fabricated vertical GaN-based light-emitting diodes (VLEDs) presented an in situ nanotextured surface. At a driving current of 350 mA, the VLEDs increased the output power by $\sim 17$ % compared with the conventional VLEDs without a nanotextured surface. The main enhancement can be attributed to the increase in light-extraction efficiency of photons emitted inside the LEDs. [ABSTRACT FROM AUTHOR]

Die attachment quality plays a remarkable role in producing highly reliable solid-state lighting fixtures by providing a dominant impact on thermal resistance. Color rendering, efficacy, and lifetime are strongly related to junction temperature. This paper investigated the effects of varying the thickness of sputter-coated copper on an Al2O3 ceramic substrate on the thermal resistance and luminous intensity of flip-chip light-emitting diode (LED) devices. Eutectic bonding was applied to provide excellent bonding strength and low void content between the chip and ceramic substrate. The thermal resistance dramatically decreased as the copper thickness was reduced because of a substantial reduction in the conduction impedance for heat dissipation from the junction to the ambient. The luminous intensity was improved by reducing the copper thickness as the driving current was increased from 50 to 700 mA. The results demonstrated that reducing the copper thickness effectively reduced the junction temperature and improved the performance of the eutectic flip-chip bonding LED devices. [ABSTRACT FROM AUTHOR]

Due to the flowability of benzocyclobutene (BCB) and the unavoidable shear components of the bonding force applied by bonding facilities, it is quite challenging to achieve void-free BCB adhesive bonding with simultaneous high post-bonding alignment accuracy. To solve this problem, this paper reports a compensation method for alignment errors to achieve simultaneous void-free and accurate wafer bonding using soft-baked BCB. By characterizing the wafer shift induced bonding force, it is found that the wafer shift is a systematic error associate with the bonders but independent of the wafers. Upon this investigation, a compensation method presetting a pre-bonding alignment shift opposite to the post-bonding shift is proposed to compensate the bonding induced wafer shift. Using this method, void-free bonding with soft-baked BCB has been achieved, and the alignment errors are improved significantly from around 35-40 μm to around 3 μm. Test results show that the average bonding strength of soft-baked BCB is about 26.4 % higher than that of partially-cured BCB. The preliminary results demonstrate the efficacy of the proposed compensation method, which has potential to improve the alignment accuracy of BCB bonding for three-dimensional integration, MEMS, and microsensors. [ABSTRACT FROM AUTHOR]

This paper presents design, analysis, fabrication, and measurement of airflow sensors with three hot-wire resistors on an out-of-plane glass bubble. The fabrication process is based on etching cavities in silicon wafer, followed by anodic bonding of a thin Pyrex glass wafer to the etched silicon wafer. The bonded wafers are then heated inside a furnace at a temperature above the softening point of the glass, and because of the expansion of the trapped gas in the silicon cavities, the glass is blown into three-dimensional (3-D) spherical glass bubbles. Resistors patterned on the glass wafer above the cavities are elevated above the base during the glass bubble blowing process. An optimization analysis on the structure and geometry of the sensor, fabrication process, and properties of multilayer thin-film resistors on glass has been conducted in an attempt to improve the sensitivity. [2014-0177] [ABSTRACT FROM PUBLISHER]

In this paper, we introduce a new bonding technology for the assembly of micro- structured glass substrates for miniaturized chemical analysis. The protocol features a facile polymer chemistry method processing at lower temperatures (<100 °C). The method consisted of a proper cleaning of the two glass surfaces, followed by hydroxylization, aminosilylation and hyperbranched polyurethane oligomers (HPU) bridging on quartz wafer surfaces as the interlayer. Strong bonding with a shear force 4.5 MPa has been achieved. The present procedure avoids the possible micro-channel blockage and contamination by using conventional adhesives. Moreover, the microfluidic chips bonded by the above procedures are highly transparent therefore allowing for biochemical compositions to be easily characterized by UV-vis or IR spectroscopy. [ABSTRACT FROM AUTHOR]

The high-temperature requirement of Al-Ge eutectic bonding stands as a major obstacle to its wider acceptance for hermetic sealing application in the microelectromechanical systems packaging industry, in particular for temperature-sensitive devices. It has been demonstrated that a reduction in bonding temperature is feasible without compromising the hermeticity. The change in the mode of bonding from eutectic to solid-state diffusion did not have a dramatic impact on the bonding quality. However, this resulted in a substantial increase in bonding time. The shear strength also deteriorated as a result of the decrease in thickness of the reaction interface. However, the shear strength still complied with military standards. It has been confirmed that a hermetic seal could still be achieved without any solidification occurring at the interface. This is feasible since the interdiffusion coefficients of Al in (Ge) phase and Ge in (Al) phase are closer and are comparable to diffusion between solid-solution phases of identical metals such as in Au-Au, Cu-Cu, and Si-Si bonding, which are generally used for such hermetic sealing application. An appropriate stacking mechanism for Al-Ge diffusion bonding is identified to overcome the limitations with respect to surface topography. [ABSTRACT FROM AUTHOR]

We present a method for low temperature plasma-activated direct wafer bonding of III-V materials to Si using a transparent, conductive indium zinc oxide interlayer. The transparent, conductive oxide (TCO) layer provides excellent optical transmission as well as electrical conduction, suggesting suitability for Si/III-V hybrid devices including Si-based tandem solar cells. For bonding temperatures ranging from 100 °C to 350 °C, Ohmic behavior is observed in the sample stacks, with specific contact resistivity below 1 Ω cm² for samples bonded at 200 °C. Optical absorption measurements show minimal parasitic light absorption, which is limited by the III-V interlayers necessary for Ohmic contact formation to TCOs. These results are promising for Ga0.5In0.5P/Si tandem solar cells operating at 1 sun or low concentration conditions. [ABSTRACT FROM AUTHOR]

This paper presents an ultrasonic fingerprint sensor based on a 24×8 array of 22MHz piezoelectric micromachined ultrasonic transducers (PMUTs) with 100 lm pitch, fully integrated with 180 nm complementary metal oxide semiconductor (CMOS) circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. The array frequency response and vibration mode-shape were characterized using laser Doppler vibrometry and verified via finite element method simulation. The array's acoustic output was measured using a hydrophone to be ~14 kPa with a 28V input, in reasonable agreement with predication from analytical calculation. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20×8 sub-array, resulting in 300mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D polydimethylsiloxane fingerprint phantom (10mm × 8mm) at a 1.2mm distance from the array. [ABSTRACT FROM AUTHOR]

SUMMARY Usually, wafer inspection is a two-step process. The first step, which is very important, consists of detection of defects on the wafer. The second step classification of the detected defects, which is done after defect detection as necessary. Recently, it has become necessary to perform simultaneous detection and classification of wafer defects in order to reduce the wafer inspection time while maintaining high resolution of inspection. Optical wafer inspection is the most effective method for detecting and classifying defects and estimating their size in a short time. In this method, the scattered light distribution is compared with a database of previous scattered light distributions and pattern matching is used to classify defects and estimate their size. Therefore, to achieve optical wafer inspection based on scattered light distribution, it is necessary to gather scattered light distribution data for many samples of various kinds. The first aim of this study is to develop a defect classification and size estimation method utilizing the scattered light distribution. We propose a method of classifying defects on wafers and estimating their size. The proposed method is based on pattern matching utilizing a parametric eigenspace. The second aim of the paper is to validate the proposed method by applying it to scattered light distribution samples. The light scattering distribution samples were generated by discrete dipole approximation (DDA) simulation. A database of the light scattering distribution is easily created using the simulation. [ABSTRACT FROM AUTHOR]

A novel concept termed confined lateral guided growth (CLGG) has been demonstrated to prepare single crystalline GaN microtiles with a goal to create high crystalline quality and strain-free GaN on large-sized Si (111) substrates. Uniform array of hexagonal GaN tiles has been created with a diameter of larger than 30 μm for each tile. As revealed by the surface pits density of around 2 × 108 cm−2, the density of dislocations in these GaN tiles has been significantly reduced compared with that obtained typically from a GaN heteroepitaxy on Si (111). The strain in GaN tiles has been dramatically reduced to nearly zero. This approach offers a route to eliminate wafer-bowing for growing high crystalline quality GaN on Si, especially when the substrate size scales to 12 in and beyond. The growth behavior and mechanism within these confined growth masks are investigated by both finite element modeling and experimental studying, indicating that CLGG is dominated by gas phase diffusion. [ABSTRACT FROM AUTHOR]

This paper presents the design, fabrication and characterization of a millimetre-wave wide-band patch antenna integrated on silicon (Si) and using a BCB membrane suspended over a deep cavity etched in the Si substrate. The antenna structure consists of a top patch on a Si cap, a bottom patch on a BCB membrane and a ground plane in the cavity. The antenna takes advantage of the coupling between the stacked patches and the large air cavities to achieve a wide impedance bandwidth around 60 GHz. The bottom patch is implemented using electroplating on the suspended BCB membrane which is transferred through our wafer-level transfer technique over the cavity. The size of the realized antenna is 3.5 × 2.8 × 0.6 mm. The fabricated antenna showed a reflection coefficient lower than −7 dB from 49.5 GHz to more than 67 GHz (30 % fractional bandwidth) and an experimental gain in the order of 7 dBi at 60 GHz in good agreement with the simulation (7.5 dBi). [ABSTRACT FROM AUTHOR]

As the basic process, elevated temperature annealing is widely used in silicon MEMS device fabrication. This paper studies plastic and creep characteristics of single crystal silicon (SCS) microstructure which would take place during high temperature fabrication processes. The widely used microstructure in MEMS design, which consists of a square diaphragm with a center boss and a vacuum cavity, is adopted in this work. During high temperature process, because of atmospheric pressure outside the vacuum cavity, maximum Von Mises stress of SCS microstructure will exceed the yield stress of SCS, and plastic deformation of the SCS microstructure will occur. An empirical formula for plastic deformation is derived from measurement results in order to predict the plastic deformation in the SCS microstructure design. The plastic deformation is in inverse ratio to the cube of the diaphragm thickness and is not continuous at the yield point. The creep of the microstructure is also investigated by measuring the deformation as a function of annealing time. The obvious creep was observed at 1,100 °C. Due to the non-uniform stress distribution, the creep curve of SCS microstructure is found to be different from that of SCS by tension tests. For SCS microstructure, the creep rate decreases with annealing time in the primary creep and becomes nearly zero in the secondary creep. [ABSTRACT FROM AUTHOR]

Component miniaturization is increasingly gaining importance in numerous microsystem technologies, including medical technology, biotechnology, and drive technology. In this study, two types of nano-sized powder, namely, metal (stainless steel 316L) and ceramic (yttria-stabilized zirconia), were used to fabricate miniature parts through micro powder injection molding. Micro parts were produced by mixing powders with a binder system, followed by injection, debinding, and sintering process. Partially water-soluble binder system with surfactant addition was used to mix with either stainless steel 316L or yttria-stabilized zirconia nanopowder to form feedstock to avoid the agglomeration of fine powder and environmentally hazardous organic binder. The polyethylene glycol loss in water was observed after a rapid removal period in the first 60 min of immersion for the micro parts. Approximately 99 % of the polymethyl methacrylate binder was removed after pyrolysis at 450 °C for 2.5 h. Sintered ceramic and metallic parts showed a relative density that is approximately 97 % of theoretical density and free of defects. Hardness of approximately 221 and 1,200 Hv was achieved for the fabricated micro parts using stainless steel 316L and yttria-stabilized zirconia powders, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a fabrication process for micro synthetic jet actuators (SJA) by bonding a high-quality Pb (Zr,Ti) O (PZT) ceramic wafer to a silicon wafer using epoxy resin at low temperature (<150 °C). The bulk-PZT was lapped and polished to be PZT thick film by chemical mechanical polishing (CMP) method, and patterned by wet-etching method. The cavity and orifice of SJA were formed by inductive coupled plasma etching (ICP) method. A MEMS piezoelectric SJA was then completed and characterized, including the performance of the PZT thick film. While the dimension of bonded PZT thick film is about 6,000 × 6,000 × 100 μm, and the dimension of Si membrane is about 1,000 × 1,000 × 20 μm. The experimental results show that the maximum center amplitude of PZT-Si diaphragm is 15.05 μm at Vp-p of 90 V and the resonant frequency of 5 kHz, and the maximum jet velocity is higher than 11 m/s. This novel process has great potential to fabricate MEMS piezoelectric synthetic jet actuators. [ABSTRACT FROM AUTHOR]

In this study we proposed a device composed of dry electrode and dry adhesive medical patch for biopotentials measurement. The behavior of the dry adhesive with mushroom-shaped micropillars is characterized through normal and friction force test. The adhesion strength (~1.2 N/cm) is comparable to acrylic medical patch, and the repeating cycle testing result demonstrates that the adhesion strength of dry adhesive medical patch is larger than that of acrylic medical patch. Moreover, the dry adhesive medical patch does not cause skin to turn allergic owning to its biocompatibility. The proposed device also is used to record electrocardiogram (ECG) with dry electrode. Compared with conventional wet electrode, the signal quality is outstanding. The QRS-complex and T-wave of ECG are clearly legible. [ABSTRACT FROM AUTHOR]

A new technique was developed for embossing microstructures on thermoplastic substrates, which can achieve high accuracy replication with little loss of the production efficiency. The technique is no need of the preheating process and cooling device. In the new technique, just the surface layer of the polymer substrate was heated through heat transmission and ultrasonic viscoelastic heating was the major heat source. For our new technology, the temperature of the mould just provided the initial temperature of the mould-substrate interface and a higher boundary temperature for embossing. The replication accuracies of three embossing technologies were contrasted, including ultrasonic embossing at room temperature (HER), thermal assisted ultrasonic embossing (TUE) and local thermal assisted ultrasonic embossing (L-TUE). The results indicated that, the replication accuracy of L-TUE was approximate with TUE. Moreover, the effects of the processing parameters on the replication quality, including average replication depth and uniformity over the entire chip, were investigated. Different with our prediction, the replication accuracy did not monotonously improved with the ultrasonic force and the temperature of the mold. Finally, the temperature test was carried out to study the temperature characteristic of our new technology. [ABSTRACT FROM AUTHOR]

Two sapphire substrates are tightly bonded through a fresnoite-glass thin film, by irradiation with a 1,064 nm nanosecond laser. The composition of the glass solder at the bond interface changes, due to incorporation of Al from the upper substrate. The oxidic solder remains amorphous after laser irradiation, but after annealing (850 °C for 1 h) crystalline structures are observed in different morphologies, which are attributed not only to fresnoite, but also to Ba-Ti-Al-O phases, which lead to a strong luminescence of the laser irradiated region under UV excitation. [ABSTRACT FROM AUTHOR]

This paper deals with the improvement of the TTV values (Total Thickness Variation) of 300 mm silicon wafers thinned down at 100 μm using the ZoneBond (ZoneBond is registred by Brewer Science Inc.) technology. We have demonstrated that the thin film TTV of the film was mainly driven by the bonding process and was very tolerant towards the coating step. It was also shown that, within the experiment precision, the TTV value was not changed by the grinding thinning process. 8 µm was the best TTV value obtained after the optimization of the bonding parameters. [ABSTRACT FROM AUTHOR]