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Spiking Neural Networks (SNNs) is promising to enable low power and high performance edge computing hardware design and have recently attracted attentions of researchers. Compared to Artificial Neural Networks (ANNs), SNNs, which present more realistic brain-inspired computing models, are developed as an alternative to ANNs. However, the temporal primitive of SNNs causes irregular and repeated data accesses, leading to high latency and extra power consumption. In this work, we propose an efficient architecture for SNNs by exploiting event-based characteristics. A reconfigurable spiking neuron processing unit is proposed to support a variety of spike-layers. Furthermore, to reduce the cycles needed per frame, an efficient dataflow with fast-filtering mechanism is introduced to leverage the sparsity of discrete spikes. The results show that this design achieves 67.5 μJ/image prediction energy with a throughput of 2.2K FPS. The core size is 0.89 mm under 28-nm technology, with 90.98% computing hardware utilization and a competitive accuracy 97.10% on a driving dataset.

This document describes the dataflow of the CubeSat mission SpaceTeamSat1 (STS1) of the TU Wien Space Team (TUST). We developed the dataflow architecture during a game which relates to the Concurrent Design Facility (CDF) utilized by the European Space Agency (ESA). In our so called Dataflow Game every member played the role of a subsystem of the CubeSat. Then we played through different scenarios like sending a beacon from the CubeSat, or uploading a file from the ground to the CubeSat considering both normal operation and error cases. This allowed us to test our high-level design and deduce the functionality of the subsystems in a top-down manner.

Despite the constant efforts of coming up with new ideas and approaches, operating systems’ development has continued to be based on the same fundamental technologies of the 1970s, when the UNIX operating system and the C programming language were first developed. However, there are certain segments of the market, where companies and software engineers are fed up with C and its derivatives, and they are seeking something that promises more automation in the development of low-level systems. A classic layout of complex software, such as operating systems, usually involves a set of fine-tuned performance-optimized routines that are combined and controlled from an upper layer in a lightweight fashion. As the complexity grows, reliable operation, portability, and maintainability become a major concern. However, this can be tamed by abstracting away from the platform-dependent details by modelling the components and their relation on a higher level. Using a functional programming language combined with the technique of language embedding may be an answer to the question of how to implement such a solution. In this design, the component descriptions may be captured adequately by an embedded domain-specific language that compiles to a lower-level language but there also has to be mechanism for composition and thereby obtaining a complete working system out of them. The Flow language is introduced through a motivating example which is also featured in the thesis. It also describes the major elements in the resulting computation model, e.g. tasks, channels, and the execution of tasks. Though its focus is on the applicability of the approach in relation of arbitrary Haskell-embedded domain-specific language as that is one of the main concerns in the adaption among third-party developers. Thus, Feldspar (Functional Embedded Language for Digital Signal Processing and Parallelism) is used as prime example for a domain-specific language to be applied in conjunction with the Flow. During the work on the design and implementation of a coordination language framework for embedded domain-specific languages we briefly touch on the issue of executing specialized task graphs. In our model, we create a set of workers (executors) dynamically picked and executed DSL programs (tasks) as part of a dataflow graph. The number of workers matched the number of processing units of the given hardware in the ideal case. This last aspect may contribute to lowering the expectations from the supporting run-time environment, eventually making the compiled graphs standalone on top of the bare metal. However, during the preliminary performance tests, we observed that our first na¨ive stab at scheduling execution of graphs did not scale well for multiple workers – which is not surprising as relations between tasks induced by data dependencies in the dataflow graph are not respected. To provide guarantees for that, tasks are partitioned into pools, although the optimal organization of pools is hard to achieve automatically. Hence we decided to create another embedded domain-specific functional language to provide a way for the programmer to express heuristics on how dataflow graphs are scheduled, which lead us to the concept of “declarative scheduling”. Declarative scheduling allows the implementation of domain-specific scheduling constraints that helps to abstract away from the low-level scheduling details and rather focuses on the protocol implementation itself. Also, an extension is proposed to the above model, where a tuning for performance based on certain properties is enabled which shows how a practitioner may profit from describing the application on a higher level and leaving the details to an appropriate compiler.

Dynamically scheduled high-level synthesis can exploit high levels of parallelism in poorly-predictable control-dominated applications. Yet, dataflow circuits are often generated by literal conversion of basic blocks into circuits interconnected in such a way as to mimic the program's sequential execution. Although correct and quite effective in many cases, this adherence to control flow still significantly limits exploitable parallelism. Recent research introduced techniques to deliver data tokens directly from producers to consumers and achieved tangible benefits both in circuit complexity and execution time. Unfortunately, while this successfully addressed ordinary data dependencies, the problem of potential dependencies through memory remains open: When no technique can statically disambiguate accesses, circuits must be built with load-store queues (LSQs) which, to reorder accesses safely, need memory accesses to be allocated in the queues in program order. Such in-order allocation still demands control circuitry emulating sequential execution, with its negative impact on parallelization. In this paper, we transform potential memory dependencies into virtual data dependencies and use the new direct token delivery strategy to allocate accesses sequentially into the LSQ. In other words, we exploit more parallelism by constructing control circuitry to emulate exclusively those parts of the control flow strictly necessary for in-order allocation. Our results show that we can achieve up to a 74% reduction in execution time compared to prior work, in some cases, at no area cost., Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, ISBN:978-1-4503-9417-8

Linear Genetic Programming (LGP) represents programs as sequences of instructions and has a Directed Acyclic Graph (DAG) dataflow. The results of instructions are stored in registers that can be used as arguments by other instructions. Instructions that are disconnected from the main part of the program are called noneffective instructions, or structural introns. They also appear in other DAG-based GP approaches like Cartesian Genetic Programming (CGP). This article studies four hypotheses on the role of structural introns: noneffective instructions (1) serve as evolutionary memory, where evolved information is stored and later used in search, (2) preserve population diversity, (3) allow neutral search, where structural introns increase the number of neutral mutations and improve performance, and (4) serve as genetic material to enable program growth. We study different variants of LGP controlling the influence of introns for symbolic regression, classification, and digital circuits problems. We find that there is (1) evolved information in the noneffective instructions that can be reactivated and that (2) structural introns can promote programs with higher effective diversity. However, both effects have no influence on LGP search performance. On the other hand, allowing mutations to not only be applied to effective but also to noneffective instructions (3) increases the rate of neutral mutations and (4) contributes to program growth by making use of the genetic material available as structural introns. This comes along with a significant increase of LGP performance, which makes structural introns important for LGP.

Model-driven methodology has been widely adopted in embedded software design, and Dataflow is a widely used computation model, with strong modeling and simulation ability supported in tools such as Ptolemy. However, its code synthesis support is quite limited, which restricts its applications in real industrial practice. In this paper, we focus on the automatic code synthesis of Dataflow, and implement , a code generator that could support most of the widely used modeling features such as expression type and boolean switch, more efficiently. First, we disassemble the Dataflow model into actors embedded in if-else or switch-case statements based on schedule analysis, which bridges the semantic gap between the code and the original Dataflow model. Then, we design well-designed templates for each actor, and synthesize well-structured executable C and Java codes with sequential code assembly. Compared to the existing C and Java code generators of Dataflow model in Ptolemy-II, and the C code generator in Simulink, the lines of code synthesized by are decreased by an average of , and , and the execution time of the synthesized code by is also decreased by an average of , and respectively.

Deep Neural Networks (DNNs) have shown superiority in solving the problems of classification and recognition in recent years. However, DNN hardware implementation is challenging due to the high computational complexity and diverse dataflow in different DNN models. To mitigate this design challenge, a large body of research has focused on accelerating specific DNN models or layers and proposed dedicated designs. However, dedicated designs for specific DNN models or layers limit the design flexibility. In this work, we take advantage of the similarity among different DNN models and propose a novel Lego-based Deep Neural Network on a Chip (DNNoC) design methodology. We work on common neural computing units (e.g., multiply-accumulation and pooling) and create some neuron computing units called NeuLego processing elements (NeuLegoPEs). These NeuLegoPEs are then interconnected using a flexible Network-on-Chip (NoC), allowing to construct different DNN models. To support large-scale DNN models, we enhance the reusability of each NeuLegoPE by proposing a Lego placement method. The proposed design methodology allows leveraging different DNN model implementations, helping to reduce implementation cost and time-to-market. Compared with the conventional approaches, the proposed approach can improve the average throughput by 2,802% for given DNN models. Besides, the corresponding hardware is implemented to validate the proposed design methodology, showing on average 12,523% hardware efficiency improvement by considering the throughput and area overhead simultaneously.

Coarse-grained reconfigurable architectures (CGRAs) are increasingly employed as domain-specific accelerators due to their efficiency and flexibility. A CGRA typically relies on compilers to perform task scheduling. The longstanding problem of static scheduling is that it suffers from insufficient parallelism in handling irregularities due to over-serialization and workload imbalance, which leads to severe resource underutilization and performance loss. To counteract the limitations of static scheduling in CGRAs, it is essential to exploit dynamic parallelism automatically and manage hardware resources adaptively. However, existing dynamic scheduling mechanisms, e.g., work stealing, often reschedule aggressively for instant performance but sacrifice efficiency, which is unfavorable to CGRAs that emphasize efficiency and fewer reconfigurations. This article proposes an elastic task scheduling scheme that enables lightweight dynamic scheduling in CGRAs. Tasks are rescheduled at runtime according to the classic tagged-token dataflow paradigm to enable dynamic task-level parallelism. Meanwhile, tasks are dynamically resized according to run-time throughputs via duplication, combination, and substitution operators for balanced multitask execution. We implement the elastic task scheduling scheme on a well-known reconfigurable architecture - triggered instruction architecture (TIA). Evaluation on the MachSuite benchmarks shows that the proposed scheme is effective in improving performance and energy efficiency. The average speedup is $2.2\times$ 2 . 2 × over the baseline. Also, our design attains a 57 percent improvement in the area-normalized performance and a 49 percent better energy efficiency. Compared with a state-of-the-art dynamic scheduling method, our scheme achieves $1.6\times$ 1 . 6 × speedup and $1.6\times$ 1 . 6 × energy efficiency than work-stealing mechanism on the same substrate.

When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable information is often lost during physical synthesis. This paper proposes HiDaP, a novel multi-level algorithm that uses RTL information and analytical methods for the macro placement problem of modern designs dominated by multi-cycle connection pipelines. By taking advantage of the hierarchy tree, the netlist is divided into blocks containing macros and standard cells, and their dataflow affinity is inferred considering the register latency and flow width of their interaction. The layout is represented using slicing structures and generated with a top-down algorithm capable of handling blocks with both hard and soft components. An adaptive multi-objective cost function is used to simultaneously minimize wirelength, timing, overlap and distance to preferred locations, which can be user-defined or generated by analytic methods (spectral and force-directed). These techniques have been applied to a set of large industrial circuits and compared against state-of-theart commercial and academic placers, and also to handcrafted floorplans generated by expert back-end engineers. The proposed approach outperforms previous algorithmic methods and can produce solutions with better wirelength and timing than the best handcrafted floorplans. Post-routing layouts are almost brought to timing closure and DRC cleanness with minimal engineer modification, showing that the generated floorplans provide an excellent starting point for the physical design flow and contribute to reduce turn-around time significantly. This work has been partially supported by a grant from Inphi Corporation and funds from the Spanish Ministry for Economy and Competitiveness and the European Union (FEDER funds) under grant TIN2017-86727-C2-1-R, and the Generalitat de Catalunya (2017 SGR 786).

The pervasiveness of the smart Internet of Things (IoTs) enables many electric sensors and devices to be connected and generates a large amount of dataflow. Compared with traditional big data, the streaming dataflow is faced with representative challenges, such as high speed, strong variability, rough continuity, and demanding timeliness, which pose severe tests of its efficient management. In this paper, we provide an overall review of IoT dataflow management. We first analyze the key challenges faced with IoT dataflow and initially overview the related techniques in dataflow management, spanning dataflow sensing, mining, control, security, privacy protection, etc. Then, we illustrate and compare representative tools or platforms for IoT dataflow management. In addition, promising application scenarios, such as smart cities, smart transportation, and smart manufacturing, are elaborated, which will provide significant guidance for further research. The management of IoT dataflow is also an important area, which merits in-depth discussions and further study.

Although dataflow models are known to thrive at exploiting task-level parallelism of an application, it is difficult to exploit the parallelism of data, represented well with loop structures, since these structures are not explicitly specified in existing dataflow models. SDF/L model overcomes this shortcoming by specifying the loop structures explicitly in a hierarchical fashion. We introduce a scheduling technique of an application represented by the SDF/L model onto heterogeneous processors. In the proposed method, we explore the mapping of tasks using an evolutionary meta-heuristic and schedule hierarchically in a bottom-up fashion, creating parallel loop schedules at lower levels first and then re-using them when constructing the schedule at a higher level. The efficiency of the proposed scheduling methodology is verified with benchmark examples and randomly generated SDF/L graphs.

Convolutional neural network (CNN) have been widely used in speech recognition, object detection and image recognition. In the process of inference, data access operations consume more energy than calculations. Therefore, optimizing the dataflow from external storage to the on-chip processing unit is an effective method to reduce the power consumption. The state-of-the-art row stationary dataflow maximizes the data reusing to reduce the number of data movement and thus reducing the power consumption of the system. However, it has the problems of low processing unit utilization and poor scalability. In this letter, we propose an enhance row stationary (ERS) dataflow. ERS dataflow maps the data of each channel of the three-dimensional filter and input feature map (ifmap) into a column of processing units by changing the mapping of data. The processing array operates multiple filters in parallel, which effectively improves the utilization of computing resources. Within each processing unit, one row of filter data and one row of ifmap data are processed at a time, and the filter row data and ifmap row data are reused in multiple convolution operations. In addition, a configurable sliding window model is proposed to solve the problem that the existing dataflow cannot handle the calculation array width smaller than the filter width. Simulation results show that for AlexNet and VGG16, the execution speed of ERS dataflow is improved by about 60% compared with row stationary dataflow, and the hardware resource utilization is improved by about 30%. For the MobileNet V1, the execution speed of ERS dataflow is improved by about 4% compared with the row stationary dataflow.

This work introduces a data model, compiler and runtime interpreter to drive the logic of animation graphs in game engines. The primary purpose of an animation graph is to allow for animation logic to be evaluated in a data driven way, which enables game programmers and animators to work iteratively and in parallel. The combination of animation blend trees and hierarchical state machines serves to empower animators to break down the complexity into simpler units with precise and predictable control over animation sampling and the transitions between them. Additionally, the system also serves as a synchronization point between game play elements and animation with input parameters and output events which can potentially trigger other systems such as audio and visual effects. The result is a standalone library which can be used as a foundation in a project and expanded with additional functionality as required. Detta arbete introducerar en data model, kompilator och körmiljö för att driva logiken av animationsgrafer i spelmotorer. Huvudsyftet av en animationsgraf är att tillåta datadrivet animationslogik vilket möjliggör spelprogrammerare och animerare att arbeta iterativt och parallellt. Kombinationen av animationblandningsträd och hierarkiska statmaskiner ger animerare ett sätt att bryta ner komplexa problem till mindre enheter med exakt och förutsägbar kontroll av animationer och övergångar mellan dem. Systemet verkar också som en synkroniseringspunkt mellan spelelement och animation med inmatningsparameterar och utgående händelser som potentiellt kan utlösa andra system som ljud- och visuella effekter. Resultatet är ett fristående programbibliotek som kan användas som en startpunkt i ett projekt och vars funktionalitet kan utökas vid behov.

In this paper, we introduce the concept of Multi-Reader Buffers (MRBs) for high throughput and memory-efficient implementation of dataflow applications. Our work is motivated by the huge amount of data that needs to be processed and typically accessed in a FIFO manner, particularly in image and video processing applications. Here, multi-cast, fork, and merge operator implementations known today produce huge memory overheads by storing and communicating copies of the same data. As a remedy, we first introduce MRBs as buffers preserving FIFO semantics for a finite number of readers of the same data while storing each data item only once. Second, we present an approach for memory minimization of data flow networks by replacing all multi-cast actors and connected FIFOs with MRBs. Third, we present a Design Space Exploration approach to selectively replace multi-cast actors with MRBs in order to explore memory, throughput, and processor resource allocation tradeoffs. Our results show that the explored Pareto fronts of our approach improve the solution quality over a reference by 78% in average for six benchmark applications in terms of a hypervolume indicator., OASIcs, Vol. 108, Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023), pages 6:1-6:13

We present Golden Gate, an FPGA-based simulation tool that decouples the timing of an FPGA host platform from that of the target RTL design. In contrast to previous work in static time-multiplexing of FPGA resources, Golden Gate employs the Latency-Insensitive Bounded Dataflow Network (LI-BDN) formalism to decompose the simulator into subcomponents, each of which may be independently and automatically optimized. This structure allows Golden Gate to support a broad class of optimizations that improve resource utilization by implementing FPGA-hostile structures over multiple cycles, while the LI-BDN formalism ensures that the simulator still produces bit- and cycle-exact results. To verify that these optimizations are implemented correctly, we also present LIME, a model-checking tool that provides a push-button flow for checking whether optimized subcomponents adhere to an associated correctness specification, while also guaranteeing forward progress. Finally, we use Golden Gate to generate a cycle-exact simulator of a multi-core SoC, where we reduce LUT utilization by up to 26% by coercing multi-ported, combinationally read memories into simulation models backed by time-multiplexed block RAMs, enabling us to simulate 50% more cores on a single FPGA.

Artificial Intelligence workloads have grown in popularity over the last decade, but database query processing runtimes are also evolving to keep up with increased demand. This report investigates whether the memory and compute profiles of Data Science/Analytics applications can benefit from techniques used to optimize Machine Learning workloads. In other words, expressing database operators as data-centric coarse-grained kernels with dynamic shape dimensions may enable the merging of Machine Learning (ML) and query runtimes into one. Since database applications are traditionally optimized for CPU performance and heterogeneous computing environments are becoming the norm, performance is being left on the table if SQL queries continue to only use the CPU. This report attempts to reuse state-of-the-art tensor-based runtimes for query/database workloads and evaluate the performance against traditional data-analytics frameworks. Reasoning about scheduling/execution primitives in a composable way can unlock new opportunities for system-level performance optimizations (e.g., eliminating unnecessary materialization, eliding compute that is not used downstream, etc.). Even though workload profiles and work dispatch strategies between Machine Learning (ML) and Data Analytics appear similar at first glance, differences in the type system, compute characteristics, and expressiveness in the program description push these domains farther apart instead of closer together. Although current ML frameworks do not provide compelling performance on database-style workloads, there is room in the ecosystem to support much better interoperability between these two domains.

International audience; Dataflow programming is considered a good solution for the implementation of parallel signal processing applications. However, the strict separation between kernel and coordination codes limits the variety of possible optimizations and the compatibility with state-of-the-art compiler frameworks. We present a prototype static dataflow compiler, built with the LLVM MLIR framework, that overcomes these limitations and enables a previously impossible combination of optimization strategies that leverages information from the dataflow topology. Initial results show 30% wall time improvement and 53% memory usage improvement on a video processing workload.

Using artificial intelligence (AI) components to solve real-world heterogeneous tass is more than simple plug and play type integration and often necessitates tight coupling of components. With current state of the art, such integration consumes large engineering effort due to problems like low expressivity, modularity, reusability, and abstraction. To alleviate these problems, a dataflow graph-based functional programming model is proposed to integrate AI components as microservices. Along with loose coupling, the integration platform also allows tight coupling of components to solve complex heterogeneous tasks without compromising modularity. A graphical method of construction of integration programs relieves a developer from learning programming syntax. The usability of the proposed method has been demonstrated by solving a heterogeneous maze problem where an agent needs to solve a reinforcement learning environment, a machine vision task, and integrate them. Solving a speech recognition problem demonstrates modularity and functional abstraction of the method. Qualitative comparison with current state-of-the-art methods based on these use cases justifies the claims.

Over the past decade, distributed dataflow systems (DDS) have become a standard technology. In these systems, users write programs in restricted dataflow programming models, such as MapReduce, which enable them to scale out program execution to a shared-nothing cluster of machines. Yet, there is no established consensus that prescribes how to extend these programming models to support iterative algorithms. In this survey, we review the research literature and identify how DDS handle control flow, such as iteration, from both the programming model and execution level perspectives. This survey will be of interest for both users and designers of DDS.

Internet of Things (IoT) applications are often designed as dataflows that analyze sensor data in real-time to make decisions. Stream processing systems like Apache Storm execute these on Cloud infrastructure. As IoT applications within shared data environments like smart cities grow, they will duplicate tasks like pre-processing and analytics. This offers the opportunity to collaboratively reuse the outputs of overlapping dataflows, improving the resource efficiency on Clouds. We propose dataflow reuse algorithms that when given a submitted dataflow, identify the intersection of reusable tasks and streams from existing dataflows to form a merged dataflow, with guaranteed equivalence of their output streams. Algorithms to unmerge dataflows when they are removed, and defragment partially reused dataflows are also proposed. We implement these algorithms for the Storm fast-data platform, and validate their performance and resource savings using 86 real and synthetic dataflows from eScience and IoT domains. Our reuse strategies reduce the number of running tasks by 34 - 45% and the cumulative CPU usage by 29 - 63% . Including defragmentation of incremental dataflows achieves a monetary savings on Cloud resources of 36 - 44% compared to dataflows without reuse, and has limited redeployment overheads.