Back to Search
Start Over
Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods
- Source :
- UPCommons. Portal del coneixement obert de la UPC, Universitat Politècnica de Catalunya (UPC)
- Publication Year :
- 2021
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2021.
-
Abstract
- When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable information is often lost during physical synthesis. This paper proposes HiDaP, a novel multi-level algorithm that uses RTL information and analytical methods for the macro placement problem of modern designs dominated by multi-cycle connection pipelines. By taking advantage of the hierarchy tree, the netlist is divided into blocks containing macros and standard cells, and their dataflow affinity is inferred considering the register latency and flow width of their interaction. The layout is represented using slicing structures and generated with a top-down algorithm capable of handling blocks with both hard and soft components. An adaptive multi-objective cost function is used to simultaneously minimize wirelength, timing, overlap and distance to preferred locations, which can be user-defined or generated by analytic methods (spectral and force-directed). These techniques have been applied to a set of large industrial circuits and compared against state-of-theart commercial and academic placers, and also to handcrafted floorplans generated by expert back-end engineers. The proposed approach outperforms previous algorithmic methods and can produce solutions with better wirelength and timing than the best handcrafted floorplans. Post-routing layouts are almost brought to timing closure and DRC cleanness with minimal engineer modification, showing that the generated floorplans provide an excellent starting point for the physical design flow and contribute to reduce turn-around time significantly. This work has been partially supported by a grant from Inphi Corporation and funds from the Spanish Ministry for Economy and Competitiveness and the European Union (FEDER funds) under grant TIN2017-86727-C2-1-R, and the Generalitat de Catalunya (2017 SGR 786).
- Subjects :
- Standards
Circuits integrats -- Disseny i construcció
Layout
Dataflow
Computer science
Shape
Enginyeria electrònica::Microelectrònica::Circuits integrats [Àrees temàtiques de la UPC]
Timing closure
Computer Graphics and Computer-Aided Design
Slicing
Tools
Set (abstract data type)
Tree (data structure)
Computer engineering
Integrated circuit modeling
Netlist
Manuals
Timing
Electrical and Electronic Engineering
Macro
Physical design
Integrated circuits -- Design and construction
Software
Subjects
Details
- ISSN :
- 19374151 and 02780070
- Volume :
- 40
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Accession number :
- edsair.doi.dedup.....2d632d12d32016a8b7e1222e79ca4379
- Full Text :
- https://doi.org/10.1109/tcad.2020.3047724