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Collaborative communication produces high power gain and significantly reduces bit error rate BER if both frequency and phase synchronization are achieved. In this paper, a novel collaborative communication system with imperfect phase and frequency synchronization that includes the influence of noise and fading is proposed, modeled, theoretically analyzed, and simulated. Mathematical expressions are derived for the received power as a function of number of collaborative nodes and BER as a function of signal to noise ratio Ebi¾?N0. To analyze the energy efficiency of our proposed collaborative communication system, energy consumption of the system is modeled, simulated, and analyzed by considering the parameters of the off-the-shelf products. Analytical and simulation results showed that the proposed system produces significant power gain and reduction in BER in the presence of phase errors, frequency errors, additive white Gaussian noise, and Rayleigh fading. A detailed theoretical analysis and Monte Carlo simulation revealed that the proposed collaborative communication system is an energy efficient communication system that can be implemented in sensor networks, as approximately N number of collaborative nodes times less total transmitted power is required than for the single input single output communication for a specifies transmission range. Copyright © 2012 John Wiley & Sons, Ltd.

The Wireless Sensor Network (WSN)-based pipeline monitoring systems are expected to have long life time in order to make their deployment cost-effective. In reality, wireless transceivers are considered one of the main consumers of energy in individual sensor nodes of WSNs. The duty cycling technique which puts transceiver module into sleep state for the majority of sensor node's operating time is considered a highly effective method to reduce energy consumption. In this paper we present the use of Wake-on-Radio (WoR) for reduction of used energy and conducted power consumption experiments using CC430-based WSN nodes. The results show promising performance improvement when using WoR in the CC1101 radio transceiver of CC430. Then, an adaptive duty cycle algorithm based on the WoR functionality, which enables sensor nodes to dynamically adjust their WoR duty cycles according to the real-time wireless channel conditions in achieving reduced power consumption, was proposed.

Standalone inertial navigation system (INS) in indoor pedestrian positioning is becoming imminent as the researchers exploit its small form factor and low power requirement. This will result in small-size, low-power wearable devices that are not obtrusive to the users and yet provide sufficiently accurate pedestrian localization and tracking within. At this stage, most of the recent INS-based indoor pedestrian positioning systems still have to interface with other computing machines such as a laptop or smartphone to perform computationally demanding algorithms. Most of the existing techniques operate in off-line and not real-time mode. In this paper, we propose a real-time indoor pedestrian dead-reckoning system based on embedded INS. The results show that our system successfully track the distance travelled by pedestrians up to an error of three percent with a position update interval less than a second.

The high demand for genuine honey leads to fraud practices in the market which have disadvantaged top graded genuine honey production. The conventional chemical analysis procedures are usually used to ensure the quality and authenticity of honey. Yet, some drawbacks, such as time-consuming, laborious, invasive and required complex sample preparation, in the chemical approaches make the optical spectrum based honey analysis an advantageous alternative method. This paper reports a comprehensive survey of peer-reviewed articles in honey analysis using spectroscopy techniques. The technologies, features, and preprocessing and prediction methods from the observed articles have been discussed to give an overview about optical spectrum approaches for honey analysis. This paper quickly introduces reseachers to modern honey analysis research.

There is a growing need for new biosensing technologies that are more rapid and convenient to use for onsite sensing. Impedance-based electrochemical sensor is a promising candidate due to simplicity of its sensing mechanism. However, like other emerging biosensors, specificity, sensitivity, and reliability are major obstacles that limit their use in real-life applications. Electrode geometry and 3D shape design optimization have been popular research directions for improved sensor performance. The aim of this study is to develop a finite element modelling approach that allows calculation of electrode impedance for different electrode shapes under standard biological test medium. In addition, a method for comparing sensor sensitivity is also developed using bacterial target as case study. Impedance simulations were performed for different electrode shapes, namely flat, ridge, and trough. The effects of target binding on solution conductivity and diffusion were simulated. It was found trough shaped electrode showed the greatest change in diffusion impedance upon target recognition. However, different shapes gave maximum change in solution impedance depending on the position of bound target.

GALS-Designer is a framework for the design of software systems which comply with the formal Globally Asynchronous Locally Synchronous model of computation (GALS). Those systems consist of single or multiple GALS programs and their immediate environment, which can be other programs and any other modules described in SystemC. The framework integrates our libGALS library for writing GALS programs and SystemC. It enables modeling and simulation of single and multiple GALS programs within the single SystemC executable model on the host (simulation) operating system. The same GALS programs can then be run without SystemC on a target operating system for which the libGALS runtime library is available. The use of the GALS-Designer is demonstrated on an example of a complex embedded system. As libGALS can execute on multiprocessor platforms both the simulation and target models of the GALS system can take advantage of multiprocessor and multicore systems, which is not possible when using standard SystemC. Results of running simulation models of GALS programs demonstrate simulation performance improvement when executing on multicore platforms.

A novel silicon-based light emitting structure comprising a lithium doped zinc oxide film and a high energy electrons generating silicon structure is presented. Red light emission with wavelength of ~630 nm is generated and recorded in electroluminescent spectrum under an applied DC voltage of 8.5 V.

We present a hardware-software coprocessing speech recognizer for real-time embedded applications. The system consists of a standard microprocessor and a hardware accelerator for Gaussian mixture model (GMM) emission probability calculation implemented on a field-programmable gate array. The GMM accelerator is optimized for timing performance by exploiting data parallelism. In order to avoid large memory requirement, the accelerator adopts a double buffering scheme for accessing the acoustic parameters with no assumption made on the access pattern of these parameters. Experiments on widely used benchmark data show that the real-time factor of the proposed system is 0.62, which is about three times faster than the pure software-based baseline system, while the word accuracy rate is preserved at 93.33%. As a part of the recognizer, a new adaptive beam-pruning algorithm is also proposed and implemented, which further reduces the average real-time factor to 0.54 with the word accuracy rate of 93.16%. The proposed speech recognizer is suitable for integration in various types of voice (speech)-controlled applications.

The use of formal models of computation in dealing with increasing complexity of embedded systems design is gaining attention. A successful model of computation must be able to handle both control-dominated and data-dominated behaviors, which are most often simultaneously present in complex embedded systems. Besides behavioral heterogeneity, direct support for modeling distributed systems is also desirable, since an increasing number of embedded systems belong to this category. In this paper, we present distributed DFCharts (DDFCharts), a language based on a formal model that targets distributed heterogeneous embedded systems. Its top hierarchical level is made suitable to capture distributed systems. Behavioral heterogeneity is addressed by composing finite-state machines (FSMs) and synchronous dataflow graphs (SDFGs). We illustrate modeling in DDFCharts with practical examples and describe its implementation on heterogeneous target architecture.

The smart pebble (SP) has been developed to monitor sediment transport in riverbeds. The implementation employs small size and low-cost acceleration and angular motion sensors. In this paper, we focus on calibration and testing of the final version of the SP, as well as its packaging in a 4-cm diameter spherical package. Error analysis of the sensors as well as the whole system has been modeled to evaluate the performance of the final system's outputs. The calibration was done in two separate stages: individual sensor calibration and overall system calibration. The complete SP unit was tested under linear motions generated by a shake table, and 2-D rotational motions using two manually controlled servomotors. Offline signal conditioning was done in MATLAB. Errors due to misalignment and gravity have been reduced. Experiments conducted by sampling a 1-Hz sinusoidal signal at different rates show that to keep the amplitude errors of the system under 5%, the sampling rate has to be at least ten times the maximum bandwidth of the signals acquired from the sensors. The SP has been tested in a real flume and the results show that the system provides enough accuracy in measuring its own accelerations as it moves inside the flume.

Collaborative communication produces high power gain and significantly mitigates the fading if both frequency and phase synchronization are achieved. In this paper, a novel collaborative communication system with imperfect phase synchronization that includes the influence of noise and Rayleigh fading is proposed, modelled, theoretically analyzed and simulated. Mathematical expressions for both received power as a function of number of collaborative nodes and bit error rate (BER) as a function of SNR (E"b/N"0) are derived. To analyze the energy efficiency of our proposed collaborative communication system, energy consumption of the system is modelled, simulated and analyzed by considering the parameters of the off-the-shelf products. Exploration of performance shows that the proposed system mitigates the fading, hence, significant power gain and significant reduction in BER can be achieved in the presence of phase errors, AWGN and Rayleigh fading. A detailed theoretical analysis and Monte Carlo simulation revealed that proposed collaborative communication system is an energy efficient communication system that can be implemented in sensor networks as approximately N (number of collaborative nodes) times less total transmitted power is required than for the single-input single-output (SISO) communication for a specific transmission range.

IEC 61499 has been endorsed as the standard for modeling and implementing distributed industrial process measurement and control systems. The standard prescribes the use of function blocks for designing systems in a component-oriented approach. The execution model of a basic function block and the manner for event/data connections between blocks are described therein. Unfortunately, the standard does not provide exhaustive specifications for function block execution. Consequently, multiple standard-compliant implementations exhibiting different behaviors are possible. This not only defeats the purpose of having a standard but also makes verification of function block systems difficult. To overcome this, we propose synchronous semantics for function blocks and show its feasibility by translating function blocks into a subset of Esterel, a well-known synchronous language. The proposed semantics avoids causal cycles common in Esterel and is proved to be reactive and deterministic under any composition. Moreover, verification techniques developed for synchronous systems can now be applied to function blocks.

In this paper, a novel ambient intelligence (AmI) platform is proposed to facilitate fast integration of different control algorithms, device networks and user interfaces. This platform defines the overall hardware/software architecture and communication standards. It consists of four layers, namely the ubiquitous environment, middleware, multi-agent system and application layer. The multi-agent system is implemented using Java Agent DEvelopment (JADE) framework and allows users to incorporate multiple control algorithms as agents for managing different tasks. The Universal Plug and Play (UPnP) device discovery protocol is used as a middleware, which isolates the multi-agent system and physical ubiquitous environment while providing a standard communication channel between the two. An XML content language has been designed to provide standard communication between various user interfaces and the multi-agent system. A mobile ubiquitous setup box is designed to allow fast construction of ubiquitous environments in any physical space. The real time performance analysis shows the potential of the proposed AmI platform to be used in real-life AmI applications. A case study has also been carried out to demonstrate the possibility of integrating multiple control algorithms in the multi-agent system and achieving a significant improvement on the overall offline learning performance.

The frequency of a power system is an important operational parameter for the safety, stability, and efficiency of the power system. Accurate and fast measurement of frequency is a goal required in many applications, for example, for load shedding. An improved Taylor approximation method (ITAM) algorithm is proposed, and a comparison of the new algorithm with the conventional Taylor approximation method (TAM) algorithm is presented in this paper under the assumption of the presence of a direct-current (DC) offset component, higher order harmonics, and random noise in the power system signal. The proposed ITAM has the characteristics of low computational and simple hardware requirements, as well as more accurate measurement performance. Another key feature of the algorithm is a good tracing ability for the frequency change and measurement of rate of change of the frequency of a power system.

Esterel programs have traditionally been compiled to software code for general purpose processors or to hardware netlists. This paper, instead, proposes a reactive processor for the direct execution of Esterel. This intermediate approach offers the same flexibility as software compilation, while at the same time, providing much better code size and execution time. The proposed architecture, called STARPro, is a pipelined, multithreaded, reactive processor that provides native support for the direct execution of Esterel. STARPro manages Esterel threads and their scheduling, and also features a hardware preemption unit to assist the handling of the abort constructs in Esterel. In addition to the proposed architecture, we have also developed a new intermediate format called UCCFGsd (unrolled concurrent control-flow graph with surface and depth) to represent the structure of an Esterel program in our compiler. UCCFGsd closely resembles the Esterel source, and it has also been designed with Esterel hardware support in mind, allowing a straight forward translation into STARPro assembly instructions. We have compared the performance of STARPro against a recent reactive architecture and found an average of 37% speed-up in worst-case reaction times, and 38% in average-case reaction times.

SystemJ is a language based on the Globally Asynchronous Locally Synchronous (GALS) paradigm. A SystemJ program is a collection of GALS nodes, also called clock domains, and each clock domain is a synchronous program that extends the Java language. Initial compilation of SystemJ has been to standard Java executing on a Java Virtual Machine (JVM), which is both inefficient and bulky for small embedded systems. This article proposes a new approach for compiling and executing SystemJ using a new type of virtual machine, called a Tandem Virtual Machine (TVM). The TVM approach provides an efficient implementation of SystemJ on both standard processors and resource-constrained embedded processors. The new approach is based on separating the control-driven and data-driven operations for execution on two virtual machines. While the JVM executes the data-driven operations, a Control Virtual Machine (CVM) is introduced to execute the control-driven parts of a SystemJ program. The TVM approach is capable of handling all data-driven and control-driven operations required by the GALS model. The benchmark results show that the TVM has code size improvements of over 60% on average and also a substantial improvement in execution speed over standard Java-based compilation.

The model-driven approach to software development has been increasingly applied to manage the growing complexity in modern manufacturing systems. With this approach, a model of a system is first created at a high-level of abstraction. The model is then converted into an executable program by means of automatic code generation tools. Models can be simulated and visualized throughout the entire design flow of the system, thereby increasing confidence of the design's correctness and its adherence to user requirements. Moreover, since the design is specified at a higher level of abstraction, the description itself is easier to understand, and consequently, less prone to errors. However, automated code generation from high-level models have typically been inefficient compared to hand-crafted code. In this paper, we demonstrate an approach for generating efficient code for systems modelled using IEC 61499 function blocks. We have also developed a tool chain that allows complex material handling systems to be modelled, visualized, and synthesized in a seamless fashion. Experimental evaluations show that our approach produces significantly faster and smaller code compared to an existing tool.

In this paper we present a methodology for optimizing complex datapath oriented digital circuits. An optimizer was developed based on the earlier development of an automatic circuit synthesizer that synthesizes hardware description language specifications based on available functional modules. A genetic algorithm is tailored to the problem of digital circuit optimization through the development of specific structures and procedures. In particular, a concise encoding of the circuit is developed that the genetic algorithm can manipulate. Specific crossover and mutation mechanisms are also developed to complement the functionality of the synthesizer. The searches are effected by altering module data type, hardware resource sharing, and module implementation version. A fitness function is derived that makes use of a number of optimization parameters to objectively evaluate each particular circuit. The features of each circuit are calculated and estimated during the analysis phase.

This article describes the features and development of intelligent machines and concentrates on their information processing infrastructure. IEC 61499 function blocks have been used in these experiments as the driving vehicle to achieve important features of the intelligent machines such as reconfigurability. Information infrastructure of intelligent machines is based on the IEC 61499 architecture . The function block architecture of IEC 61499 provides a new degree of flexibility in managing embedded control and information processing systems through the lifetime of industrial automation products. The requirements of flexible manufacturing and material handling systems, such as rapid integration and reconfiguration, as well as the growing information intensity of the production environments imply that manufacturing equipment is becoming more autonomous and intelligent.

The synchronous approach featuring deterministic concurrency is widely used to design and verify real-time embedded systems. The synchronous model of computation divides the execution of a program into discrete instants, called ticks. For correctly capturing all input events from the environment, it is pivotal to statically estimate the worst case tick length, also known as the worst case reaction time (WCRT) of synchronous programs. Plenty of techniques have been proposed for WCRT analysis of synchronous programs targeting uniprocessors, but little has been done for chip-multiprocessors (CMPs). Concurrent accesses to the shared bus of a CMP are managed by the bus arbitration policy for eliminating access contentions. The common time division multiple access (TDMA) approach equally divides the bus bandwidth amongst all processors in a CMP, and is oblivious to the bus access contention patterns, thus resulting in large WCRT overestimates. In this paper we propose an application-specific TDMA (ASTDMA) bus scheduling approach, which takes into account the bus access contention pattern of the application and results in shorter static WCRT estimates. Experimental results reveal that the ASTDMA approach achieves on average 21.33% shorter WCRT estimates compared to the standard TDMA scheduling policy.

This paper presents enhancements of Service Oriented SystemJ (SOSJ) framework, which extends a system-level language based on GALS model of computation SystemJ with services, into a new programming paradigm amenable for designing dynamic distributed automation systems such as reconfigurable manufacturing systems. The new paradigm combines correct-by-construction software systems development available in SystemJ with the dynamic features of service oriented architecture. The new approach introduces macro states into fundamental concurrent and distributed entities of SOSJ, called clock domains, which address typical behaviors in dynamic distributed systems. We showcase the use of the new paradigm on an example of reconfigurable manufacturing scenarios in a dynamic manufacturing system.

The realization of intelligent services relies on ubiquitous data access which is envisaged by the concept of the Internet of Things (IoT). The foundation of IoT is the rapid growth in the area of Wireless Sensor and Actuator Networks (WSANs). However, diversity and heterogeneity of WSANs in terms of communication networks pose challenges in integrating a wide range of networks into a unified IoT infrastructure. Redesigning communication infrastructure to accommodate different or new networks increases engineering time and cost. To address the inflexibility an FPGA-based reconfigurable gateway architecture is proposed in this paper. Any number and type of radio interfaces can be plugged in and made operational directly during runtime without decommissioning and redesigning the entire gateway device. By using this gateway, physically incompatible protocols are bridged to achieve seamless communications. Software layers running on top of the gateway virtualize the underlying heterogeneous networks and hence enable transparent communications for higher level intelligent services. The implemented prototype was evaluated using three use cases to demonstrate flexible and reconfigurable integration of heterogeneous WSANs.

Embedded sensors are increasingly seen in modern mobile and wearable devices to support better user activities and vital signs monitoring. While more wireless sensing devices are becoming available, network connectivity and scalability remain the key obstacles in achieving seamless information flow and service provision as envisaged by the vision of the Internet of Things. In this paper, a mobile 6LoWPAN network architecture is proposed by engaging Android-based mobile devices as edge routers to address the connectivity and scalability issues with the wider IP network for pervasive healthcare applications. The 6LoWPAN-based wireless sensor network, together with the Android edge router, form a mobile sub-network that allows seamless information exchange with the Internet and improves service availability for each end user. The proposed architecture includes a customised bare-metal 6LoWPAN protocol designed for ultra low power wireless sensor nodes for long term vital signs monitoring and integrated with Android devices for mobile internet access. The proposed network architecture is demonstrated and validated on a pervasive healthcare monitoring application.

Previous studies on physical activity recognition have utilized various fixed window sizes for signal segmentation selected based on past experiments and hardware limitations. Specifically, there is no optimum fixed window size because it is subject to the characteristics of the activity signals. This paper presents a novel approach of activity signal segmentation for enhanced physical activity recognition. Central to the approach is that the window size could be dynamically adjusted by using signal information to determine the most effective segmentation. The approach recognizes not only well defined static and dynamic activities, but also transitional activities. The presented approach has been implemented, evaluated and compared with an existing approach and the fixed sliding window approach in a number of experiments. Results have shown that dynamic window segmentation achieved better overall accuracy of 96% in all activities considered in the experiments compared to the existing approach.

A new programming paradigm that supports development of adaptive distributed control systems found in many applications, such as flexible manufacturing systems, is introduced in the paper. The paradigm merges two powerful concepts, a formal GALS language SystemJ suitable for designing concurrent static programs and service oriented architectures suitable for dynamic system composition. The new tool, called SOSJ, designed based on the proposed paradigm has the strengths from both sides and can support programming adaptive distributed systems. The use of the new design tool and methodology is illustrated on an example of a distributed manufacturing system. It demonstrates usability and ease of design with SOSJ in developing flexible, dynamic and faulttolerant manufacturing systems.

An electro-permanent magnet based actuator has been proposed to control microvalves, which significantly reduces the energy consumption of solenoid type microvalves. Electro-permanent magnets are designed with combined hard and semi-hard magnetic materials to control the direction of the magnetic flux. Power is supplied to these magnets only to change the polarity of a magnet so that it can attract or repel the load. Therefore, power is only consumed to toggle between the states of the valve, while the actuator requires no power to maintain either close or open states at other times. Initial experiments revealed that a voltage as low as TV can be applied across the coil to switch the magnetization direction, which resulted in drawing a current of 1.76A during the current pulse duration of 100µs. The momentary power consumption was 12.37W, but the total energy consumption was only 1.237mJ for a state toggling. For applications where the valves are operated infrequently, this technique is highly energy economical as power is consumed for a very short period of time during actuation. Supercapacitor buffering is suggested to smooth out the energy requirement of the proposed actuator to make wireless low power transfer a possible solution for microfluidic systems with infrequent valve operations.

Modern manufacturing systems are best examples where networked embedded controllers and mechatronic devices form the so-called distributed cyber physical systems (CPS). Design and deployment of such systems pose significant challenges to traditional PLC-based software design approaches. In this paper, a unified framework for the design and deployment of such systems based on a formal language, SystemJ, is presented. The proposed framework supports implementing distributed CPS at system level abstraction with correct by construction design. The designed software components can easily interact with each other and with web-based interface for modelling and validation via simulation and subsequently run on embedded controllers without any change, which simplifies the design and implementation process significantly. An ice-cream manufacturing system (ICMF) example is presented to illustrate the proposed approach.

This paper presents an extensible and adaptable platform for distributed applications with mixed criticality based on using state of the art FPGA technology. Although capable of executing programs written in different languages, the platform specifically targets the execution of programs written in Globally Asynchronous Locally Synchronous language SystemJ used in the context of Internet of Industrial Things. The key properties of the prototype platform are accommodation of mixed-criticality processing as well as provision of Internet addressable services. Mixed-criticality execution platform (MCEP) uses multiple processor cores and network interfaces: (1) a dual-core ARM processor with Ethernet for Internet access and processing of non-real -- time application parts and (2) TP-JOP reactive hard real-time processor with customized Controller Area Network (CAN) for real-time and time-critical response processing. This platform has been successfully developed and used in an industrial automation system within the Internet of Industrial Things context.

Interoperability between shop floor devices and upper layer systems is a key challenge for enabling Internet of Things in industrial applications. Standardized protocols such as IPv6, CoAP, and XML can be used to address this issue. Widely used XML-based technologies such as SenML, EEML, OPC-UA as well as others rely on XML to be able to support a wide range of sensor and actuator applications. However, this approach results in high communication overhead due to the verbose nature of plain text messages encoded in XML. When devices are communicating using 6LoWPAN over IEEE 802.15.4, it is important to keep the messages small enough to fit into one MAC-layer frame to avoid fragmentation and hence conserving bandwidth and transmission energy. One possible solution is to integrate differential binary delta-encoding with a service-based framework based on CoAP, SenML and EXI. The proposed efficient communication approach for service-based architecture can compress a series of events up to 90-95%. The proposed framework is a holistic approach for enabling distributed monitoring and control applications and a move towards realizing the vision of Services of Things. Validerad; 2016; Nivå 1; 20150105 (jench) I2Mine, Arrowhead

Force Sensitive Resistors (FSRs) are used for kinetic evaluation of human gait by measuring under foot pressures during gait. FSRs from different manufacturers, with variation in morphologies and loading capacities were selected in past research projects. However a functional comparison of different FSRs and options on how to choose them for gait analysis is not established yet. In this work, investigation and comparison of behavioral patterns in measuring normal gait from two major FSR sensors are done. These FSRs had been utilised previously for the purpose of gait sensing. They were placed underneath the heel alternatively to detect heel pressures while wearing footwear with laces and with another footwear possessing straps for harnessing. Both sensors are connected to a miniature low power wireless senor node used for data collection and wireless transmission for off-line analysis of pressure patterns. The results give good indications on capabilities and trade-offs when using the two sensors types.

The advancement of embedded sensing and wireless communication technologies facilitate the possibility of continuous monitoring of our activities and surrounding environment. This leads towards many practical applications such as environmental monitoring, structural health monitoring, wearable and context aware computing which could not be easily done in the past. However, design of wireless sensor nodes and networks for such applications need to follow stringent application requirements to ensure precise measurement, long operating life, reliability under varying thermal and impact conditions, and reasonable communication range. In this paper, a low power miniaturised wireless sensor node (or mote) is designed targeting ubiquitous data acquisition applications. The mote has a modular architecture to meet different application requirements. It is built using ultra low power miniaturised components with a novel power regulation method for achieving long operating life with the overall physical dimension of 30mm x 16mm. It works at sub-1GHz frequency range to allow better obstacle penetration and communication range of up to 1.7km. The mote is planned to be deployed in various applications including earthquake simulation experiments for measuring soil movement and wearable body area networks for vital signs monitoring.

Energy consumption is a vital component in day-today life. Visualising energy consumption, recommending energy conserving strategies and, controlling the appliances are some of the widely considered means to motivate and/or to help end-users at household to conserve energy. However, the conventional energy visualisation applications have certain drawbacks, such as lack of energy consumption location, lack of controlling appliances based on energy-saving recommendations, etc. To overcome those, this research would accomplish a simulation model by designing the following: (i) visualisation engine, to visualise household electricity consumption, (ii) recommendation engine, to provide energy-saving recommendations to the end-users, (iii) control engine, to control the household appliances based on the recommendations, and (iv) integrate visualisation, recommendation and control engines. This research uses a combination of user-centred design and iterative development methods. Successful implementation of these objectives would provide a significant contribution to this inter-disciplinary research area and would serve to achieve higher energy savings.

This paper proposes a new software composition method for automated machines that exploits their mechatronic modularity. It is demonstrated that desired behavior of a certain class of machines can be composed of behaviors of its mechatronic components, including fully decentralized scheduling and operation control. This aims at increased performance of software design and maintenance, as well as systems’ flexibility and reconfigurability. The IEC 61499 Function Blocks’ (FBs) architecture is used as an implementation platform that enables system-level simulation and transparency of deployment. A configurable pick-and-place (PnP) manipulator with decentralized control synthesized using the proposed approach is chosen as an illustrative example.

After the cancellation of selective availability in May 2000, the accuracy of plain uncorrected global positioning systems (GPSs) is significantly increased. Currently, the main cause of error in plain GPS receivers is imperfect compensation of the ionospheric error. Tests performed in New Zealand show that even a simple code range differential GPS (DGPS) provides significant improvement in accuracy over a plain GPS and can be implemented using low-cost off-the-shelf equipment. A simple statistical model of positioning error estimation is developed and applied on data obtained by measurements in order to verify the findings. The method, which needs only position information without satellite constellation, provides sufficient accuracy when simultaneously gathered plain GPS and DGPS data are compared

This article addresses the need for directly expressing heterogeneous, hierarchical behaviors for modeling specific embedded systems. After analyzing two existing ESL languages, SystemC and Esterel, the authors create a new model of computation and a graphical language to gain the direct expressivity they need for their model. Although researchers have suggested various changes to SystemC and Esterel to fit modeling requirements, this article considers mainly standard SystemC and Esterel

Recursive-least-square (RLS) algorithm is widely used in many areas with real-time implementation using digital signal processors. In this paper, the authors present a pure hardware implementation of a self-tuning regulator (STR) that uses a real-time RLS algorithm as the parameter estimator. The STR contains a controller design circuit and a controller circuit. Due to RLS computation-precision and dynamic-range requirements, the hardware implementation uses a floating-point format. The floating-point processing elements presented in this paper use parameterized design, where the number of exponents and mantissa bits can be changed as the data range and the accuracy of a specific application require. The strategies for overcoming the covariance matrix asymmetrical problem during the hardware computation and the covariance matrix resetting is introduced when the system is poorly exciting are presented. The design was verified with real-time experiments using a new testbed. The experiment results are presented.

Embedded systems are typically heterogeneous requiring interacting hardware and software components, are locally synchronous while being globally asynchronous and combine both control and data dominated blocks. Conventional architectures and hardware–software platforms do not directly support such heterogeneity leading to complex design flow and verification process for such systems. This paper presents a new architecture for heterogeneous embedded systems called HiDRA based on multiple reactive processor cores. The architecture supports globally asynchronous locally synchronous systems with a mix of data-dominated and control-dominated behaviors. The reactive processor cores implement Esterel-like computation with architectural support for signal polling, emission and preemption. HiDRA also provides primitives for communication and synchronization between concurrent processes. A low level (concurrent reactive assembly) language has been specified to model embedded applications, which are executable directly on the HiDRA platform. The first implementations with up to four reactive processors have been done on the standard FPGAs. Performance comparison with a typical application realized from system level language ECL reveals significant speedup and reduction in code size.

Inertial-based indoor pedestrian tracking that uses Micro electro mechanical Systems (MEMS) technology suffers undesirable positional drift over time. As widely attested, zero-velocity updates (ZUPT) from the stance phase reduce the error growth from a third order polynomial to a linear one. However, researchers are struggling to find consistent ZUPT, especially when the pedestrian walks naturally, which has changes in walking speed or unpredictable pauses. In this paper, a novel approach to extract the ZUPT based on subtractive clustering is proposed and discussed. Its performance is compared to other techniques using internally collected and publicly available datasets. The results show that the proposed method outweighs the others in providing consistent performance level.

In this paper a detailed mathematical model of a 1/n rate conventional convolutional decoder system, based on neural networks (NNs) applications and the gradient descent algorithm, has been developed and analysed. The general expression for the noise energy function, needed for the recurrent neural networks (RNNs) decoding, is derived. Then, the expressions for the gradient descent updating rule are derived and the NN decoder was designed. Based on the developed theory, a simulator of the decoder was implemented. Simulation results have confirmed that the RNN decoder is capable of performing very close to the Viterbi decoder and works extremely well for some specially structured convolutional codes. In particular, decoding capabilities of RNN decoders are investigated in the case when simulated annealing (SA) technique has been used. It is also shown that there are certain codes that do not require SA and can achieve performance comparable to the Viterbi algorithm.

Specification of embedded systems based on formal models of computation is gaining importance. The behavior of an increasing number of embedded systems is heterogeneous, consisting of a mixture of control-dominated and data-dominated parts. While models of computations suitable to control-dominated systems and data-dominated systems are well developed, there are only a limited number of models catering to both systems. In this paper, we present informally a new model for heterogeneous embedded systems, called HEMOC, which combines three common models of computation, synchronous reactive, hierarchical finite state machines and synchronous data flow. Then, the languages Esterel and SyncCharts are used for system specification following the new model in order to determine what they need to become suitable specification platform.

Efficient and reliable interaction with the environment (reactivity) is a key feature for many embedded system applications. Current implementation technologies that include standard microprocessors and microcontrollers, or fully customized systems, are not ideally suited to such reactive tasks either in terms of their performance constraints or in terms of design implementation and programming. We propose a microprocessor architecture that has native Esterel-like support for reactivity, flexibility of using programs and design styles as used in Esterel programming language for reactive embedded system implementation and provides time-predictable behaviors in reaction to external events. The new processor, called REFLIX, is built around already existing processor core and exploits its flexibility in allowing customization at much higher level than usual microprocessor cores. REFLIX shows manifold improvement in speed and memory footprint in dominantly reactive applications compared to the traditional microprocessors.

This paper presents a system development environment for embedded applications based on custom-computing machines implemented in field programmable logic devices (FPLDs). The concept uses the fact that FPLDs enables convenient way for implementing customised and reconfigurable digital systems. The custom-computing machines are based on a flexible instruction execution unit, which is a general-purpose microprocessor that allows addition of more complex processing elements in the form of functional units. The system development environment contains a number of tools that allow high-level description of the both processor core and functional units and produces VHDL synthesisable code, which can be processed by any VHDL compiler, and automatic generation of all basic software development tools such as customised cross-assembler and C compiler.

Submicron zinc oxide (ZnO) spheres prepared by a two-stage hydrothermal method were assembled into a layer on a substrate by vertical deposition. Vanadium pentoxide (V2O5) was deposited onto the top of ZnO spheres by magnetron sputtering followed by annealing in oxygen atmosphere at 500[Formula: see text]C for an hour. The microstructures and optical properties of the prepared samples were investigated. The photoluminescence (PL) results indicate that the intensity of PL in the annealed ZnO/V2O5 composite microstructures is dramatically improved compared to the constituent V2O5 and ZnO spheres. The intensity enhancement of light emission from the ZnO/V2O5 composite may be attributed to the special microstructure of ZnO particles and the coupling effect between ZnO and V2O5. This transition oxide composite may possibly be developed into a new type of high-efficiency light emitting material.

We propose a novel silicon structure, Hot Electron Emitting Substrate (HEES), which exhibits important effect of repeated tunneling at two different voltage ranges, which we refer to as double tunneling. In ambient atmosphere and room temperature, the [Formula: see text]–[Formula: see text] characteristic of HEES shows two current peaks during voltage sweep from 2 to 15 V. These two peaks are formed by the Fowler–Nordheim (FN) tunneling effect and tunneling diode mechanism, respectively.

A cardiac pacemaker example is used to compare and contrast the Synchronous Reactive (SR) programming model of SystemJ with the SCJ programming model. Our pacemaker is implemented in the synchronous subset of the Globally Asynchronous Locally Synchronous (GALS) SystemJ, which extends the Java language with reactivity, concurrency and real-time constructs based on a formal mathematical framework. The use of different programming models results in different design choices and implementations. The SR programming model is driven by a logical clock, which clearly demarcates the state boundaries and is ideal for formal verification of functional and real-time properties. Unlike the preemptive scheduling model prescribed by the SCJ specification, the SystemJ program execution model is atomic and non-preemptive between two logical ticks, and as such it is statically schedulable without the need for a runtime scheduler. To check the effectiveness of the SystemJ approach, we implemented the cardiac pacemaker on three different execution platforms that demonstrate feasibility of guaranteed real-time of the pacemaker execution with a fraction of the used processor's resources.

We present a novel approach for design of manufacturing automation systems with formal verification of selected properties based on the use of Globally Asynchronous Locally Synchronous programming language SystemJ and industrial-proof verification tools. By being able to prove properties of the automation control logic that consists of multiple concurrent controllers, represented by FSMs that correspond to asynchronous processes of SystemJ program, using Spin model checker, we demonstrate that the program features can be formally verified. Moreover, by also guaranteeing preservation of features and GALS model of the SystemJ program after compilation (correct by construction specification), we actually close the design process within What You Prove Is What You Execute (WYPIWYE) Paradigm.

We face a glut of languages for programming distributed software today. However, only a few languages have proven their potential with wider practical use in different domains of computing. We picked two such languages, meant for different domains, to see if they could cross-pollinate and enrich one another. Specifically, we chose SystemJ, a language to program distributed embedded systems, and IEC61499, the next generation standard for distributed industrial automation control software. Unsurprisingly, we found similar structures and artifacts between the two. We also found significant differences mainly due to differing domain-specific requirements. This comparison leads to observations and guidelines for improving both languages, and we discuss directions towards an “ideal” distributed software programming language.

Static estimation of the Worst Case Reaction Time (WCRT) of synchronous programs is pivotal for designing hard-real time systems in these languages. The current approaches to WCRT estimation suffer from either large overestimation of the WCRT value or the state space explosion problem. In this paper, we present TACO: a framework that integrates model checking based WCRT estimation with code optimization techniques, which results in close to optimal WCRT estimates with orders of magnitude reduced worst case runtime complexity. Finally, the TACO framework also allows us to generate executables with a smaller overall memory footprint.

International audience; We tackle the problem of designing and programming dynamic and reactive systems with four objectives: being based on a formal model of computation, using different types of concurrency, being efficient, and tolerating failures. The challenge lies in the fact that good formal models with very high level of abstraction generally result in non-efficient implementations. We propose a 'C' based library approach following the formal Dynamic Globally Asynchronous Locally Synchronous (DGALS) model of computation. We show how a DGALS system can be dynamically constructed from concurrent behaviors on distributed platforms thanks to the DGALS paradigm. Finally, our experimental results clearly indicate the large execution time and memory footprint gains compared to the current state of the art approaches.