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FPGA-based Mixed-Criticality Execution Platform for SystemJ and the Internet of Industrial Things

Authors :
Heejong Park
Manu Sharma
Ding Ding
Kevin I-Kai Wang
Dez Packwood
Zoran Salcic
Avinash Malik
Source :
ISORC
Publication Year :
2015
Publisher :
IEEE, 2015.

Abstract

This paper presents an extensible and adaptable platform for distributed applications with mixed criticality based on using state of the art FPGA technology. Although capable of executing programs written in different languages, the platform specifically targets the execution of programs written in Globally Asynchronous Locally Synchronous language SystemJ used in the context of Internet of Industrial Things. The key properties of the prototype platform are accommodation of mixed-criticality processing as well as provision of Internet addressable services. Mixed-criticality execution platform (MCEP) uses multiple processor cores and network interfaces: (1) a dual-core ARM processor with Ethernet for Internet access and processing of non-real -- time application parts and (2) TP-JOP reactive hard real-time processor with customized Controller Area Network (CAN) for real-time and time-critical response processing. This platform has been successfully developed and used in an industrial automation system within the Internet of Industrial Things context.

Details

Database :
OpenAIRE
Journal :
2015 IEEE 18th International Symposium on Real-Time Distributed Computing
Accession number :
edsair.doi...........37c375ea8da9bc85207ec293a0538e70