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Es wird eine Blitzlampenspiegelanordnung vorgestellt, die eine homogene und schnelle Erwärmung von Halleitersubstraten bei unwesentlich höheren Anlagenkosten ermöglicht.

Vortrag anlässlich eines vertraulichen Projekttreffens bei der Creavis-Degussa AG

Thin poly-crystalline silicon films are attractive for the fabrication of active matrix liquid crystal displays. We investigate the use of flash lamp annealing to crystallize amorphous silicon layers on glass substrates as a low cost manufacturing route. In this process amorphous silicon (a-Si) can be crystallized by solid phase crystallization (SPC) or in the super lateral growth (SLG) regime. We present a thermal model incorporating the phase transitions during annealing; providing a valuable tool for optimizing the process conditions. Another consideration is the evolution of stress resulting from the transient thermal loading of the substrate material. Results are presented for various substrate geometries and important scalability issues are addressed.

Sub-second annealing is one of the key issues to meet the requirements of the 45 nm technology node according to the ITRS roadmap. Therefore, over the past decade there has been great interest in techniques such as laser and flash lamp annealing (FLA). In addition, advanced ultra-fast annealing shows promise for technologies that are not directly related to Si device processing. The main reason for using FLA in alternative applications is the reduced thermal budget because of the short annealing time, which enables one to achieve high temperatures (> 500°C) in the near-surface region while keeping the substrate bulk relatively cold. This is of particularly high importance for the development of novel polymer-based electronics and flexible solar cell technologies, where the substrates cannot withstand temperatures in excess of 150°C. An overview of theoretical simulations and related results from FLA experiments for a variety of layered systems is given. The influence of the flash duration and intensity on the heat distribution and the resulting physical properties is considered. Design and performance issues of the FLA tools depending on the specific uses and technical requirements are addressed. Furthermore, topics covered include high-throughput applications e.g. for roll-to-roll production of polymer substrates. Results of a prototype tool for multi-flash processing up to a frequency of 1 Hz using a pulse duration of 1 ms are also discussed.

Using bulk silicon can be ended for 32 nm technological nodes. New type of substrates needs for further scaling in CMOS microelectronics. We speculate that these new type of materials will be semiconductor heterostructure on insulator (SHI) compatible with current silicon planar CMOS technology. Joint semiconductor material stack placed on cheap amorphous dioxide is presented. First of all thin film SiGe heterostructure properties is considered. It was obtain using Ge ion implantation in dioxide with followed Ge segregation to the directly bonded interface between silicon and silicon dioxide wafers. The method is also compatible with A3B5 thin film formation.

Flash lamp annealing of heteroepitaxial silicon carbide on silicon structures involves melting the silicon below the SiC layer but the facetted nature of the liquid-solid interface leads to unacceptable surface roughness. This paper describes a method of controlling melting by using a melt stop created at a controlled depth below the Si / SiC interface by implanting a high dose of carbon, which significantly increases the silicon melting temperature. Results confirm the effectiveness of the technique in reducing roughness.

Due to the lattice misfit between the silicon and the silicon carbide lattices the epitaxial deposition of SiC layers normally results in a highly defected carbide layer. Short time annealing seems to be an effective method to improve the crystal structure of the epitaxial layer using intense light pulses from flash lamps. From the present point of view the annealing mechanism is based on the rapid melting of a thin silicon interface layer due to the intense light pulse, giving the non molten SiC layer the possibility for relaxation and annealing. Consequently, after the pulse is over and the liquid silicon intermediate layer solidifies epitaxially on the monocrystalline substrate one receives a high temperature annealed epitaxial SiC on silicon structure. Although the annealing of the SiC layer due to the flash irradiation could be verified by TEM investigations a serious problem remains, connected with the facetted melting of the monocrystalline silicon surface after rapid heating above the melting temperature. Due to the layer by layer crystallisation within the molten pyramides, including a lateral growth component and due to the 5 % higher density of liquid silicon in comparison to solid silicon a surface relief will be formed after the solidification process is completed. Two techniques were tested to circumvent the deep facetted melting. The first procedure to homogenize the melting depth is based on the introduction of a so called melt stop layer in a certain depth below the SiC / Si interface. For this purpose carbon admixture which increases the melting temperature of silicon was implanted at a dose of 2*1017cm-2 and a energy of 140 keV through a 30 nm thick SiC layer into silicon, forming a approximately 200 nm thick melt barrier in a depth of 400 nm. As a further possibility to prevent the facetted melting ion implantation of germanium admixture as a element reducing the melting temperature of silicon was tested. It could be experimentally shown that both, the introduction of a melt stop layer at any depth behind the Si / SiC interface as well as the modification of the silicon surface, leading to a decrease of the silicon melting temperature, are usefull methods for the homogenization of the melting depth at the bulk silicon surface.

Recently a new interest evolved in short time annealing far below 1 sec, i.e. the lower limit of Rapid Thermal Processing (RTP). This was driven by the need of suppressing the so-called Transient Enhanced Diffusion in advanced boron-implanted shallow pn-junctions. After a short common overview about the new opportunities in materials processing, in this talk two examples will serve for the demonstration of the new interest in flash lamp annealing (time duration < 20 msec) within the framework of semiconductor materials processing: (i) For ultra-shallow junction formation in silicon Flash Lamp Processing (FLP) has become one of the challenging methods to meet the requirements for the next technology nodes defined by the ITRS roadmap. Low energy boron implants have been heat-treated in this way using peak temperatures in the range of 1100o to 1300oC and effective anneal times of 20 msec and 3 msec. Optimum processing conditions using a pulse time of 3 msec have been identified, under which one can obtain combinations of junction depth and sheet resistance values that meet even the 45 nm technology node requirements (ITRS 2001). (ii) The production of cubic SiC (3C-SiC) layers in device quality through the epitaxial growth on (100) Si wafers has remained a challenging task yet to overcome for selected applications the need in high cost bulk SiC wafers. It will be demonstrated that the use of Flash Lamp Processing (FLP) shows a new and promising way to the production of high quality 3C-layers. The FLASiC process bases on a new type of nanoscale liquid epitaxy at the interface SiC/Silicon leading to the formation of SiC seed layers with low defect density on which thicker SiC layers were epigrown.

It could be shown that both, the introduction of a melt stop layer in any depth behind the Si / SiC interface and the installation of a surface layer, decreasing the silicon melting temperature, are usefull methods to homogenize the melting depth in the bulk silicon.

The paper gives an overview of our recent work in the field of thermal processing of advanced semiconductor structures by millisecond flash lamp annealing (FLA). Topics covered include ultra-shallow junction (USJ) formation and heteroepitaxial growth of improved quality thin films of cubic silicon carbide (3C-SiC). The latter is a new development, which opens up promising 3C-SiC growth possibilities and may lead to wider application of FLA. The so-called FLASiC process (Flash LAmp Supported Deposition of SiC) is based on a new type of nanoscale liquid-phase epitaxy at the SiC/Si interface resulting in the formation of a thin, low defect density seed layer of SiC onto which thicker epitaxial SiC layers can be grown.

An approach for the defect density reduction in 3C-SiC epitaxially grown on Si is to improve the quality of the carbonized layer during the early stage of growth. For this reason the conventional carbonization process was replaced by a slower and nearer equilibrium carbonization method. Carbon is introduced by implantation into oxide of an ocidized Si substrate, near the SiO2/Si interface, and then it is transferred to the Si surface by annealing. Good quality 3C-SiC grains are formed embedded into the Si substrate, which are absolutely flat at the SiO2/Si interface. Another advantage of the new carbonization process is the elimination of the cavities due to the suppression of Si out-diffusion.

In the present study cubic 3C–(Si1–xC1–y)Gex+y solid solutions were created by using ion beam synthesis. 3C–SiC thin layers grown on on-axis Si (111) substrates by Molecular Beam Epitaxy were implanted with Ge in order to incorporate Ge atoms in the Silicon Carbide lattice. Two series of experiments were carried out. The implantation energy was chosen to be 140 keV and 200 keV and the implantation dose 1 × 1017 cm–2 and 4.7 × 1016 cm–2 respectively. The samples were annealed under rapid thermal annealing conditions in the temperature range between 800 °C and 1300 °C. X-ray diffraction measurements indicate an enlargement of the lattice constant. The observed higher absorption in the implanted layers could be a sign of a band gap reduction as a consequence of Ge incorporation.

The process of formation of excess vacancies by ion implantation is explained. Moreover, the simulation of the process, the experimental detection of excess vacancies and their application for defect engineering is described.

The epitaxial 3C-SiC formation at the SiO2/Si interface by C+ Implantation into SiO2 and subsequent annealing is studied.

A thermal model for flash lamp annealing of 3C-SiC/Si multilayer systems is developed.

The capabilities of plasma doping (PLAD) and flash lamp annealing (FLA) for use in ultra-shallow junction (USJ) fabrication have been evaluated. Silicon wafers have been doped in a BF3 plasma using wafer biases ranging from 0.6 to 1 kV and a dose of 4 × 1015 cm−2. The wafers so implanted have been heat-treated by FLA using pre-heating temperatures in the range of 500–700 °C, peak temperatures of 1100–1350 °C, and effective anneal times of 20 and 3 ms. Secondary ion mass spectrometry (SIMS) and sheet resistance measurements have been undertaken to determine the junction depth and the sheet resistance, respectively. Optimum processing conditions have been identified under which both high electrical activation and insignificant dopant diffusion occur compared to the as-implanted state. In this way, one can obtain combinations of junction depth and sheet resistance that meet the 45 nm technology node requirements.

This paper describes the development of a thermal model for flashlamp processing of 3C-SiC on silicon. The model is a numerical solution of the enthalpy equation, using a modified Crank-Nichelson scheme to combine accurate prediction of melt depths with resonable computation times.

Advanced Thermal Processing of Semiconducting Materials using Flash Lamp Annealing is Discussed.

The production of cubic SiC (3C-SiC) layers in device quality through the epitaxial growth on (100)-Si wafers has remained a challenging task yet. Recently, it was demonstrated that the use of Flash Lamp Processing (FLP) can support the production of high quality 3C-SiC layers in a promising manner. The FLASiC team organized within a project of the V. Framework of the European Community is currently extending this early work as a broader approach with the following main aspects: a) Development of the epitaxial process including FLP, b) Development of a prototype equipment for the FLP, and c) Demonstrating the improved quality at dedicated devices. In this talk a short overview will be given regarding the latest advancements of this new approach.

Die Erfindung betrifft ein Verfahren zur Behandlung heteroepitaktisch auf SOI-Substraten abgeschiedener Halbleiterschichten. Die Erfindung soll insbesondere für die Herstellung elektronischer Bauelemente eingesetzt werden.

Higher integration in semiconductor technology causes the need for ultra-shallow junctions. Novel techniques are necessary to achieve abrupt and sharp profiles of dopants at high activation levels without significant diffusion of dopants. Because common RTP techniques are limited in temperature ramping speed, alternative methods for ultra-short time annealing are of great interest. In this paper we report on recent results from flash lamp annealing (FLA). Si (100) wafers were implanted with 500eV B+ ions to a fluence of 1015 cm-2. FLA was carried out at temperatures in the range 1100-1200°C with a soak time of 2-20ms using a bank of xenon flash-lamps. With this technique the final temperature is reached within one millisecond. Preheating of the samples from the rear side was performed at 250, 500 and 750°C by a bank of halogen lamps. For comparison conventional RTP was performed at 1100°C and 1200°C for the shortest reliable time of 1s and longer times up to 80 s. The boron diffusion and the dopant activation were investigated by secondary ion mass spectroscopy (SIMS) and spreading resistance profiling (SRP). The activated doses after FLA were as high as 20% of the implanted dose confined in a layer of only 60nm. The mechanical deformation induced to the samples due to the heat shock was investigated with X-ray reflection. The intensity of the specularly reflected beam (CuK radiation, scattering angle = 0.8°) is detected as a function of the incidence angle. The profile width and the distances between possible subsidiary peaks give integral values of the surface waveness.

In this paper we discuss ion-beam-assisted nanocrystal nucleation in amorphized silicon (a-Si) layers produced by high-dose implantation of Pb+ and Bi+. (100)-oriented Si wafers were implanted at room temperature (RT) with 50 keV Pb+ and Bi+ ions at doses ranging from 5E13 to 1E18 cm−2 and a constant ion current density of 10μAcm−2. The resulting structures were studied by conventional transmission electron microscopy (CTEM), high resolution transmission electron microscopy (HRTEM) and Rutherford backscattering spectroscopy (RBS) in combination with computer simulations. The dynamics of the ion-beam-induced crystallization of new phases and precipitates evolution in the implanted layer were studied as a function of implant dose. It is established that the front of the new phase crystallization (cubic Pb and hexagonal Bi nanocrystals) starts approximately at the peaks of the implanted species profiles; the crystallography of the nucleated nanocrystal is examined as a function of the dose.

The lattice damage of silicon produced by ion implantation at extremely high current density of 0.8 A/cm2 (2.5 x 1018 cm-2 s-1) was investigated. In a focused ion beam system, implantation was carried out with 70 keV Co ions, fluences of 1.2 x 1016 cm-2 and 6.7 x 1015 cm-2 into Si (111) at room temperature and elevated temperatures between 355 °C and 400 °C. Radiation damage measurements were performed by Rutherford backscattering/channeling spectroscopy and micro-Raman analysis. The radiation damage was studied as a function of pixel dwell-time and implantation temperature. The critical temperature for amorphization increases with current density. Although the fluence of the focused ion implantation was constant, crystalline layers were obtained for short and amorphous layers for long pixel dwell-times. The critical dwell-time of crystalline/amorphous transition increases with implantation temperature. From the results a typical time for defect annealing of 10-5 s at 400 °C and an activation energy of (2.5±0.6) eV were deduced.

Thermal wave measurements on 6H-SiC with a particular emphasis on Al+ and Al+/N+ implanted 6H-SiC was carried out. The 6H-SiC wafers were implanted at different substrate temperatures. The photothermal measurements of the conversion coefficient K and the reflectivity R show a strong dependence on the implantation temperature. This result is discussed in relation to Rutherford backscattering spectrometry/ion channeling measurements. The behaviour of the reflectivity in dependence on the implantation conditions could be modelized by using a simple two layer optical model. The carried out investigations of the implanted SiC demonstrate, that photothermal methods are suitable for both research and on-line production use.

Metodami photolumineszensii, kombinirovannove rassejania i spektroskopii obratnogo rasseania alpha tschastiz issledovano formirovanie zentrov rekombinationnogo uslutschenia pri otschige sloev SiO2, implantirovannich ionami Ge.

Spektri emissii i wosbuschdenia photoluminescencii pri komnatnoi temperature plenok Si3N4 implantirovannich plenok Ge+ i Ar+, issledovanui v savisimosti ot dosui ionov i temperaturui posledujuschego otschiga.

Cobalt disilicide microstructures were formed by 70 keV Co2+ focused ion beam implantation into Si(111) at substrate temperatures of about 400°C and a subsequent two step annealing (600°C, 60 min and 1000°C, 30 min in N2). It was found that the CoSi2 layer quality strongly depends on the pixel dwell-time and the implantation temperature. Only for properly chosen parameters countinuous CoSi2 layers could be obtained. Scanning electron microscopy and Rutherford backscatting/channelling investigations were carried out combined with a special preparation technique damage was investigated as a function of dwell-time (1-250 µs) and target temperature (355-415°C). The results show that the irradiation damage increases with the dwell-time.The Si top layer was ammorphization for longer dwell-times although the substrate temperature was always above the critical temperature for amorphization of about 270°C according to the model of Morehead and Crowder. For the high current density of a focused ion beam (1-10 A/cm2) the damage creation reate is higher than the rate of dynamic annealing.

This work is an attempt to model the fundamental processes that occur when 6H-SiC is implanted at elevated substrate temperatures with high doses of N+ and Al+ ions to synthesise thin buried layers of (SiC)1-x(AlN)x.

Computer simulation and RBS/C studies of high-dose N + and Al + co-implantation in 6H-SiC

A series of experimental and theoretical investigations has been initiated for 6H–SiC samples sequentially implanted with high doses of N+(65 keV) + N+(120 keV) + Al+(100 keV) + Al+(160 keV) ions at temperatures between 200 and 800 °C. Nitrogen and carbon distribution profiles are measured by ERD and structural defect distributions are measured by Rutherford backscattering with channeling. A comparison between the experimental data and the results of computer simulation yields a physical model to describe the relaxation processes of the implanted SiC structure, where the entire implanted volume is divided into regions of different depth, having different guiding kinetics mechanisms.

We studied high dose implantation of tungsten into 6H-silicon carbide in order to synthesize an electrically conductive layer. Implantation was performed at 200 keV with a dose of 1.2×10(17) W(+)cm(-2) at temperatures between 200°C and 400°C. The influence of implantation temperature on the distribution of W in SiC was investigated and compared to results obtained earlier from room temperature (RT) and 500°C implants. Rutherford backscattering spectrometry (RBS) was employed to study the structure and composition of the implanted layers. Implantation at temperatures between RT and 300°C did not influence the depth distribution of C, Si and W. The W depth profile shows a conventional Gaussian shape. Implanting at higher temperatures led to a more confined W rich layer in the SiC. This confinement is explained by Ostwald ripening which is enabled during implantation at temperatures above 300°C. The depth of the implantation induced damage decreases slightly with increasing implantation temperature, except for 400°C implantation. The amount of damage, however, is significantly reduced only for implantation at 500°C.