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Unmanned aerial vehicles (UAVs) have played an important role in wireless communications due to the advantages such as highly controllable mobility in three-dimensional (3D) space, swift deployment, line-of-sight (LoS) aerial-ground links, and so on. In this paper, we consider a UAV-enabled two-way relaying system where the UAV relay assists the information exchange between two ground users (GUs) under three different schemes, i.e., four-slot multi-hopping (FSMH) without network coding (NC), three-slot NC and two-slot physical NC (PNC). Firstly, the capacity region of each scheme in this relaying system is analyzed. Then, we maximize the system average sum rate by jointly optimizing the time resources allocation, transmission powers of the transceivers, and the UAV trajectory subject to the constraints on UAV mobility and information causality under each scheme. To solve those problems, we propose an iterative algorithm by applying the successive convex approximation and block coordinate descent techniques. Specifically, the time resources allocation, transmission powers and the UAV trajectory are alternatively optimized in each iteration. In addition, the non-convex trajectory optimization problem is solved by successively solving an approximate convex optimization problem. To gain more insights, we also investigate the performance of those three schemes with symmetric and asymmetric traffic respectively by introducing a new traffic pattern constraint. Numerical results show that the proposed relaying schemes with moving relay can achieve great throughput gains as compared to the conventional scheme with static relay. The three relay schemes also show great performance heterogeneity under different traffic patterns.

As an auxiliary to the electricity market, the traditional frequency regulation market (FRM) lacks reliable data storage ways and direct transaction channels for buyers and sellers, and the cost-sharing method of frequency regulation (FR) service is still unfair. To this end, this article proposes a general and decentralized FRM framework based on multiblockchain techniques. According to the scheduling sequence of transactions, the FR services are divided mainly into before-the-fact transactions (BFTs) and after-the-fact transactions (AFTs). We construct a combinatorial double-auction model for BFTs and propose a novel cost-sharing model based on triggers for AFTs. Taking Pennsylvania-New Jersey-Maryland as an example, we design a consensus algorithm for the on-chain transaction process and cost sharing. Numerical results on both types of transactions show that the proposed auction model can meet the different needs of FR buyers. The proposed sharing method highlights that triggers from frequency events should result in higher costs. The consensus algorithm also improves the fault tolerance and throughput of transactions.

MAC-layer frame aggregation has significantly improved the efficiency of IEEE 802.11n and 802.11ac networks by placing multiple MAC-layer data units in a large PHY-layer frame. In this paper, we focus on finding the optimal length of an Aggregated MAC Protocol Data Unit (A-MPDU) in order to maximize throughput. In theory, larger A-MPDUs amortize overheads over more bits and therefore increase throughput. However in practice, throughput can be negatively impacted if too many frames are aggregated, due to higher error rates at the end of A-MPDUs. Determining the optimal number of subframes is challenging because error rates can be higher in the later part of the A-MPDU which change with factors such as mobility, speed and transmission rate. Additionally, there are dependencies between consecutive A-MPDUs due to software retransmissions. We develop a model of A-MPDU frame aggregation and use it to design a statistically optimal algorithm. Using our understanding of that algorithm we develop a standard compliant, Practical, Near-Optimal Frame Aggregation algorithm (PNOFA). Our trace-based evaluation shows that across a variety of devices and scenarios PNOFA outperforms existing state-of-the-art algorithms and obtains throughputs that are within 97% of those obtained using the statistically optimal algorithm. Furthermore, we implement PNOFA as a user-space process on an 802.11ac Wave 2, Google Wifi access point. We find that when compared with the frame aggregation algorithm provided in the device’s Qualcomm IPQ 4019 chipset’s firmware, PNOFA increases average throughput by 17% and 13% for UDP and TCP traffic on the scenarios tested.

Driven by the massively growing applications in Internet of Things (IoT) and the new requirements of the six-generation (6G) wireless network, the amount of terrestrial mobile devices (TMDs) and data traffic in wireless communications have increased explosively. Consequently, the integrated terrestrial-satellite relay networks (ITSRNs) have emerged to address the issue of the huge wireless traffic with the limited allocated resources, which attracts extensive research attention to the field of IoT. However, previous research works in ITSRN mostly focus on terrestrial relays (TRs) configured on the ground, which can only perform limited improvement to the networks on system throughput. In this paper, by introducing an aerial relay (AR), we propose a novel structure of ITSRN and investigate the system throughput maximization and energy consumption minimization problems by jointly optimizing power allocation and AR altitude. In this system, the system implementation includes two periods: satellite to relay (S-R) period and satellite to devices (S-D) period. To maximize the overall system throughput, we propose a joint optimization scheme of the power allocation and altitude of AR. Specifically, due to the non-convexity of the original formulated problem, a bilevel programming method is proposed to obtain the global optimal solution, where the closed-form expressions of power allocation and the optimal altitude of AR are derived to reduce the complexity of the proposed scheme. Subsequently, we investigate the energy consumption minimization problem during S-R period, which is formulated as a convex problem. To achieve the minimum energy consumption, we propose a low complexity algorithm and derive the optimal closed-form solution based on the rigorous mathematical analysis. The effectiveness of the proposed algorithms and solutions are verified by extensive simulations.

In this paper, we address the issue of congestion in future Unmanned Aerial Vehicle (UAVs) traffic system in uncertain weather. We treat the traffic of UAVs as fluid queues, and introduce models for traffic dynamics at three basic traffic components: single link, tandem link, and merge link. The impact of weather uncertainty is captured as fluctuation of the saturation rate of fluid queue discharge (capacity). The uncertainty is assumed to follow a continuous-time Markov process. We define the resilience of the UAV traffic system as the long-run stability of the traffic queues and the optimal throughput strategy under uncertainties. We derive the necessary and sufficient conditions for the stabilities of the traffic queues in the three basic traffic components. Both conditions can be easily verified in practice. The optimal throughput can be calculated via the stability conditions. Our results offer strong insight and tool for designing flows in the UAV traffic system that is resilient against weather uncertainty.

The variations and uncertainties in complex assembly processes could cause conventional industrial robots failure to perform assemblies. Therefore, intelligent robots must be developed which can adapt to these variations and uncertainties; moreover, the assembly process parameters must be optimized to satisfy the performance requirements such as First Time Throughput (FTT) rate and cycle time. However, it is challenging to optimize the performance of complex robotic assembly systems. The existing solutions are not efficient and human knowledge is needed to perform experiments and explore optimal parameters. These requirements greatly limit the applications of robotic assembly in manufacturing automation. In this paper, a robotic assembly process optimization method is developed for complex assembly processes. We propose a modeling method based on Gaussian Process Regression (GPR) to construct a model to build the relationship between the process parameters (input) and system performance (output). The GPR surrogated Bayesian Optimization Algorithm (GPRBOA) is improved to iteratively optimize the robotic assembly performance. Two industrial assembly processes (a tight-tolerance peg-in-hole assembly process and a torque converter assembly process) are used to verify the proposed method. The experiments were performed many times and the results demonstrate that the proposed GPRBOA method can optimize the complex assembly process parameters effectively and efficiently. The proposed complex assembly process optimization method opens a door for online manufacturing process optimization and will greatly reduce the manufacturing cost.

As the demand for neural network operations on edge devices increases, energy-efficient neural network inference solutions become necessary. To this end, this paper proposes a compact 4-bit number format (SD4) for neural network weights. In addition to significantly reducing the amount of neural network data transmission, SD4 also reduces the neural network convolution operation from multiplication and addition (MAC) to only addition. MNIST and CIFAR-10 CNNs with SD4 weights achieve results similar to their FP32-trained counterparts. The difference between the top-1 accuracy of 4-bit ResNet CNN for ImageNet and the baseline FP32 CNN is less than 0.5%. In the hardware design, we have implemented a multiplier-less convolution acceleration circuit. Compared with the 8-bit weight circuit, the power consumption and area of a 4-bit 3x3 convolution circuit are reduced by nearly 50%. This work also proposes a systematic CNN deployment solution consisting of software CNN training and hardware acceleration. The proposed FPGA-based accelerator for VGG7 image classification achieves a peak throughput of 345.6 GOPS when running at a 100-MHz clock rate. The proposed convolution accelerator’s power consumption and energy efficiency are 1.19W and 289. 5 GOPS/W, respectively. Compared to the CPU implementation of VGG7-128 inference, the multiplier-less acceleration circuit is 4.8 times faster and achieves 384 times higher energy efficiency.

Accurate predictions from models based on physical principles are the ultimate metric of our biophysical understanding. Although there has been stunning progress toward structure prediction, quantitative prediction of enzyme function has remained challenging. Realizing this goal will require large numbers of quantitative measurements of rate and binding constants and the use of these ground-truth data sets to guide the development and testing of these quantitative models. Ground truth data more closely linked to the underlying physical forces are also desired. Here, we describe technological advances that enable both types of ground truth measurements. These advances allow classic models to be tested, provide novel mechanistic insights, and place us on the path toward a predictive understanding of enzyme structure and function.

IEEE 802.11ax partitions a regular 20MHz channel into smaller sub-channels called resource units to support simultaneous multiuser operation using orthogonal frequency division multiple access (OFDMA). Uplink OFDMA random access (UORA) in IEEE 802.11ax allows stations to transmit via a scheduled random access mechanism. UORA is initiated via a trigger frame which aside from serving as a synchronization mechanism, also informs stations which resource units are allowed for random access. Using the trigger frame information, the stations engage in an OFDMA backoff process to win access to a resource unit. Similar to slotted ALOHA, the maximum normalized throughput of UORA is only 37 percent due to high probability of collisions at high loads. To reduce collisions, we equip UORA with carrier sensing capability resulting in a new uplink hybrid UORA (H-UORA) OFDMA access mechanism. Unlike other multi-carrier CSMA methods previously proposed in literature, H-UORA is an easily implementable modification to current 802.11ax WLANs. We show that H-UORA can achieve a normalized throughput of at least 80 percent (which increases further depending on the buffering capabilities of the access point) using various numerical analysis and simulations.

Deep Neural Networks (DNNs) have shown superiority in solving the problems of classification and recognition in recent years. However, DNN hardware implementation is challenging due to the high computational complexity and diverse dataflow in different DNN models. To mitigate this design challenge, a large body of research has focused on accelerating specific DNN models or layers and proposed dedicated designs. However, dedicated designs for specific DNN models or layers limit the design flexibility. In this work, we take advantage of the similarity among different DNN models and propose a novel Lego-based Deep Neural Network on a Chip (DNNoC) design methodology. We work on common neural computing units (e.g., multiply-accumulation and pooling) and create some neuron computing units called NeuLego processing elements (NeuLegoPEs). These NeuLegoPEs are then interconnected using a flexible Network-on-Chip (NoC), allowing to construct different DNN models. To support large-scale DNN models, we enhance the reusability of each NeuLegoPE by proposing a Lego placement method. The proposed design methodology allows leveraging different DNN model implementations, helping to reduce implementation cost and time-to-market. Compared with the conventional approaches, the proposed approach can improve the average throughput by 2,802% for given DNN models. Besides, the corresponding hardware is implemented to validate the proposed design methodology, showing on average 12,523% hardware efficiency improvement by considering the throughput and area overhead simultaneously.

This paper is to explore the dynamical analysis and active control synthesis for improving seaport operations through system optimization. First, the multi-dimensional system of the fractional Lotka-Volterra model is utilized to investigate its underlying dynamics of port competition and cooperation for container throughput. The nonlinear dynamical behaviors are intensely examined by using eigenvalue evaluation, bifurcation analysis and time series analysis to illustrate the stability of the competition and collaboration model. With the system theory based on fractional order calculus, various dynamic properties of ports system have been discovered. Based on the dynamical analysis, adaptive fractional-order sliding mode control with artificial neural network algorithm has been realized for port growth rate improvement against disruptions. Furthermore, the proposed approach is successfully validated by the case study of major Korean seaports for improving port operations through neural network prediction. The decision making policies implemented by control algorithms are guaranteed to improve the port growth rate against disruptions. Specifically, the novel management strategy is to provide managerial insights and innovative solutions for seaport authorities who can make more efficient strategic planning for handling risk management in maritime logistics.

Non-destructive inspection of multi-pass welds for defects is traditionally performed once all layers have been deposited and the sample is at ambient temperature and therefore can lead to complicated and expensive rework, reduced throughput and higher lead times. By performing inspection either as the weld is deposited, or between weld passes, it is possible to identify defects earlier in the process and rectify them. Traditional ultrasonic inspection is severely limited in this application due to the high temperatures associated with the welding process and therefore, the authors describe a novel high-temperature ultrasound phased array roller probe to perform robotically delivered in-process inspection of multipass welds. The new roller probe is able to operate at temperatures up to 350 °C and perform angled weld inspection using 55° transverse waves. The wheel probe's endless rotation enables continuous inspection and makes it well suited to integrate within automated environments commonly employed for high integrity multipass welding applications. The probe demonstrated capability to detect calibration side drilled holes at room temperature and artificial defects embedded into a real weld at high temperature. The experimental results indicate potential to industrialise this prototype in the future.

PURPOSE The ability of next-generation sequencing (NGS) assays to interrogate thousands of genomic loci has revolutionized genetic testing. However, translation to the clinic is impeded by false-negative results that pose a risk to patients. In response, regulatory bodies are calling for reliability measures to be reported alongside NGS results. Existing methods to estimate reliability do not account for sample- and position-specific variability, which can be significant. Here, we report an approach that computes reliability metrics for every genomic position and sample interrogated by an NGS assay. METHODS Our approach predicts the limit of detection (LOD), the lowest reliably detectable variant fraction, by taking technical factors into account. We initially explored how LOD is affected by input material amount, library conversion rate, sequencing coverage, and sequencing error rate. This revealed that LOD depends heavily on genomic context and sample properties. Using these insights, we developed a computational approach to predict LOD on the basis of a biophysical model of the NGS workflow. We focused on targeted assays for cell-free DNA, but, in principle, this approach applies to any NGS assay. RESULTS We validated our approach by showing that it accurately predicts LOD and distinguishes reliable from unreliable results when screening 580 lung cancer samples for actionable mutations. Compared with a standard variant calling workflow, our approach avoided most false negatives and improved interassay concordance from 94% to 99%. CONCLUSION Our approach, which we name LAVA (LOD-aware variant analysis), reports the LOD for every position and sample interrogated by an NGS assay. This enables reliable results to be identified and improves the transparency and safety of genetic tests.

With the rapidly growing traffic demand, the cellular industry is moving toward heterogeneity to fulfill the heavy traffic requirement. The existing heterogeneous networks are comprised of the Long-Term Evolution (LTE), LTE-Advanced (LTE-A), and other compatible access technologies. It has been identified that due to the shortage of capacity, cell performance can deteriorate. To deal with users’ requirements, the 5G heterogeneous network architectures comprising LTE-advanced access technology with the combination of comparatively low configured small base stations, and macro eNodeBs (MeNB) have been extended as a solution. Therefore, operators have introduced the 5G with the existing LTE Advanced Heterogeneous Network (5GLHN) where small cells such as Home eNodeBs (HeNBs) are deployed overlapping with the conventional macro eNodeB (MeNB). However, in highly dense and closely compacted 5GLHNs, the cell capacity can still be lower than what is on-demand, thus affecting the system throughput. This article proposes a framework to maximize the throughput in 5GLHNs through a Constriction Factor Particle Swarm Optimization (CFPSO) technique of cell association and load-balancing algorithm to enhance the throughput of the 5GLHN. The proposed approach is designed to offload the traffic of MeNB Users (MUEs) to the small cells (HeNBs). The convergence, cumulative distribution function of the UEs rate, average throughput, and allocation time are analyzed to evaluate the performance of the proposed CFPSO approach. Simulation results reveal that the throughput of the proposed approach is improved by up to 44.08% of the existing index-based approach and by 94.20 \% of the existing Matching with Minimum Quota (MMQ) approach.

Emerging power services with massive connections and real-time control have different requirements on delay, rate, reliability, etc. In order to meet the diversified requirements of power services, network slicing can provide guarantee for the wide application of 5G in power. The current research on network slicing adapting power services is still in its infancy. This paper proposes a trade-off analysis method for radio access network (RAN) slice delay and throughput based on dynamic intelligent resource allocation to meet the different QoS requirements of different services in smart grid scenarios. Firstly, clustering analysis is used to classify the communication requirements of smart grid services. A throughput demand model for enhanced mobile broadband (eMBB) slice users based on importance and a delay constraint model for ultra-reliable and low latency communication (uRLLC) slice users are constructed, and a throughput model for slice users based on cell capacity limitation is constructed. Then, the problem model of maximizing the throughput of the eMBB slice by reasonably allocating resource blocks and power under the premise of ensuring the delay of the uRLLC slice is established. The Lyapunov drift plus penalty function method is used to convert the above problem into a tractable form, and then the problem is solved by the active set method. Simulation results show that the different QoS requirements of smart grid services will significantly affect the actual queue length of the uRLLC slice as well as the throughput of the eMBB slice.

Mobile edge computing becomes a promising technology to mitigate the latency of various cloud services. In addition, network function virtualization (NFV) has been shown a great potential in reducing the operational cost of cloud services while enhancing the flexibility of virtual network function deployments, by implementing dedicated hardware network functions as pieces of software in generic servers. Recently, the GPU acceleration has been investigated to speed up flow processing in virtual network functions (VNFs), by leveraging the parallelism of GPUs. VNFs that need accelerations prefer to stay at cloudlets (locations) equipped with GPUs. However, little attention has been paid for the VNF placement that takes into account GPU-affinity in cloudlets of mobile edge clouds. In this paper, we consider the affinity-aware throughput maximization problem in a mobile edge cloud via leveraging the parallelism on GPUs for user requests with VNF requirements. We consider two types of affinities in the VNF placement: The soft-affinity that allows VNFs to be executed by either CPUs or GPUs in cloudlets; and the hard-affinity that only allows VNFs to be placed to the GPUs of a specified set of cloudlets. We formulate two corresponding VNF placement problems in a mobile edge cloud. Specifically, we first propose an exact solution to the soft-affinity throughput maximization problem by formulating an Integer Linear Program (ILP). We then propose an efficient algorithm for the problem, by proposing a randomized algorithm with a provable approximation ratio for the hard-affinity-aware throughput maximization problem and extending the proposed approximation algorithm to the soft-affinity throughput maximization problem. Furthermore, assuming that user requests arrive into the mobile edge cloud one by one without the knowledge of future arrivals, we devise an online algorithm with a good competitive ratio for this dynamic hard-affinity-aware throughput maximization problem. Finally, we evaluate the performance of the proposed algorithms, through simulations and implementations in a real test-bed. Experimental results show that the performance of the proposed algorithms outperform their existing counterparts and achieve higher throughput.

Deep learning (DL)-based channel state information (CSI) feedback algorithms for massive multiple-input multiple-output (MIMO) can provide high beamforming accuracy to improve the throughput. However, bitstream errors in the feedback process can significantly affect the performance of CSI reconstruction. In this letter, we focus on building high reconstruction accuracy CSI feedback algorithm in the presence of bitstream errors. Specifically, we firstly introduce a DL-based architecture named ATNet, which can improve at least 2.96dB Normalized Mean Square Error (NMSE) compared with the existing algorithm. Then, we propose an error correction block called ECBlock and a two-step training strategy. Compared with traditional methods, the proposed scheme can reduce the influence of quantization and bitstream errors more effectively and improve the reconstruction accuracy.

With the development of the Internet of things (IoT), sensors are being mounted on various objects. This trend has prompted demand for low-power, high-performance information processing on the edge side. Here, an Ising model architecture that can efficiently solve optimization problems would be an efficient processing solution for edges. In this study, we implemented a 512-spin fully connected Ising model on an LSI chip fabricated in a 28-nm CMOS process. The fully connected Ising model was implemented in the chip by using pseudo-annealing (PA), which is easier to implement than simulated annealing (SA). In addition, we devised a multi-spin-thread structure, concurrent update structure, and a folded interaction placement for accuracy, speed, and compactness. Because eight spin threads are implemented, the calculation throughput could be increased by a factor of eight in comparison with a single spin-thread implementation. Moreover, as a measure of solution accuracy, the average route length of a 22-city traveling salesman problem was reduced by 19% and the standard deviation (SD) was reduced by 46%. Likewise, the average cut value of a 512-node max-cut problem was increased by 1.6% and SD was decreased by 60%. The concurrent update almost doubled the calculation speed in comparison with the case of no concurrent update. In addition, the circuit area was reduced by about 38% as a result of the folded interaction placement. The time required to obtain a solution was 128 ms. The chip at annealing processing (main processing) had a power consumption of 12 mW at 1 MHz.

Cryptocurrency networks such as Bitcoin have emerged as a distributed alternative to traditional centralized financial transaction networks. However, there are major challenges in scaling up the throughput of such networks. Lightning network and Spider network are alternates that build bidirectional payment channels on top of cryptocurrency networks using smart contracts, to enable fast transactions that bypass the Blockchain. In this paper, we study the problem of routing transactions in such a payment processing network. We first propose a Stochastic model to study such a system, as opposed to a fluid model that is studied in the literature. Each link in such a model is a two-sided queue, and unlike classical queues, such queues are not stable unless there is an external control. We propose a notion of stability for the payment processing network consisting of such two-sided queues using the notion of on-chain rebalancing. We then characterize the capacity region and propose a throughput optimal algorithm that stabilizes the system under any load within the capacity region. The stochastic model enables us to study closed loop policies, which typically have better queuing/delay pe

Battery energy-storage system (BESS) based on the modular multilevel converter (MMC) can flexibly manage the battery packs integrated into submodules, where the battery pack can directly or through a small capacitor connect to the rear-end half-bridge circuit for reducing cost and volume caused by an additional dc–dc converter. But the alternating current ripples will cause substantial additional charge throughput for battery packs and, consequently, reduce the battery lifetime in theory. Therefore, this article proposes a variable dc-link voltage regulation method for a single-phase MMC-BESS. In specific, the phase disposition (PD) modulation scheme is improved to properly bypass the gating signals with unnecessary conduction during operation and the modified gating signals will be rearranged for balancing the states-of-charge and states-of-health. Doing so, the additional charge throughput could be significantly reduced compared with the traditional phase-shift modulation and PD modulation. Even comparing with the ideal dc current charging/discharging, the proposed method will only increase slight additional charge throughput and nearly negligible capacity loss. The experimental results of a 6.6 kW/6.6 kWh single-phase MMC-BESS prototype verified the performance of the proposed method.

This investigation proposes a computing-in-memory (CIM) design to circumvent the von Neumann bottleneck which causes limited computation throughput for effective artificial intelligence (AI) applications. The proposed CIM performs multiple operations such as single-instruction basic Boolean operations, addition, and signed number multiplication, and multiple functions such as normal mode and retention mode for the built-in self-test (BIST). Its 2T-Switch requires only two transistors to be utilized for static random-access memory (SRAM) array; thus, the arithmetic unit can be chosen easily and the area overhead is minimized. Its ripple carry adder and multiplier (RCAM) unit based on single-ended disturb-free 7T 1-Kb SRAM was developed using the full swing-gate diffusion input (FS-GDI) technology that has full voltage swing resolution, low power consumption, and less chip area cost. Its Auto-Switching Write Back Circuit restores addition and multiplication operations automatically to assigned memory address. The CIM is implemented using the TSMC 40-nm CMOS process, where the core area is $432.81 \times 510.265\,\,\mu \text{m}^{2}$ . Among the related works, the proposed CIM performs the most number of operations and functions.

Non-orthogonal multiple access (NOMA) has drawn significant attention due to its high spectral efficiency. Invoking NOMA in heterogeneous networks (HetNets) can support ubiquitous connectivity and satisfy the growing demand for mobile data traffic. Existing studies on NOMA-enhanced HetNets mainly focus on network’s quality of service (QoS) metrics such as delay, throughput, coverage, etc. However, these parameters are not sufficient for evaluating the quality of experience (QoE) perceived by users. To that end, we propose a QoE-aware resource allocation framework for NOMA-enhanced HetNets under web browsing and video services. Specifically, a unified QoE-aware joint subchannel and power allocation optimization problem is formulated to maximize the sum mean opinion scores (MOSs) of all users, while guaranteeing the QoE requirement of each user. However, this problem is mixed-integer, non-convex, and intractable. To solve it, a penalty-based iterative algorithm is proposed. In particular, binary constraints on subchannel assignment variables are equivalently transformed into equality constraints via penalty method. Then, subchannel assignment and power allocation are alternately optimized in each iteration by leveraging block coordinate descent method and sequential parametric convex approximation techniques. Extensive numerical results show that the proposed scheme could achieve competitive QoE performance compared to existing NOMA and orthogonal multiple access schemes. acceptedVersion

For massive multiple-input multiple-output (MIMO) systems, linear minimum mean-square error (MMSE) detection has been shown to achieve near-optimal performance but suffers from excessively high complexity due to the large-scale matrix inversion. Being matrix inversion free, detection algorithms based on the Gauss-Seidel (GS) method have been proved more efficient than conventional Neumann series expansion-based ones. In this paper, an efficient GS-based soft-output data detector for massive MIMO and a corresponding VLSI architecture are proposed. To accelerate the convergence of the GS method, a new initial solution is proposed. Several optimizations on the VLSI architecture level are proposed to further reduce the processing latency and area. Our reference implementation results on a Xilinx Virtex-7 XC7VX690T FPGA for a 128 base-station antenna and eight user massive MIMO system show that our GS-based data detector achieves a throughput of 732 Mb/s with close-to-MMSE error-rate performance. Our implementation results demonstrate that the proposed solution has advantages over the existing designs in terms of complexity and efficiency, especially under challenging propagation conditions.

Native 2-D low-density parity-check (LDPC) codes provide 2-D burst erasure correction capability and have promising applications in two-dimensional magnetic recording (TDMR) technology. Though carefully constructed rastered 1-D LDPC codes can provide 2-D burst erasure correction, they are not as efficient as 2-D native codes constructed for handling the 2-D span of burst erasures. Our contributions are twofold. First, we propose a new 2-D LDPC code with girth greater than 4 by generating a parity-check tensor through stacking permutation tensors of size $p\times p\times p$ along with the $i,j,k$ -axes. The permutations are achieved through circular shifts on an identity tensor along different coordinate axes in such a way that it provides a burst erasure correction capability of at least $p\times p$ . Second, we propose a fast, efficient, and scalable hardware architecture for a parallel 2-D LDPC decoder based on the proposed code construction for data storage applications. Through efficient indexing of the received messages in an RAM, we propose novel routing mechanisms for messages between the check nodes and variable nodes through a set of two barrel shifters, producing shifts along two axes. Through simulations, we show that the performance of the proposed 2-D LDPC codes matches a 1-D QC-LDPC code, with a sharp waterfall drop of three to four orders of magnitude over ~0.3 dB, for random errors over code sizes of ~32 kbits or equivalently ~ $180\times 180 2$ -D arrays. Furthermore, we prove that the proposed native 2-D LDPC codes outperform their 1-D counterparts in terms of 2-D cluster erasure correction ability. For $p=16$ and code arrays of size $48\times 48$ , we implemented the proposed design architecture on a Kintex-7 KC-705 field-programmable gate array (FPGA) kit, achieving a significantly high worst case throughput of 12.52 Gb/s at a clock frequency of 163 MHz.

A reconfigurable field-programmable gate array (FPGA)-based wired-logic deep neural network (DNN) accelerator is presented. High energy efficiency of 16 nJ/classification (Modified National Institute of Standards and Technology: MNIST) is achieved due to the wired-logic architecture. Each neuron in the neural network consists of combinational circuits only, and all the neurons are implemented on an FPGA. Intermediate data are never stored in memory or registers and are transmitted to the output stage by passing through only neuron cells. The latency and power required for memory access can be minimized, enabling low power and high throughput operation. A critical technical issue is reducing hardware resources because all neurons need to be implemented on an FPGA, where hardware resources are limited. Two core technologies have been developed to minimize the required hardware resources: (1) A neural network with a small number of neurons in which weight values of all synapses are fixed to a common value, and (2) a small neuron cell circuit consisting of an adder and look-up table containing an activation function. By fixing all weight values to a certain common value, processing can be simplified from multiply-accumulate operations to just additions, and the hardware resources required for each neuron are minimized. An experiment with the MNIST dataset using a 28-nm FPGA confirmed power consumption of 0.16 W and latency per inference of 100 ns (16nJ/classification). With the same recognition accuracy, the power efficiency is 45.6 times higher than that of the conventional state-of-the-art binarized DNN accelerator with a digital ASIC.

Chirp spread spectrum (CSS) is the modulation technique currently employed by Long-Range (LoRa), which is one of the most prominent Internet of things wireless communications standards. The LoRa physical layer (PHY) employs CSS on top of a variant of frequency shift keying, and non-coherent detection is employed at the receiver. While it offers a good trade-off among coverage, data rate and device simplicity, its maximum achievable data rate is still a limiting factor for some applications. Moreover, the current LoRa standard does not fully exploit the CSS generic case, i.e., when data to be transmitted is encoded in different waveform parameters. Therefore, the goal of this paper is to investigate the performance of CSS while exploring different parameter settings aiming to increase the maximum achievable throughput, and hence increase spectral efficiency. Moreover, coherent and non-coherent reception algorithm design is presented under the framework of maximum likelihood estimation. For the practical receiver design, the formulation of a channel estimation technique is also presented. The performance evaluation of the different variants of CSS is carried out by inspection of the symbol error ratio as a function of the signal-to-noise ratio together with the maximum achievable throughput each scheme can achieve., Summited to the IEEE Transactions on Green Communications and Networking. arXiv admin note: text overlap with arXiv:2009.10421

In semiconductor foundries, wafer map defect analysis is crucial to prevent yield excursion. However, traditional manual inspection can hardly meet the high throughput demand. Deep learning based automatic defect detection shows promising efforts to achieve high accuracy and efficiency, yet the current approaches’ performance is limited by the imbalanced dataset and lack of interpretability. In this paper, we propose a Variational Autoencoder Enhanced Deep Learning Model (VAEDLM) for wafer defect imbalanced classification. It is light-weighted and effective in wafer defect pattern recognition on imbalanced dataset. It used variational autoencoder and decoder to generate similar wafer defect maps and a refined deep convolutional neural network for feature learning. We demonstrate the method using an authentic wafer map dataset, WM-811K. The performance is not only significantly improved after data augmentation, but it also beats the state-of-the art methods, reaching 99.19% accuracy, 99.10% recall, 99.23% precision, 99.96% AUC and 99.16% for F1-score. It clearly demonstrates the method’s efficacy to deal with the imbalanced defect pattern. Our study using saliency map and t-SNE further leads to enhanced interpretability.

The exploration of custom deep neural network (DNN) accelerators for highly energy constrained edge devices with on-device intelligence is gaining traction in the research community. Despite the superior throughput and performance of custom accelerators as compared to CPUs or GPUs, the energy efficiency and versatility of state-of-the-art DNN accelerators is constrained due to a) the storage and movement of a large volume of data and b) the limited scope of monolithic architectures, where the entire accelerator executes only a single model at any given time. In this paper, a multi-voltage domain heterogeneous DNN accelerator is proposed that executes multiple models simultaneously with different power-performance operating points. The proposed architecture concurrently implements near-memory computing and leakage reuse, where the leakage current of idle memory banks within each processing element is utilized to deliver current to the adjacently placed multiply-and-accumulate (MAC) units. The proposed architecture and circuit techniques are evaluated with SPICE simulation in a 65 nm CMOS technology. The simulation results indicate that the proposed heterogeneous architecture with leakage reuse improves the energy efficiency to 3.27 tera-operations per second per watt (TOPS/W) as compared to a conventional monolithic and single voltage domain architecture that exhibits an energy efficiency of 0.0458 TOPS/W. In addition, the proposed accelerator that applies the leakage reuse technique to only half of the memory elements storing the weights reduces the power consumption of the sub-arrays of processing elements by 100 mW as compared to an accelerator that does not apply leakage reuse.

The Purdue Make It system is a unique automated platform capable of small-scale in situ synthesis, screening small-molecule reactions, and performing direct label-free bioassays. The platform is based on desorption electrospray ionization (DESI), an ambient ionization method that allows for minimal sample workup and is capable of accelerating reactions in secondary droplets, thus conferring unique advantages compared with other high-throughput screening technologies. By combining DESI with liquid handling robotics, the system achieves throughputs of more than 1 sample/s, handling up to 6144 samples in a single run. As little as 100 fmol/spot of analyte is required to perform both initial analysis by mass spectrometry (MS) and further MS

Here we consider how high-content flow cytometric methodology at appropriate scale and throughput rapidly provided meaningful biological data in our recent studies of COVID-19, which we discuss in the context of other similar investigations. In our work, high-throughput flow cytometry was instrumental to identify a consensus immune signature in COVID-19 patients, and to investigate the impact of SARS-CoV-2 exposure on patients with either solid or hematological cancers. We provide here some examples of our 'holistic' approach, in which flow cytometry data generated by lymphocyte and myelomonocyte panels were integrated with other analytical metrics, including SARS-CoV-2-specific serum antibody titers, plasma cytokine/chemokine levels, and in-depth clinical annotation. We report how selective differences between T cell subsets were revealed by a newly described flow cytometric TDS assay to distinguish actively cycling T cells in the peripheral blood. By such approaches, our and others' high-content flow cytometry studies collectively identified overt abnormalities and subtle but critical changes that discriminate the immuno-signature of COVID-19 patients from those of healthy donors and patients with non-COVID respiratory infections. Thereby, these studies offered several meaningful biomarkers of COVID-19 severity that have the potential to improve the management of patients and of hospital resources. In sum, flow cytometry provides an important means for rapidly obtaining data that can guide clinical decision-making without requiring highly expensive, sophisticated equipment, and/or "-omics" capabilities. We consider how this approach might be further developed.

High-throughput experimentation (HTE) has become integral to the pharmaceutical industry with most major pharmaceutical companies investing in automation and high-throughput screening technologies....

As the trend of technology shrinking continues a vast amount of processors are being incorporated in a limited space. Due to this almost half of the chip area in Multi-Processor Systems-on-Chips (MPSoCs) is under interconnections, which pose a big problem for communication. Network-on-Chips (NoCs) evolved as a significant scalable solution for removing wiring congestion and communication problem in MPSoCs. NoCs provide the advantage of customized architecture, increased scalability and bandwidth. NoC is a structured framework where communication is the prime concern. In this review paper we present an overview of research and design approaches in the communication centric areas of NoCs. Here we have tried to discuss and iterate most of the available work done for communication in 2D NoCs. This paper gives the insight of different attributes and performance parameters of NoCs. Further it gives a detailed description of how topology, flow control and routing mechanisms can affect the qualitative aspects (performance) of NoCs. It then explains how various attributes of routing can help in increasing the efficacy of NoCs. Subsequently a brief review of different simulators used for NoCs is given. All of this is provided based on the survey of academic, theoretical and experimental approaches presented in the past. Finally some suggestions for future work are also given.

Multipliers are the most demanding component of any filter. They not only dominate most of the chip area but also contribute to most of the computational delay. An efficient realization of filter thus requires optimization of the multipliers. In this paper, a high performance block reconfigurable finite impulse response filter structure is presented. Block-based realization improves the overall throughput of the structure. A novel partial-product-based structure is proposed for Multiply and Accumulation operation, instead of traditional multipliers-based structure. Pipelining and parallelism in the structure improves the throughput of the design. The reuse of the partial products reduces the number of adders and increases the speed, thereby reducing the area-delay product (ADP) and energy-per output (EPO), in comparison with the earlier reported structures. The comparative analysis is done with the help of ASIC synthesis results and the results show that the proposed architecture for filter order 16 and block input 8requires 28.91% less ADP and 25.72% less EPO than the earlier reported architecture.

High-throughput microscopic imaging is highly desirable in biomedical applications. Advances in computational microscopy have achieved high space-bandwidth products and even permitted gigapixel ima...

The main objective of this paper is to design and implement High throughput, area efficient AES encryption algorithm on FPGA for security purposes. The high speed and area efficiency is achieved by designing an area efficient and high throughput structural S-Box architecture for AES encryption process. A combinational logic circuit based Rijndael Low area high speed S-Box is designed. The results compared with conventional S-Box. The speed and propagation delay of the S-Box are calculated for the designed S-Box. The proposed S-Box is used in AES encryption process. To further increase the speed of the encryption process efficient structure of Mix column is also proposed. This Mix column structure is used to achieve high throughput. The proposed S-Box and Mix Column are used in AES encryption. This proposed AES structure is implemented in FPGA Virtex 5.The results are compared with the conventional implementation.

In this article, a cybertwin-assisted nonorthogonal random access (RA) system is presented, where the cybertwins of the physical devices at the access point (AP) collect the devices’ information and decide the transmission parameters on behalf of the devices to achieve the maximum system performance. Specifically, the system performance of a $p$ -persistent slotted CSMA system with nonorthogonal multiple access (NOMA) is analyzed, in which wireless devices transmit data to the ensure the received signal strength at the AP side is either high power or low power with certain probabilities. We first develop an analytical framework to quantify the successful transmission probability and the sum data rate as a function of the above probabilities. Accordingly, the feasible region of the number of high-power and low-power devices to ensure successful transmission is derived. With the analysis, nonconvex optimization problems are then formulated to maximize successful transmission probability and the sum data rate, respectively. To tackle the nonconvexity, an effective and fast-convergent iterative algorithm is designed to obtain the optimal transmission probabilities for the devices. Extensive simulations are conducted to validate our analytical results and demonstrate the benefits of NOMA in RA networks.

This paper demonstrates how an analytical and experimental method can be used to rapidly define the additive manufacturing settings for a new alloy where the process parameters were previously unknown. A nickel-based superalloy, Haynes 282, was chosen for the analysis. An experimental matrix of focused processing parameters was predicted with a dimensionless number and 100 samples were printed using the Laser Powder Bed Fusion technique. High-throughput measurements validated the predicted process conditions needed to achieve desired density and hardness. The whole process was completed in 16 hours. The new technique was confirmed with analytical processing maps adopted by the metal additive manufacturing community. With the predicted set of process parameters, a low-throughput analyses of conventional microstructural characterizations and tensile testing were used to test the predictions. The resultant as-fabricated microstructures have refined length scales of both microsegregation and secondary phase distributions. The mechanical properties were comparable within the predicted processing window and exhibited high strength and high ductility.

The two prime dynamics that are steering the future wireless communications are energy efficiency and efficient spectral usage. Energy harvesting (EH) when integrated with cognitive radio (CR) technology guarantees to address the challenges of limited availability of energy and spectrum. In this paper, we propose an estimation based cyclostationary spectrum sensing technique in an energy harvesting cooperative cognitive radio network (EH-CRN). The analytical model for the assessment of the performance is established under various fusion rules with varying numbers of nodes in a centralized cooperative CRN. The performance is investigated with respect to the harvested energy and overall throughput of the network. We model the analytical framework for the detection performance, energy harvesting, and throughput in an EH-CRN scenario. The implication of the various network parameters viz., detection frames, number of CR users operating in cooperation, collision probability, prediction error upon the throughput of the network is studied. A comprehensive comparative analysis is made between the performance of an estimation based cyclostationary detection (ECSD) and estimated noise power based energy detection strategy (ENP ED). The results indicate that the proposed estimation based cyclostationary approach provides a better performance regardless of the low SNR and is immune to noise uncertainty as compared to other techniques.

INTRODUCTION We aimed to evaluate the performance of the fully automated multiparameter CN-6000 hemostasis analyzer. METHODS Performance evaluation of the CN-6000 analyzer was conducted for 10 tests including prothrombin time (PT), activated partial prothrombin time (aPTT), fibrinogen level, anti-Xa activity, and antithrombin activity using a unique portfolio of liquid ready-to-use reagents. Precision, sample and reagent carryovers, throughput, and sample turnaround time (STAT) function were prospectively assessed. Results from 343 samples (normal subjects, critically ill patients, patients receiving anticoagulants, subjects with high or low fibrinogen levels, and patients with decreased levels of factor II, V, VII, and X) were compared to those obtained on the STA-R Max 2® analyzer using dedicated reagents. RESULTS Total precision (coefficient of variation) was below 7% for all parameters in both normal and pathological ranges. For all analyzed parameters, results obtained on the CN-6000 were strongly correlated with those obtained on the STA-R Max 2®analyzer. Agreement between both instruments was excellent for all assays. The CN-6000 demonstrated a 30% higher throughput compared to the STA-R Max 2® (258 vs 185 tests per hour for a panel of tests including PT, aPTT, fibrinogen, factor V, anti-Xa, and D-Dimer). STAT turnaround time for critical care samples testing was

Increasingly accurate mathematical models have been developed to relate solute and hydrogel properties to solute diffusion coefficients in hydrogels, primarily by comparing solute sizes and hydrogel mesh sizes. Here, we use a standardized, high-throughput method for fluorescence recovery after photobleaching (FRAP) experiments and analysis to characterize the diffusion coefficients of fluorescein, three sizes of FITC-dextran, and three sizes of FITC-conjugated poly(ethylene glycol) (PEG) through 18 structurally varied poly(vinyl alcohol) (PVA) hydrogel formulations. Increasing the hydrogel mesh radii increased the diffusivities of all the tested solutes within the hydrogels. While the diffusivity of FITC-dextrans in hydrogels decreased with increasing solute size, the diffusivity of FITC-PEGs increased with increasing solute size, suggesting that a generalized hydrodynamic radius-based model is not universally applicable for solute diffusion in hydrogels. The high-throughput characterization method for solute diffusion in hydrogels described here facilitates precise hydrogel design for biomedical applications.

The process optimization for the synthesis of an RSV antiviral agent is described. Key to the identification of these optimal conditions was the use of high-throughput experimentation to greatly re...

The rapid evolution of error-resilient programs intertwined with their quest for high throughput has motivated the use of Single Instruction, Multiple Data (SIMD) components in Field-Programmable Gate Arrays (FPGAs). Particularly, to exploit the error-resiliency of such applications, Cross-layer approximation paradigm has recently gained traction, the ultimate goal of which is to efficiently exploit approximation potentials across layers of abstraction. From circuit- to application-level, valuable studies have proposed various approximation techniques, albeit linked to four drawbacks: First, most of approximate multipliers and dividers operate only in SISD mode. Second, imprecise units are often substituted, merely in a single kernel of a multi-kernel application, with an end-to-end analysis in Quality of Results (QoR) and not in the gained performance. Third, state-of-the-art (SoA) strategies neglect the fact that each kernel contributes differently to the end-to-end QoR and performance metrics. Therefore, they lack in adopting a generic methodology for adjusting the approximation knobs to maximize performance gains for a user-defined quality constraint. Finally, multi-level techniques lack in being efficiently supported, from application-, to architecture-, to circuit-level, in a cohesive cross-layer hierarchy. In this article, we propose Plasticine , a cross-layer methodology for multi-kernel applications, which addresses the aforementioned challenges by efficiently utilizing the synergistic effects of a chain of techniques across layers of abstraction. To this end, we propose an application sensitivity analysis and a heuristic that tailor the precision at constituent kernels of the application by finding the most tolerable degree of approximations for each of consecutive kernels, while also satisfying the ultimate user-defined QoR. The chain of approximations is also effectively enabled in a cross-layer hierarchy, from application- to architecture- to circuit-level, through the plasticity of SIMD multiplier-dividers, each supporting dynamic precision variability along with hybrid functionality. The end-to-end evaluations of Plasticine on three multi-kernel applications employed in bio-signal processing, image processing, and moving object tracking for Unmanned Air Vehicles (UAV) demonstrate 41%–64%, 39%–62%, and 70%–86% improvements in area, latency, and Area-Delay-Product (ADP), respectively, over 32-bit fixed precision, with negligible loss in QoR. To springboard future research in reconfigurable and approximate computing communities, our implementations will be available and open-sourced at https://cfaed.tu-dresden.de/pd-downloads.

Ever increasing performance demand and shrinking in the transistor size together result in complex and dense packing in large chips. That motivates designers to opt for many small specialized hardware modules in a chip to extract maximum performance benefits with relatively lower complexity and cost. These altogether opens up new directions for heterogeneous modular System-on-Chip (SoC) research, where a large system is built by assembling small independently designed chiplets (small chips). We focus on the communication aspect of such SoCs, especially the newly observed deadlock among chiplets. Even though deadlock is a classic problem in networks and many solutions are available, the modular SoC design demands customized solutions that preserves the design flexibility for chiplet designers. We propose Remote Control (RC) , a simple routing oblivious deadlock avoidance scheme based on selective injection-control mechanism. Along with guarantee on deadlock freedom, RC aims to provide a methodology to make each independently designed chiplet seamlessly integrate in any modular SoCs. We achieve up to 56.34% throughput and 15.49% zero load latency improvements on synthetic traffic and up to 20% speedup on real workloads taken from vast range of benchmark suites, over the state-of-the-art turn restriction based technique applied in the modular SoC domain.

Recent information-theoretic studies have resulted in several interference management (IM) techniques that promise significant capacity improvements over interference avoidance techniques. However, in practice, the stable throughput region is a more relevant metric compared to the capacity region. In this work, we focus on the stable throughput region of a two-pair intermittent interference network with distributed transmitters and propose a queue-based transmission protocol in different regimes to handle the data between queues. In this context, we translate physical-layer IM protocols to accommodate stochastic message arrivals. To evaluate our proposed techniques, we compare the stable throughput region to the capacity region and show, through simulations, that the stable throughput region matches the capacity region when the latter is known. We show that in order to achieve the optimal stable throughput region, new ingredients are needed when compared to prior results. We quantify the trade-off between the encoding/decoding complexity of the proposed scheme (in terms of number of required algebraic operations), and the achievable rates. Finally, we study the lifetime of messages (i.e. the duration from arrival to successful delivery) vis-a-vis the total communication time, and we observe that the average lifetime scales as the square root of the total communication time., Submitted to IEEE Transactions on Communications

This brief proposes a method of generating custom-shaped attractors, which depends on a planarly rotating V-shape multi-scroll chaotic system with offset boosting and amplitude control, and its FPGA verification. The proposed planarly rotating, translational (offset boostable), and scalable (amplitude controllable) system exhibits a wide basin of attraction and can cover the whole space. Consequently, non-autonomous parameters enable generating attractors of custom-shapes, e.g., letters of the English alphabet as a demonstrating example. Furthermore, non-autonomous parameters are employed to generate attractors with the shape of complete words and sentences. This takes place by generating letter shapes successively and controlling the position and size of each letter. The chaotic behavior is quantified and indicated using spectral entropy. Experimental verification on FPGA shows good hardware resources utilization and throughput.

In this article, a Co-existing Preamble and Data (CoPD) random access approach for machine-type communications (MTC) is proposed and studied in massive multiple input multiple output (MIMO) systems. Unlike conventional grant-free random access in which preambles are time-multiplexed with data, the proposed approach enables CoPD transmissions by different groups of devices, which leverages favourable propagation of massive MIMO and successive interference cancellation (SIC) technique. To fully understand the performance behavior of the proposed approach, the error characteristics of channel estimation (CE) due to SIC error propagation are investigated. To avoid the CE error variance growing arbitrarily with time that leads to data transmission failure, key conditions, with respect to preamble length $L$ , traffic intensity $\lambda $ , and average number of data packets per active device $\bar b$ , are derived. Under the conditions, we demonstrate that the throughput of the proposed CoPD approach cannot be arbitrarily high by increasing $\bar b$ and $\lambda $ even though the antenna array size, denoted by $M$ , grows arbitrarily in massive MIMO. Accordingly, its maximum throughput and success probability are theoretically obtained. Simulation results verify our analysis results and confirm that the maximum throughput of the proposed CoPD approach can be at least 4 times than that of the conventional one. Furthermore, its success probability approaches 1 when $M \to \infty $ as long as the derived conditions are met.

This work studies an unmanned aerial vehicle (UAV)-assisted wireless communication system where UAV acts as an aerial base station (BS) and serves multiple ground users simultaneously using rate-splitting multiple access (RSMA). We propose a new architecture called RSMA-UAV that leverages the interplay between rate-splitting (RS) and UAV and shows the effect of RSMA on system performance. Further, we derive closed-form expressions of outage probability and corresponding throughput at each user considering independent and non-identical Nakagami- ${m}$ small-scale fading. In addition to this, we also highlight the importance of the judicious selection of the power allocation coefficient in order to enhance the overall throughput performance of the system. Moreover, we show that hovering the UAV near certain coordinates can maximize the sum throughput of the system. Hence, we formulate an optimization problem to find the UAV coordinates. Finally, the accuracy of the derived analytical expressions is verified using the Monte-Carlo simulations.

This article presents a dynamic model and a current-mode control for a dc–dc modular multilevel converter with the ultimate aim of expanding the converter to a three-leg configuration to reduce the filtering requirements of the dc ports. A complete model of the converter including a systematic approach for the control of the power throughput is developed. It is then shown that the expansion from a single-leg to three-leg configuration requires no additional modeling, and that the three-leg converter significantly alleviates the filtering requirements on both the high-voltage and low-voltage sides. The proposed model and control technique are verified using simulation results based on the MATLAB / Simulink software environment for both the single and three-leg configuration. Further verification is carried out through a single-leg 1-kW experimental prototype.

The dynamic pricing problem of a freeway corridor with high-occupancy toll (HOT) lanes was formulated and solved based on a point queue abstraction of the traffic system [1] . However, existing pricing strategies cannot guarantee that the closed-loop system converges to the optimal state, in which the HOT lanes’ capacity is fully utilized but there is no queue on the HOT lanes, and a well-behaved estimation and control method is quite challenging and still elusive. This paper attempts to fill the gap by making three fundamental contributions: (i) to present a simpler formulation of the point queue model based on the new concept of residual capacity, (ii) to propose a simple feedback control theoretic approach to estimate the average value of time and calculate the dynamic price, and (iii) to analytically and numerically prove that the closed-loop system is stable and guaranteed to converge to the optimal state, in either Gaussian or exponential manners.