Efficient Parallel Decoding Architecture for Cluster Erasure Correcting 2-D LDPC Codes for 2-D Data Storage

Native 2-D low-density parity-check (LDPC) codes provide 2-D burst erasure correction capability and have promising applications in two-dimensional magnetic recording (TDMR) technology. Though carefully constructed rastered 1-D LDPC codes can provide 2-D burst erasure correction, they are not as efficient as 2-D native codes constructed for handling the 2-D span of burst erasures. Our contributions are twofold. First, we propose a new 2-D LDPC code with girth greater than 4 by generating a parity-check tensor through stacking permutation tensors of size $p\times p\times p$ along with the $i,j,k$ -axes. The permutations are achieved through circular shifts on an identity tensor along different coordinate axes in such a way that it provides a burst erasure correction capability of at least $p\times p$ . Second, we propose a fast, efficient, and scalable hardware architecture for a parallel 2-D LDPC decoder based on the proposed code construction for data storage applications. Through efficient indexing of the received messages in an RAM, we propose novel routing mechanisms for messages between the check nodes and variable nodes through a set of two barrel shifters, producing shifts along two axes. Through simulations, we show that the performance of the proposed 2-D LDPC codes matches a 1-D QC-LDPC code, with a sharp waterfall drop of three to four orders of magnitude over ~0.3 dB, for random errors over code sizes of ~32 kbits or equivalently ~ $180\times 180 2$ -D arrays. Furthermore, we prove that the proposed native 2-D LDPC codes outperform their 1-D counterparts in terms of 2-D cluster erasure correction ability. For $p=16$ and code arrays of size $48\times 48$ , we implemented the proposed design architecture on a Kintex-7 KC-705 field-programmable gate array (FPGA) kit, achieving a significantly high worst case throughput of 12.52 Gb/s at a clock frequency of 163 MHz.