Search

As2S3 strips were fabricated on thermal oxide using a lift-off procedure. Buried structures are formed by covering the strips with SiO2, and initial optical testing confirms waveguiding.

Silicon nanowires (SiNWs) have been grown on Si(100) substrates with and without a thermal oxide layer by rf magnetron sputtering of Si in Ar/H2. In the experiments, thin Au layers were employed as catalysts, resulting in a significant and substantial growth of randomly oriented, polycrystalline SiNWs, typically 20 µm long and 350 nm in diameter after 60 min of growth on both Si and SiO2 substrates at 700 °C. These indicate the possibility of providing an alternative method of SiNW growth that does not require toxic feed gases and high-temperature tube furnaces, and hence is suitable for growth on large-diameter substrates in industry.

The x-ray interference technique has been applied to evaluate the structural changes of high temperature grown chemical vapor deposited (CVD) SiO2 film under several post annealing conditions. In annealing above 800 °C in O2 ambient, a thermal oxide growth has been found at the CVD SiO2/Si interface, and its precise thicknesses have been determined. The estimated diffusion coefficient of the oxidant in CVD film was about three times larger compared to that of thermal oxide. A threshold voltage shift in the oxide was found to strongly correlate to the thickness of the thermal oxide rather than to thermal modifications of the CVD SiO2 itself.

Deep surface states are discovered on the interface between 6H-SiC and its native thermal oxide by analyzing the C-V characteristics of metal-oxide-semiconductor structures measured at a high temperature (600 K). The maximum of the density of states distributed according to energy (Dtm=2×1012 cm−2· eV−1) is at an energy about 1.2 eV below the bottom of the conduction band of SiC. It is postulated that the states discovered are similar in nature to the Pb centers observed in the SiO2/Si system.

The effects of N2 annealing on the physical properties of room-temperature-deposited ion plating (IP) oxide have been characterized. As-deposited IP oxide exhibits higher refractive index and dielectric constant values than high-temperature-annealed IP oxide. Strained bonds existing in as-deposited oxide can be relaxed by N2 annealing depending on the annealing temperature. After annealing at 800 °C, the physical characteristics of IP oxide are comparable to those of thermal oxide.

Quality of low-pressure chemical-vapor-deposited (LPCVD) oxide and N2O-nitrided LPCVD (LN2ON) oxide is investigated under high-field stress conditions as compared to thermal oxide. It is found that LPCVD oxide has lower midgap interface-state density Dit-m and smaller stress-induced Dit-m increase than thermal oxide, but exhibits enhanced electron trapping rate and degraded charge-to-breakdown characteristics, which, however, are significantly suppressed in LN2ON oxide, suggesting effective elimination of hydrogen-related species. Moreover, LN2ON oxide shows further improved Si/SiO2 interface due to interfacial nitrogen incorporation.

Femtosecond laser ablation of silicon (100) with thermal oxide thin films was studied in order to further understand the ablative properties of thin films and to evaluate their influence on the ablation of the substrate.

The effect of gamma-irradiation on the electrical characteristics of MOSFETs fabricated in DeleCut SOI wafers was defined. Properties of gate-oxide and BOX (buildup of radiation-induced charge in the oxide, interface state density and the initial concentration of traps in the oxide) were determined for DeleCut SOI MOSFETs and compared with that for thermal oxide on bulk silicon, Unibond and SIMOX wafers.

Dodecapeptides with affinity for thermally grown silicon dioxide were isolated by phage display. Selectants had high histidine content, though distributions of histidine are distinct from reported silica particle-precipitating peptides. Our peptides will have utility as nanoscale affinity domains when inserted into proteins intended for deposition on thermal oxide surfaces/interfaces in micro/nanodevices.

We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

Memory effect in a metal-insulator-silicon (MIS) structure with the insulator layer consisting of a sputtered capping SiO2 / Ge nanocrystals embedded in SiO2/ rapid thermal oxide structure has been observed. For the devices with a co-sputtered SiO2+Ge middle layer, larger nanocrystals were formed devices with a higher Ge concentration. It was noted that for such devices, the RTO and the capping oxide layers were able to confine the nanocrystals within the middle layer to some extent. However, in devices with pure sputtered Ge middle layer, the RTO and capping oxide layers were not as effective in confining the Ge nanocrystals. In addition, we have consistently observed memory effect from devices annealed in Ar and the absence of memory effect from devices annealed in forming gas. However, Ge nanocrystals were found in devices annealed in both ambient. This implies that having nanocrystals does not necessarily imply the presence of charge storage or memory effect.

During studies of the alternating cyclic, A.C., technique for the selective epitaxial growth of silicon, lateral epitaxial overgrowth (ELO) structures were observed following non-A.C. reference depositions in a low pressure hot wall system. Experiments were conducted at 2.5 Torr, 950°C, H 2 /SiCl 4 = 50, Ar/H 2 = 9, with H 2 = 2 slpm, SiCl 4 = 0.04 slpm, and Ar = 18 slpm. Patterned 0.22 to 0.35 μm thermal oxide covered silicon substrates with the oxide coverage ranging from 10 to 70% were employed. It was found that if the growth conditions and the oxide mask and exposed silicon opening sizes are properly chosen, void-free ELO structures are obtainable.

The effect of electrostatic bonding on the resistance and its temperature coefficient of the polysilicon highly doped piezoresistors is considered. The resistors are on the surface of anisotropically etched silicon diaphragms of different thickness. It is shown that changes of the resistance and temperature coefficient of the resistance cannot be accounted for solely by the mechanical stresses/strains at the silicon-glass interface. The residual thermo-mechanical stresses at the silicon-silicon thermal oxide interface are, probably, an issue. The effects of bonding on the R and TCR decreases as the thickness of diaphragm is increased.

In this paper, a new RF LDMOS is demonstrated with a cost effective process technology. By combining a step LDD and an inherent thermal oxide spacer, the parasitic feedback capacitance C/sub rss/ is reduced by 40%, achieving a 35% higher output power. Furthermore, the hot-electron resistance is improved by 70%, allowing more power to be obtained with a higher reliability.

Many IC fabs have expressed a great deal of interest in CMP pad life improvement with the expectation that improved pad performance will reduce process variability and improve CMP cost-of-consumables (CoC). Critical parameters that impact grooved-pad life and that can reduce pad life variability have been identified through designed experiments performed on a multiple head/platen CMP tool. The most important parameters effecting pad life are groove quality and groove size. New technologies have been developed to control these critical parameters in conjunction with extensive process optimization. Lathing technology (in tools and processes) plays a critical role in achieving high groove quality and desirable groove size. In many extended wafer runs and several accelerated pad wear runs, pad life was more than doubled by optimizing these critical parameters on polyurethane-based grooved-pads. Low defect counts of 2750 Ang./min. were achieved for thermal oxide CMP in the extended runs. The new pads double pad life when used with optimized processes, and achieve planarity comparable to conventional pads. Significant pad life improvement was attributed mainly to the implementation of larger and more consistent grooving, and optimized pad conditioning and polishing processes for the CMP tool. In general, the pad cost contributes approximately one third of the total CMP CoC. In this case study, average CMP pad life was found to be 250 wafers/pad with a variance of 100 to 400 wafers/pad. Pad CoC significantly increases for pad lives

Post-CMP cleaning of polished thermal oxide wafers is conducted using megasonic and brush cleaning techniques. The wafers were polished using Rodel silica based slurry. The results achieved by the two different cleaning methods are presented and compared. They show that although the two techniques produce comparable cleaning performance, non-contact cleaning using SCl produces lower defect counts on the cleaned wafers.

We have investigated visible photoluminescence excited by Ar ion laser (488 nm, 2.54 eV) at room temperature from Si+‐implanted thermal oxide films grown on crystalline Si wafer, as‐implanted and after subsequent annealing in vacuum. We found two types of visible luminescence bands similar to those of silica glasses; one band is observed in as‐implanted specimens and disappears after heating to about 600 °C, and the other band is observed only after heating the specimens to about 1100 °C. Though the shapes of these luminescence spectra are different from those having been observed in Si+‐implanted silica glass, the origins of these bands are the same as in silica glass. We discuss the similarities and the differences of luminescence bands in Si+‐implanted silica glasses and thermal oxide films grown on crystalline Si.

High temperature oxidation of the low dose SIMOX has been shown to increase the thickness of the buried oxide, and improve its electrical characteristics in terms of pinhole densities, leakage current and breakdown voltage. The high temperature oxidation is a relatively new technique applied to low dose SIMOX and detailed characteristics of this material have not yet been finally explored. In our work on low dose SIMOX with internal thermal oxidation (ITOX), we observed the sensitivity of the characteristics of this material to the process conditions such as energy and dose of implanted oxygen, and temperature and ambient of the high temperature oxidation. Although the growth of the internal thermal oxide at the BOX interfaces, simultaneously accompanied by the oxidation of silicon inclusions in the BOX, was observed under wide range of process conditions, the leakage characteristics of the resultant buried oxide exhibited stronger dependencies on the process conditions than expected from the structural analysis. In this paper we continue to examine the effects of the process conditions on the structural and electrical characteristics of low dose SIMOX with ITOX.

Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator of poly-Si TFT's. The ECR plasma thermal oxide grown on poly-Si film shows good electrical characteristics and renders a smooth interface with the poly-Si film. The fabricated poly-Si TFTs, even without plasma hydrogenation, show high performance characteristics. Both as-fabricated and plasma hydrogenated TFT's exhibit only a small threshold voltage shift (/spl Delta/V/sub th/ >

The authors report on lamp heated ZMR (zone melting recrystallization) of two silicon layers, stacked on top of each other and separated by an oxide layer in between. A 1.5- mu m thermal oxide was grown on

The mechanisms, chemistry, structure and interface properties of native and grown oxides on CuInSe/sub 2/ are presented. During thermal oxidation of this ternary semiconductor, the composition and the electrical properties are controlled, primarily by the temperature and duration of oxidation treatment. The oxygen reacts principally with In, leaving the Cu and Se to readjust at the interface to form a Cu/sub x/Se transition layer. The thermal oxide consists of an In/sub 2/O/sub 3/ matrix and having either inclusion of Cu or SeO/sub 2/ particles, depending on the precise formation conditions. The Cu/sub x/Se transition layer eventually acts as a barrier that prevents further oxidation of the underlying CuInSe/sub 2/.

A fast screening technique is used to study the ALD HfO2 growth behavior on different types of starting surfaces (H-passivated, chemical oxide, thermal oxide). The amount of Hf deposited at the early stages of the ALD process is measured by means of RBS. The HfO2 film quality on different starting surfaces is examined with ToFSIMS. The results suggest an island growth mechanism on a H-terminated starting surface: nucleation, development of separated nuclei and flattening. It is shown that ALD growth starts faster if –OH groups are present on the surface. A remote H2 plasma surface pre-treatment at room temperature is also studied. The influence of the plasma exposure time and number of water pulses prior to HfO2 deposition was examined. The H2 plasma surface pre-treatment can be considered as a promising candidate for sub 1 nm EOT performance.

Spin-on pre metal dielectric (PMD) materials are being developed for memory and logic devices at 0.10 um design rules and beyond. The stringent design rules require a PMD material with a low thermal budget, excellent gap fill capability, and etch resistance similar to that of a thermal oxide. Spin-on PMD is being developed to meet these requirements as current PMD technologies of HDP CVD and BPSG reflow are constrained by void formation or high thermal budget requirement. One common challenge that faces spin-on PMD is inhomogeneous densification, or “corner etch”. In this paper EELS-STEM, FTIR, SEM and HF wet etching were used to study the mechanism of this phenomenon. This information provides a possible route for the development of spin-on PMD resins.

Epitaxial growth of 3C-SiC on Si substrates has been studied for many years, however an important issue is how to reduce the high density of interfacial defects. Channel epitaxy is the growth of a film on small channeled windows and is related to selective growth. Channel epitaxy of 3C-SiC grown on the seed 3C-SiC previously deposited on patterned Si substrates was achieved via CVD using hexamethyldisilane (HMDS). The proper selection of mask materials was also key to achieve channel epitaxy. Thermal oxide, silicon nitride and thin SiC masks were tried. Thin SiC was an effective mask to achieve selective growth at 1350°C. Smooth surface morphology was observed on both the channel regions and the mask regions at the growth temperature of 1350°C. Scanning electron microscopy revealed coalescence of the laterally grown regions via channel epitaxial growth of 3C-SiC.

A study of the SC1 (NH 4 OH:H 2 O 2 :H 2 O) solution for use in both resist particulate removal and in selective wet etching of certain films is reported. The ratio of SC1 solution used for the following tests is 1:2:10. Etch rates for films such as tetraethylorthosilicate oxide, borophosphosilicate glass, nitride, doped polysilicon, and thermal oxide are investigated. Film composition, age of chemicals used, temperature, and composition of chemicals are factors which can influence etch rates of these films

The superior characteristics of floating-gate electron tunneling MOS (FETMOS) EEPROMs fabricated using a furnace N/sub 2/O oxynitridation process are described. These devices exhibited about eight times better endurance and good data retention characteristics while maintaining defect density comparable to that of the control thermal oxide devices. These devices also showed very good thickness uniformity across the wafer and wafer-to-wafer. >

We have used capacitance‐voltage and electron paramagnetic resonance to measure interface defects in ultrathin (30 A) SiO2 prepared by rapid‐thermal oxidation. We observe a very narrow interface state peak in the upper portion of the Si band gap, as well as both Pb0 and Pb1 defects in the as‐oxidized film. Forming‐gas annealing removes the interface state and most of the Pb centers. However, from the energy level and charge state of the interface state peak, we argue that it cannot be reliably ascribed to either Pb0 or Pb1.

The oxygen‐vacancy defect (E’) generated at the surface of buried SiO2 (BOX) layers of the separation by implantation of oxygen structure has been studied by K‐band electron spin resonance. Besides the usual Eγ’ signal, the Eδ’ center—a delocalized variant of the E’ center—has been identified in the BOX. No such signal, however, was observed in reoxidized (950 °C; 1.1 atm O2) BOX or conventional thermal oxide. These data lead to the proposal of an adapted model for the defect, based on the existence of small Si clusters (≳5 atoms) in the BOX serving as E’ defect precursors. This model implies that the buried oxide contains excess Si, exceedingly so near the BOX/substrate interface.

Via fill performance of AR7 (KrF anti-reflectant) and a prototype 193nm anti-reflectant were measured for 600 and 1000 nm deep vias in thermal oxide. Simple fitting functions were found which gave good agreement with experimental data (Rsq over 0.84). The most important factors were AR thickness, via duty ratio and via depth. The importance of these factors was different for the different anti-reflectants.

The effects of post-oxidation N/sub 2/O anneal on conventional thermal oxide are studied. The oxide thickness increase resulting from N/sub 2/O anneal is found to be self-limiting and insensitive to initial oxide thickness, which makes the thickness of the resulting oxide easy to control. The N/sub 2/O anneal leads to increased resistance against injection-induced interface-state generation and to reduced hole trapping. No further quality improvement is found when the N/sub 2/O-annealed oxide is subject to an additional reoxidation. This finding confirms that nitrogen incorporation in the absence of hydrogen is responsible for improving the quality of the conventional oxides. >

Via fill and intervia coverage of AR5 and AR7 anti-reflectants were measured for 608nm deep vias in thermal oxide. Fitting functions were found which gave god agreement with experimental data. The most important factors were AR thickness, via duty ratio and via width. The importance of these factors was different for via fill and intervia coverage, and for AR5 and AR7. AR7 was found to fill a range of vias to a depth of 25 percent to 50 percent, suitable for a partial planarization approach to dual damascene fabrication. Planarization was shown to be relatively insensitive to several coat process variations, but sensitive to solution surface tension.

Current SiC metal-oxide-semiconductor-field-effect-transistors (MOSFETs) have regions of the gate electrode that overlaps the source/drain contact implant. The source/drain region is electrically isolated from this gate electrode extension by the gate insulator. Typically, the gate insulator is established through a controlled thermal oxidation step. The performance of the electrical isolation between the gate electrode and the source/drain implant region is studied using MOS systems for the nitrogen and phosphorus implant species. The dielectric strength of thermal oxide grown over a phosphorus implanted region is about four times lower than a non-implanted region and about two times lower than the nitrogen implanted region for the same implant and anneal conditions.

Defects in thermal oxides were investigated by a photoluminescence technique. Thermal oxides with a thickness of 100 nm grown either by dry or wet oxidation were studied. A broad PL band at 2-4 eV was observed for both dry and wet oxides. Effects of annealing under vacuum or in atmospheres of Ar or N2 on the PL were also examined. The PL intensity was enhanced for the case of wet oxide by vacuum annealing at 700 °C. High-temperature anneal above 750 °C without O2 further generated PL centers for both dry and wet oxides. The formation mechanism of the PL centers will be discussed in terms of the decomposition of oxide at Si/SiO2 interface.

A comparative study of diluted HF etch rates was performed on thermally grown oxide (1120 °C; O2 pressure ≊1.1 atm) and buried oxide layers [formed by implanting n‐and p‐type (100)Si maintained at ≊600 °C with 150–200 keV O+ ions to a dose of ≊1.8×1018 cm−2, and subsequent annealing at 1250–1325 °C]. From accurate mechanical thickness measurements, a difference in etch rate between thermally grown and buried oxide is observed. This is direct evidence for a structural and/or stoichiometrical difference between both oxides. Additionally, plots of the etch rate as a function of oxide thickness reveal detailed information on the local structure of the oxide layers.

This report presents a nondestructive inspection assessment of eddy current and electrochemical analysis to separate inconel alloys from stainless steel alloys as well as an evaluation of cleaning techniques to remove a thermal oxide layer on aircraft exhaust components. The results of this assessment are presented in terms of how effective each technique classifies a known exhaust material. Results indicate that either inspection technique can separate inconel and stainless steel alloys. Based on the experiments conducted, the electrochemical spot test is the optimum for use by airframe and powerplant mechanics. A spot test procedure is proposed for incorporation into the Federal Aviation Administration Advisory Circular 65-9A Airframe & Powerplant Mechanic - General Handbook. 3 refs., 70 figs., 7 tabs.

We investigate nucleation densities in UHV-CVD of Si on ultrathin SiO2 layers (0.2-2 nm) which were prepared by three different oxidation methods: thermal, UV-ozone, and plasma oxidation. The experiments changing the Si2H6 pressure in UHV-CVD indicate that these oxide surfaces have preferred sites for nucleation. Among the three oxidation methods, the nucleation density, Ns, on the thermal oxide is the lowest, while the plasma oxide shows the highest Ns. These results suggest that strained bonds and ion-induced damages in the oxide layers assist nucleation. For UV-ozone and plasma oxides Ns is independent of orientation, reconstruction, and morphology of the initial Si surface.

In this paper, experimental data on the temperature-dependent transient photoconductivity obtained on bonded SOI structures are presented. It is shown that, during the bonding process at the interface of the sample, electrically active states appear. The values of activation energies and capture cross-sections of charge carriers at the interface are similar to those at the interface of silicon and thermal oxide.

Recent studies have shown that extremely dilute HCl mixtures can offer considerable cost savings and improved particle performance relative to traditional SC2 formulations. This work indicates, however, that extreme levels of dilution are not necessary to secure many of the benefits suggested for dilute HCI. Significant benefit can be attained by pursuing moderate concentration and temperature alterations. In this study, an intermediate dilution and temperature reduction are evaluated to assess potential production advantage. Comparison of a 1:1:20 formulation at 60 C is made to a more traditional 1:1:6 mixture at 85 C. The impact of the chemistry and temperature alteration on peroxide decomposition rate is shown to be dramatic. While initial pour-up ratios suggest that the dilute recipe could require 1/3 as much peroxide as the traditional chemistry, chemical savings are significantly more dramatic due to the ability of the solution to maintain concentration over time. An additional benefit associated with the alternative pour-up is a marked reduction in particle levels on silicon surfaces; particle levels on thermal oxide wafers have not shown the same trend. VPD-ICPMS measurements are used in this study to illustrate that the recipe change results in comparable metallic removal efficiency.

An improved method for quenching a Buffered Oxide Etch (BOE) process in a DI water overflow rinse tank is shown. Many different factors were investigated in several preliminary experiments. Most of these factors were thought to influence etch uniformity yet proved not to be significant. The transfer process from chemical to rinse was identified as contributing negatively to etch uniformity. A chemical carryover layer formed during the transfer process was identified as the most significant factor. The hydrodynamics of liquids are outlined to help explain how the carryover layer is formed and shaped. Several sensitivity analysis experiments show transfer speeds to significantly affect carryover layer thickness and uniformity. Slow transfer speeds are determined to produce consistent and improved uniformity. Results of a follow up experiment quantify the uniformity improvement.

Hydrogen and water vapor plasma downstream treatment with the downstream injection of NF3 removes native oxide from silicon surfaces. In contact hole cleaning, this dry processing is a promising alternative to HF wet treatment, which has a problem of expansion of hole diameter. We examined the etching characteristics of boron-phosphosilicate glass (B-PSG) films, as a typical oxide material for the side-walls of the contact holes and compared the etching depths of B-PSG and thermal oxide films. We found that the etching depths of B-PSG films fell to one third of those of thermal oxide films at lower treatment temperature. This result indicates that the expansion of contact hole diameters can be minimized.

We examine the electron mobility and hole mobility at the Si/buried oxide (BOX) interface at which the valley splitting of the electron system is strongly enhanced, and compare the values observed to those at a standard Si/thermal oxide (T-SiO2) interface in the same silicon-on-insulator device. In contrast to the electron mobility, which is lower at the Si/BOX interface, the hole mobility at the Si/BOX interface is found to be slightly higher than that at the Si/T-SiO2 interface.

Thermal oxide layers on Si which have been implanted with Si conduct electrical current and emit light. The electroluminescence effect (EL) has an efficiency which is comparable to the best values that have been reported for the porous Si based devices. Generally, the EL spectrum differs substantially from the photoexcited luminescence. It is linked with that excited by external high energy electrons in cathodoluminescence (CL) experiments. We suggest to consider the effect as internal CL. Based on studies of transport and EL characteristic we evaluate the possibilities of an electroluminescent device based on such layers.

The application of CoSi2 in ever shrinking Si CMOS source-drain technologies demands a better knowledge of the states of stress caused by the formation of cobalt-silicides in Si. In this study the variation in local mechanical stress in the silicon substrate near arrays of polycrystalline cobalt-silicide lines was investigated by micro-Raman spectroscopy. The lines were formed by annealing Co sputtered in windows in lithographically patterned, thermal oxide coated Si wafers. The CoSi2 lines varied in width from ˜0.25 to 5.0μ, in number from 2 to 7, and in thickness from ˜ 10 to 230nm. The spacing between lines was 1 and 3 times the line width.Trends in the Si stress between CoSi2 lines are described as a function of line width and line thickness. From the stress measured in the Si, information is obtained about the stress in the CoSi2 lines. In addition, the Si stress due to lines of primarily CoSi phase (monosilicide) is compared with the Si stress due to polycrystalline-CoSi2 (disilicide) lines.Cross section TEM and SEM micrographs of the CoSix line morphologies are used to aid the description of the resulting stress profiles. Some theoretical modeling of the stress in the Si due to the CoSix lines is presented for comparison with the micro-Raman spectroscopy results.

The outplating behaviour of Fe and Cu was investigated for diluted solutions of HCl and HNO3. The deposition of the metallic contaminants was found to be strongly dependent on the type of surface that is exposed to the contaminated solution. Cu deposits heavily on bare silicon surfaces, whereas only low levels of Fe deposition are observed. On the other hand, on thermal oxide surfaces, the levels of deposited Fe are consistently higher than the Cu ones. The acid used appears to have no major impact on the deposition process. The pH of the solutions has a major effect on the Cu deposition and a minor effect on the Fe case.

We investigated the density profile of thermally grown SiO2 thin films on a Si(100) using X-ray reflectivity. Samples were grown at 750 and 1000 °C with a slow ramp process and at 1000 and 1100 °C with a rapid thermal process. A SiO2 thin film was reconfirmed to have a two-layer structure: a dense transition layer of about 1 nm and an overlayer. The density profile was affected by the ramp rate and the growth temperature. The SR samples had some complicated features in the overlayer such as an inversion accompanying a density jump at 750 °C or a dense part near the transition layer at 1000 °C. The transition layer maintained a constant density from 750 to 1000 °C. The RTP samples showed a simple two-layer structure with a smaller density than the SR ones. The density was classified into four discrete groups according to its value.