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This paper intends to propose an authoring tool system that allows users to easily create augmented reality content with the application of marker based and gesture interactions. It is possible to generate a simplified form of marker based augmented reality content with the user interface by using Kinect that enables gesture interaction. We seek to provide methods for the user to actively interact with augmented reality content. The interaction method we put forth in this study is a gesture interaction approach capable of Transfer, Rotate, Enlarge, and Shrink an object by recognizing and tracking the user's bare hand. As for marker based interaction methods, there is one employing two markers and another using marker occlusion. We ascertain the positive results of this study from the user evaluation of an authoring tool system and marker based and gesture interactions.

Ray tracing naturally supports high-quality global illumination effects, but it is computationally costly. Traversal and intersection operations dominate the computation of ray tracing. To accelerate these two operations, we propose a hardware architecture integrating three novel approaches. First, we present an ordered depth-first layout and a traversal architecture using this layout to reduce the required memory bandwidth. Second, we propose a three-phase ray-triangle intersection architecture that takes advantage of early exit. Third, we propose a latency hiding architecture defined as the ray accumulation unit. Cycle-accurate simulation results indicate our architecture can achieve interactive distributed ray tracing.

We propose a node cache scheme for efficient ray tracing hardware. The scheme uses an aspect that traversing high-level nodes have more locality. In this method, a node cache is split into a high-level node cache and a low-level node cache. The data of the high-level nodes is retained during one frame. In addition, this scheme has a hybrid tree layout. That is, the high-level nodes are represented to the breath-first layout for a division of nodes, and the low-level nodes are represented to the depth-first layout for an effective use of locality. Simulation results show the reduction in cache miss ratio up to around three percent.

This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3 M rays per second over realistic 3 D scenes. The future implementation with ASIC is expected to achieve real-time performance.

Color-vision-based applications for mobile phones has become a subject of special interest lately. It would be interesting to investigate an unsupervised, adaptive, and fast algorithm that can classify color components into color clusters. We propose a hierarchical clustering approach using a single-linkage algorithm and a k-means clustering approach to color classification for color-based image code recognition in mobile computing environments. We also measured the performance of the proposed algorithms by color channel stretch, which is a simple color-correction method. Experimental results show that the single-linkage method is more robust than previous algorithms used in experiments with varying cameras and print materials. In particular the k-means-based method with color channel stretching has the highest performance and is the most robust under varying environment conditions such as illuminants, cameras, and print materials.

Color-image data is generally more complex than black and whilt version in terms of the number of variables in the channels and “color constancy” issue. Most of two-dimensional (2D) codes are dominant in a black and white domain such as QR code, PDF417, Data Matrix and Maxicode rather than in color domain, affected usually by such technical difficulities of handing color variables. Conventional 2D codes adopt Reed-Solomon (RS) algorithm for their error control codes mainly to recover from damages such as stains, scrathes and spots, while highlight and shadow issues in color codes are much more complex. In this paper we propose a new decoding approach by applying recoverable erasures by RS algorithm in color codes to resolve color recognition issue effectively. Using erasure concept ultimately for color constantcy, marking erasure strategy during color recognition processing steps is very crucial. Our algorithm ultimately mitigates color recognition load overall in decoding color codes. Consequently our new erasure decision algorithm prevents color recognition failures within erasure correction capability of RS algorithm, and it can be applied along with other color constancy algorithms easily to increase overall decoding performance just using RS erasure.

In recent years, extensive research has been carried out on vision-based automatic identification technology that recognizes image codes using a camera phone, and then provides various services. These image codes such as one-dimensional barcodes and two-dimensional codes consist of black and white patterns for easier and faster recognition by the reader. Therefore, the image codes have limitations in providing information for users, such as service type and service aim, because their patterns are sensitive to deformations. In this paper, we propose a color-based image code that is configurable and can present visual information on its service. Moreover, we describe an encoding/decoding technology and actual services of the image code.

Detection technology is a requirement for an Augmented Reality system. One of the problems with detection technology is the instability problem, which occurs when an obstacle occludes a tag while detecting the tag, and the augmented object suddenly disappears. We have proposed a corner detection algorithm to solve this instability problem. The key feature is that if the tag can recognize its position using its four corner cells despite the obstacle being present, then it can maintain its augmented object. We defined the corner case for all types of cases where the instability problem occurs in ARToolkit or ARTag. We have adapted our proposed algorithm to the corner case in ARToolkit, ARTag and ColorCode vision systems and have compared their false detection rates.

We describe a framework for designing and implementing autonomous navigation in automobiles. It integrates vehicle control, environment sensing, remote services, and navigation functions using mobile computing devices such as smartphones. We use wireless Web-service for data access and Axis2 as the SOAP engine for bounded delays in communication. A hierarchical data fusion strategy is proposed with flexible synchronization primitives for interaction among data objects. Supporting autonomous navigation using computers and sensors also takes advantage of throttle by wire instead of mechanical links, steering by wire, and brake by wire.

Accurate environment sensing has become crucial in various domains ranging from remote control, remote collaboration, navigation in autonomous vehicles and disaster prevention systems. The common characteristics for these applications are: diverse sensors operating at different rates resulting in the heterogeneity of data sources, constant processing time constraints, and real-time decision making processes based on the collected information. A reliable data fusion model must address each of these requirements and must allow the user to constantly monitor the flow of data in the framework. This paper proposes a hierarchical model for data fusion using real time objects and an application program interface (API).

Many new services have emerged to realize ubiquitous computing environments, owing to the increasing supply of mobile devices and more widespread Internet and wireless network facilities. We introduce the U-Campus (ubiquitous computing for campus) service. This study has been conducted through interdisciplinary research by four participating departments. The U-campus project is part of the UTOPIA project (Ubiquitous computing TOwn Project: Intelligent context Awareness), which covers town- and city-wide environments. Currently, a test bed for U-campus has been constructed to support various services suck as U-profile, U-messaging and U-campus tour guide services. Students, professors, school staffs, and campus visitors can easily access the various available campus services by using image-based sensors and mobile devices such as CDMA cellular phones or WiFi smart phones. The major purpose of this research is to provide a context-aware U-campus environment to users by utilizing sensors and mobile devices currently available in the public sector and the marketplace.

As a 3D scene becomes increasingly complex and the screen resolution increases, the design of effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture, which performs a depth test operation twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste caused by fetching unnecessary obscured texture data, by performing the depth test before texture mapping. The proposed architecture reduces the miss penalties of the pixel cache by using a pre-fetch scheme - that is, a frame memory access, due to a cache miss at the first depth test, is done simultaneously with texture mapping. The proposed pixel rasterization architecture achieves memory bandwidth effectiveness and reduces power consumption, producing high-performance gains.

In this paper, an effective memory-processor integrated architecture, called memory-based processor array for artificial neural networks (MPAA), is proposed. The MPAA can be easily integrated into any host system via memory interface. Specifically, the MPA system provides an efficient mechanism for its local memory accesses allowed by row and column bases, using hybrid row and column decoding, which is suitable for computation models of ANNs such as the accessing and alignment patterns given for matrix-by-vector operations. Mapping algorithms to implement the multilayer perceptron with backpropagation learning on the MPAA system are also provided. The proposed algorithms support both neuron and layer level parallelisms which allow the MPAA system to operate the learning phase as well as the recall phase in the pipelined fashion. Performance evaluation is provided by detailed comparison in terms of two metrics such as the cost and number of computation steps. The results show that the performance of the proposed architecture and algorithms is superior to those of the previous approaches, such as one-dimensional single-instruction multiple data (SIMD) arrays, two-dimensional SIMD arrays, systolic ring structures, and hypercube machines.

This paper proposes a new memory access control scheme called delayed precharge scheme, to improve the performance of on-chip DRAM's by increasing the DRAM page hit ratio for multiple block accesses. This architecture shows higher performance than the hierarchical multi-bank architecture as well as the conventional bank architecture by execution-driven simulation. The proposed scheme could reduce the cache refill time and CPI obtained by the conventional DRAM by 26.9% and 6.2% respectively in typical applications.

This paper demonstrates how the demultiplexor is used for making a new tree embedded in a MIN and how the Augmented Generalized Cube Network is designed using this tree. Evaluation of its performance and examination of its characteristics are also included. The demultiplexor was originally used for providing tolerance for destination link failures. The above shows that the AGCN gets better performance than other MINs. Not only does the AGCN have all of the Generalized Cube Network's features but it also offers multiple paths using a new embedded tree and intrastage links. Its self-adaptive routing in the last stage can alleviate tree saturation and contribute greatly to performance improvement.

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time /spl Delta/M table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a /spl Delta/M table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time /spl Delta/M table generation method is faster than other algorithms in /spl Delta/M table generation time and access time for 10,000 array elements.

A new lookahead instruction prefetching mechanism is proposed in this paper. Though significant performance improvement can be obtained by improving both the cache miss ratio and average access time for successfully prefetched blocks, most conventional prefetching mechanisms improve only one out of the two factors. To achieve balanced improvement of the two factors, a lookahead prefetching scheme that fetches multiple blocks for a prefetch request and adopts prefetch on miss mechanism is proposed. Performance evaluation is carried out through the trace-driven simulation and the proposed prefetch scheme reduces 32%/spl sim/56% of the memory access delay time of the cache system that does not perform any prefetching.

A memory based processor array (MPA) for matrix multiplications is designed as an effective array architecture. Also a mapping algorithm to implement matrix multiplication on the MPA system is proposed. One outstanding feature of the MPA system is that it can be easily integrated into any host system via memory interface. Specifically, the MPA system provides an efficient mechanism for its local memory accesses allowed by the row basis and the column basis using the hybrid row and column decoding, which is suitable for matrix multiplications. An important factor to improve performance in the processor array is to reduce the communication time among processing units and this can be achieved through efficient memory structure. The proposed architecture and its corresponding algorithm are turned out to be better than others by performance evaluation. And the MPA system also provides a new platform for computing a variety of linear algebra applications.

In this paper an effective memory-processor integrated architecture, called memory based processor array (MPA), for computer vision is proposed. The MPA can be easily attached into any host system via memory interface. In order to measure the impact of the memory interface structure an analytical model is derived. The performance improvement on the proposed model for the memory interface architecture of the MPA system can be 6%/spl sim/40% for vision tasks consisting of sequential and data parallel tasks. The asymptotic time complexities of the mapping algorithms are evaluated to verify the cost-effectiveness and the efficiency of the MPA system.

Scheduling a directed acyclic graph (DAG) which represents the precedence relations of the tasks of a parallel program in a distributed computing system (DCS) is known as an NP-complete problem except for some special cases. Many heuristic-based methods have been proposed under various models and assumptions. A DCS can be classified in two types according to the characteristics of the processors on a network: a distributed homogeneous system (DHOS) and a distributed heterogeneous system (DHES). The paper defines a general model for a DHOS and a DHES and presents a genetic algorithm (GA) to solve the task scheduling problem in the defined DCS. The performance of the proposed GA is compared with the list scheduling algorithm in a DHOS and with the one-level reach-out greedy algorithm (OLROG) in a DHES. The proposed GA has shown better performance in various environments than other scheduling methods.

In this paper an effective memory-processor integrated architecture, called memory based processor array for artificial neural networks (MPAA), is proposed. The MPAA can be easily integrated into any host system via memory interface. Specifically, the MPAA system provides an efficient mechanism for its local memory accesses allowed by the row basis and the column basis using the hybrid row and column decoding, which is suitable for the computation model of ANNs such as the accessing and alignment patterns given for matrix-by-vector operations. Mapping algorithms to implement the multilayer perceptron with backpropagation learning on the MPAA system are also provided. The proposed algorithms support both neuron and layer level parallelisms which allow the MPAA system to operate the learning phase as well as the recall phase in the pipelined fashion. Performance evaluation is provided by detailed comparison in terms of two metrics such as the cost and the number of computation steps.

An approach for designing high performance disk array systems using a dual head disk structure is presented. In general, both I/O bandwidth and reliability can be significantly improved by using disk array systems, i.e., RAID. However, the performance of RAID systems can be significantly degraded where small read/write accesses are frequently requested. Thus, the dual head disk structure is applied to improve the performance of RAID systems. The dual head disk model can reduce not only the maximum seek time but also the average seek time by dividing the disk surface into two separated regions, one for each head. To compare the performance of the dual head RAID (DH-RAID) system with the conventional RAID systems, simulations are performed with two types of RAID configurations and several workloads. Simulation results show higher performance can be obtained by DH-RAID systems as compared with the conventional RAID systems. The DH-RAID model can provide better performance in the application environment that has a relatively high seek time ratio.

Trace-driven simulation is widely used to evaluate the cache memory system. The accuracy of the trace-driven simulation depends on the accuracy and length of the trace data. To achieve an accurate and long trace, trace collection hardware is designed. The flying cache simulator is attached to the tracing system to simulate various cache systems during the execution of an application program. The tracing system designed, called the Reconfigurable Address Collector and Flying Cache Simulator (RACFCS), can generate accurate and long traces and simulate the cache system for a long execution time.

An approach for designing a hybrid parallel system that can perform adaptively for different types of parallelism is presented. An adaptive parallel system (APS) is proposed to attain this goal. The APS is constructed by integrating tightly two different types of parallel architectures, i.e., a multiprocessor system and a memory based processor array (MPA), into a single machine. The multiprocessor and the MPA can execute medium to coarse grain parallelism and fine grain data parallelism optimally. One important feature in the APS is that the programming interface is the same as the usual subroutine call mechanism to execute data parallel code on the MPA. Thus the existence of the MPA is transparent to the programmers. This research concerns the design of an underlying base architecture that can be optimally executed for a broad range of applications, from coarse grain to fine grain parallelism. Also the performance model is provided for fair comparison with other approaches. It turns out that the proposed APS can provide significant performance improvement and cost effectiveness for highly parallel applications having a mixed set of parallelisms.

The CalmRISC32 FPU (Floating-Point Unit) is a RISC coprocessor for embedded system applications. It supports IEEE-754 standard single precision floating-point addition, floating-point subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, load, store, etc. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order, if constraints such as data dependency, resource conflict, and exception prediction are resolved. Standard cell-base design techniques were used to reduce design time and expense. The first prototype operated at approximately 70 MHz with the worst-case delay in gate level simulation.

The cache memory system for CalmRISC32 embedded processor is described in this paper. A dual data cache system structure called a cooperative cache that takes advantage of design flexibilities of a dual cache structure is used as the cache memory system for CalmRISC32 to improve performance and reduce power consumption. The cooperative cache system is applied to both data cache and instruction cache. This paper describes the structure and operational model of the cache memory system for CalmRISC32. The implementation of the cache memory system for CalmRISC32 is also presented.

Recently, more advanced image quality and many techniques are needed in 3D computer graphics. Especially texture mapping support is the major issue in the design of high performance 3D graphics system. In this paper, a high-performance 3D graphics hardware is designed for texture mapping. The proposed system is composed of a single-chip rasterizer and frame buffer using a processor-memory integration method, which is adapted for processing high-performance 3D graphics. Also, the texture mapping unit is designed using the processor-memory integration technology to provide sufficient bandwidth. Therefore, the tremendous memory bandwidth and the long latency required for texture mapping can be reduced by this approach.

The CalmRISC32 FPU is RISC style coprocessor for embedded systems. It supports IEEE-754 standard single precision addition/subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, and load/store. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order if some constraint is resolved-data dependency, resource conflict, and exception prediction. Standard cell base design technique is used to save design time and cost. First prototype is running at about 70 Mhz with worst-case delay in gate level simulation.

Processing flow of the conventional floating point addition/subtraction operation consists of several steps, i.e., alignment, addition/subtraction, normalization, and rounding stages in this order. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel was presented where any additional execution time nor any high speed adder for rounding operation was not required. But, the sticky-bit, which is generated at the alignment stage, is included in the critical path delay. In this research, a technique to remove the sticky-bit generation from the critical path is proposed. Its hardware model and correctness proofs are provided and evaluated. The proposed floating point adder provides effectiveness in the points of chip area and its execution time.

A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor, the prototype chip of which was recently manufactured with a 0.25 /spl mu/m, 4-metal process by Samsung Electronics Co.

Texture mapping is commonly used to make images realistic in most current graphics systems. Texture mapping, however, requires high memory bandwidth and low memory latency to obtain good performance. Recently, a few studies have been carried out to use a cache memory system in texture mapping in older to overcome these problems and those studies show that the cache is useful for texture mapping. Miss distribution of texture cache is analyzed and we find out that quite a few conflict misses occurred by period. Considering this fact, cache systems such as Victim, Half and Half and Cooperative cache which are known to be effective to reduce conflict misses, are evaluated and compared to each other. Performance evaluation is carried out through trace-driven simulation using the DineroIII, and the results reveal that victim cache also has cost-performance effectiveness in texture mapping.

Digital image stabilisation for mobile devices based on real-time phase correlation with support for the SIMD data path is presented. By using sub-image projection, the phase correlation process can be fitted within the real-time criteria. The proposed method acquires a global motion vector from a sub-image at the centre of the viewport, which is projected onto the x- and y-axes on which the phase correlation is performed. The projection stage and the FFT calculations are accelerated using the Neon SIMD engine that is facilitated in the ARM CPU. With this acceleration, the global motion vector for each image frame can be calculated in

The Practical Fat Tree Network (PFN) is proposed as an efficient interconnection structure for parallel processing computers using a butterfly network. It satisfies the concept of volume universality from Leiserson's theoretical fat tree network [1]. In the fat tree network, the locality of input traffic is a very important factor because it has significant effects on performance. The proposed performance model effectively highlights this locality factor. Performance is analyzed according to varing input traffic loads and buffer sizes. The accuracy of the model is confirmed by comparing its results with those from simulation. The proposed model is found to be very accurate. Although the PFN is a dynamic connection network, it shows low delay and high throughput for the applications that have locality.

A new conceptual cache, NRP (nonreferenced prefetch) cache, is proposed to improve the performance of instruction prefetch mechanisms which try to prefetch both the sequential and nonsequential blocks under limited memory bandwidth. The NRP cache is used for storing prefetched blocks that were not referenced by the CPU. These blocks were discarded in previous prefetch mechanisms. By storing the non-referenced prefetch blocks in the NRP cache, both cache misses and memory traffic are reduced. A prefetch method to prefetch both the sequential and the nonsequential instruction paths is designed to utilise the effectiveness of the NRP cache. The results from trace-driven simulation show that this approach provides an improvement in memory access time compared to other prefetch methods. Particularly, the NRP cache is more effective in a lookahead prefetch mechanism that can hide longer memory latency. Also, the NRP cache reduces the additional memory traffic required to prefetch both instruction paths. This approach can achieve both improved memory access time and reduced memory traffic in a cost-effective cache design.