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The article is a continuation of a hands-on semicustom IC design series. The layouts use products from American Microsystems Inc. (AMI) and International Microelectronic Products (IMP). The AMI design employs a single-level-metal gate array. The IMP version uses single-level-metal standard cells. Both designs are based on 3-microm Si-gate CMOS technology. The article includes several diagrams that illustrate circuit designs based on the AMI and IMP products.

Mostek Corp. is advocating a sixteen-bit wide memory chip housed in a twenty-eight-pin package for parts that store a megabit or more. The firm is introducing a complementary-MOS megabit ROM (64-K by 16 bits), called the MK3901, and wants to make the twenty-eight-pin footprint a standard. The Joint Electon Device Engineering Council's 43.2 committee is considering both forty-and twenty-eight-pin packages for the next generation of memory chip standards. A diagram illustrates Mostek's projection of consumption of megabit worldwide ROMs and dynamic RAMs.

Computers soon will design themselves. Work towards totally automated design is being carried out. Main aims of automation are on system synthetics based on application programs and unified CAE systems for IC design. MIMOLA design system is a microprogramming language and can be used in application programming for CAE systems. VLSI Technology Inc. offers a whole team of design aids. A block diagram shows the MIMOLA system.

For VLSI to deliver its true advantages, design techniques must undergo changes. Designers must think about testability before designing a system. If testing becomes more efficient, semicustom chip design will be easy. Test software really presents a hurdle in the chip design.

At least for the 1980s, silicon-based processing will dominate the electronics industry. Technologies such as silicon-on-sapphire, Josephson-junction, and gallium-arsenide will continue to deliver for specific applications. However, for memories and microprocessor-related circuits, most engineers will remain with tried-and-true silicon-based processing - primarily because of the ongoing improvements in silicon technology.

Silicon compilation permits the automatic synthesis of complex VLSI designs from high-level architectural descriptions of systems without loss of performance or inefficient use of chip area. The architectural descriptions are in terms of known structures that are synthesized from the compiler's stored rules. The design process proceeds by successive refinement, or incremental design. Silicon compilation creates design leverage by allowing the designer to hold design activity to high levels of abstraction, permiting greater design creativity and exploration. Integrated design, verification, and documentation are all provided by silicon compilation to enhance the design flow. The design of an Ethernet data-link controller and the RasterOp Controller used in Sun workstations, both by Silicon Compilers Inc., showed time and manpower improvements over the classical design process. Silicon Compilers also contributed to the rapid turnaround of the MicroVAX I data-path chip. Static-timing analysis guaranteed the performance of the MicroVAX chip. The integration of entire systems on single chips is the direction that the industry is going. Photographs illustrate the results of the silicon compilation process. Diagrams and tables show the benefits of silicon compilation in manpower and tools required.

Silicon-gate CMOS integrated circuits are moving into linear circuits thanks to low power consumption and ideal switching characteristics. For sampled-data circuits, silicon-gate CMOS is superior to metal-gate CMOS in the areas of charge injection, speed and better threshold stability. As for starting material, the n-well process is better for digital circuits, while p-well suits linear circuits. Linear circuits also must operate at higher voltages, and so space between geometries must be larger and junctions must be deeper. This results in lower speed and density. Diagrams illustrate the technologies.

Raytheon Co. will introduce a family of high-speed programmable read-only-memory chips that use amorphous-silicon switches for improved density. The PROMs will use an antifuse approach in which an amorphous-silicon switch acts as an insulator until a programming voltage is applied. Stacking the amorphous-silicon switches above the Schottky diodes allows for density improvements.

The year 1983 saw growth in semicustom integrated circuits and evolution of IC-design technologies, tools, and support programs. Standard cells are becoming alternatives to gate arrays, and compilers are making standard-cell design more flexible. The semicustom-IC industry should grow dramatically over the next decade. Silicon compiler technology should make rapid progress in the coming years also. The use of semicustom ICs changes the economics of system design. Design decisions are increasingly based on functional and design-complexity considerations. Vendors' circuit libraries should include basic versions of common functions and enough variety to allow the design of a broad range of systems. Architecturally optimized ICs can be uniquely suited to specific applications. Core microprocessors can restrict architectural freedom and make little economic sense. Analog- circuit integration is limited by process characteristics. Programmable logic should play a bigger part in future system design. Photographs illustrate several chips designed using semicustom ICs. The economics of design are illustrated by graphs and diagrams. A table lists manufacturers of semicustom ICs.

Westinghouse Electric Corp. is the prime contractor in the Department of Defense's $1.2 million effort to develop magnetic Czochralski crystal growth for its Very High Speed Integrated Circuits Program. The Japanese developed technique applies a strong magnetic field to the silicon melt to produce purer and more uniform silicon to improve yields on 1.25 micrometer devices. A correlation between quality of starting material and yields are seen in current bipolar chips.