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International audience; Ultimate-thinning-and-transfer-bonding (UTTB) of RF SOI-CMOS chips is demonstrated on plastic, metal and glass substrates. Beyond process simplicity, UTTB can be tailored to meet specific application requirements like ultra mechanical flexibility, heat dissipation, transparency while retaining same f(T)/f(max) performance and improving harmonic rejection when compared to conventional rigid SOI.

A fast modulator for a dynamic supply linear RF amplifier has been integrated in a 0.35-/spl mu/m CMOS technology. The use of this modulator with an external linear power amplifier (PA) allows to maintain its efficiency at a higher level than it would with the same PA supplied at constant voltage. The modulator is designed to follow rapid envelope variations at high efficiency without compromising the RF PA linearity.

International audience; Boron delta-doping of diamond has appeared as a promising viable approach for the fabrication of high performance RF power transistors taking advantage of diamond properties. Here structures based on p-/p+/p- multilayers were synthesised on (100) HPHT Ib substrates using MPCVD. An original gas injector system was developed enabling to significantly improve the sharpness of both interfaces between p+ and p- layers with a good reproducibility. SIMS profiles recorded on the doping transients still demonstrate an asymmetry of the interface sharpness from 7nm/decade to 2nm/dec on the p-/p+ and the p+/p- interfaces, respectively. The observed differences are here explained and confirmed experimentally, and result from the combination of ion mixing with the effect of the surface roughness, thus limiting the SIMS resolution in depth. The MRI (Mixing Roughness Information) model then allows to evaluate the real value of the delta thickness achievable using this technique to 7 nm and the negative and positive gradients to identical values, namely of 1.4 nm/dec.

International audience; Leveraging the performances offer at MilliMeter-Wave (MMW) by advanced BiCMOS and CMOS technologies, various researches have evaluated the potential of silicon technologies to develop cost effective MMW applications (60 GHz wireless link is a good example). But MMW applications do not only require low cost RFICs, the development of low cost antenna and package is also a key issue. This point has been largely investigated at 60 GHz to address both antenna characterization and the development of low cost packaging technologies. Since 60 GHz technology is currently under deployment in products (WiGig standard), research activity is moving higher in frequency in order to achieve higher data rates (@ 120 GHz or beyond 200 GHz), which makes necessary to develop dedicated antenna measurement setup. In this paper, we present a 3D radiation pattern measurement setup for probe-fed F-band (90-140 GHz) antennas and we evaluate its performances using preliminary antenna design achieved in glass IPD TM technologies.

This paper describes a 4.48 GHz–5.89 GHz LC voltage-controlled oscillator (LC-VCO) as a key component in RF transceivers. The circuit is fully designed in TSMC’s 65 nm radio-frequency complimentary metal-oxide-semiconductor technology process. The LC-VCO uses the structure of only one couple of NMOS differential negative resistances, tank circuit which consists of an optimal on-chip spiral inductor with switched capacitor and varactor arrays. The proposed design accomplishes wide tuning range frequency by using 6-bit switch capacitor array in addition to linearly varying MOS varactors. A switched current source block is used to improve the performance of the LC-VCO. The oscillator has a wide tuning range, between 4.48 GHz and 5.89 GHz. The LC-VCO dissipates 15.96 mW from a voltage supply of 1.8 V, whereas its phase noise is -124.1 dBc/Hz at 1 MHz offset of a at 5.89 GHz carrier. DOI: http://dx.doi.org/10.5755/j01.eee.20.2.6383

International audience; This paper presents a W-band on-chip elliptical slot antenna fabricated in the IBM CMOS8RF (0.13 μm) process. Improved antenna efficiency is achieved using a 400 μm quartz superstrate, which increases antenna gain from -5.7 dB to 0.5 dB. The superstrate-loaded antenna has a measured impedance bandwidth of 3.9% and an estimated efficiency of 26%.

International audience; During past years, various research teams have been implied in the development of 60 GHz chipset solutions, using both BiCMOS and advanced CMOS technologies. But for the 60 GHz market to flourish not only low cost RFICs are required, low cost antennas and packages are also key points. So far, HTCC technology has been seen as the chosen one when targeting millimeter wave (MMW) applications. But since 60 GHz applications are targeting large volume consumer applications, the pressure on the cost of the packaging will become higher and it is highly desirable to explore alternative lower cost solutions than HTCC. In this paper, we present 60GHz integrated antennas in an innovative low cost High Density Interconnect (HDI) organic technology demonstrating promising high-gain antenna solution (>; 7 dBi).

International audience; In this paper, we investigate an alternate test strategy for RF integrated circuits based on DC measurements. A methodology to select the appropriate DC parameters is presented, that allows precise estimation of the DUT performances while minimizing the number of measurements to be carried out. The method is demonstrated both on simulation test data from a Low-Noise Amplifier (LNA) and production test data from a Power Amplifier (PA). Results indicate that good prediction of the RF performances can be achieved using only a reduced number of DC measurements.

In this chapter we present two innovative contributions derived by the System-on-Chip (SoC) approach combining standard microelectronic technologies with the life and geo-sciences. The former regards a SoC radar sensor for contactless cardiopulmonary monitoring. The latter focuses on a SoC radiometer for temperature remote sensing. For both micro-sensors we report the framework and motivation, theoretical concepts, current results, and the future direction of ongoing research by the authors.

A comparison study was carried out between a wireless sensor node with a bare die flip-chip mounted and its reference board with a BGA packaged transceiver chip. The main focus is the return loss (S parameter S11) at the antenna connector, which was highly depended on the impedance mismatch. Modeling including the different interconnect technologies, substrate properties and passive components, was performed to simulate the system in Ansoft Designer software. Statistical methods, such as the use of standard derivation and regression, were applied to the RF performance analysis, to see the impacts of the different parameters on the return loss. Extreme value search, following on the previous analysis, can provide the parameters' values for the minimum return loss. Measurements fit the analysis and simulation well and showed a great improvement of the return loss from -5dB to -25dB for the target wireless sensor node.

This paper discusses a novel tag/reader system, based on the passive, far-field RFID principle, with megabits per second read capability at operating ranges of several centimeters. The system operates in the ISM band at 2.45 GHz. A maximum data rate of 4 Mbps was demonstrated, at a tag/reader distance of 5.5 cm. The tag is entirely realized in a standard CMOS process for minimum costs. The described system also uses wireless voltage regulation, an innovative technique that allows to improve the overall efficiency of wireless power transmission and to save power on reader side. According to the measurement results, it is shown that the efficiency was improved by a factor larger than four in the best case. ©2008 IEEE.

The target in the design of CMOS Radio-Frequency (RF) transceivers for wireless application is the highest integration level, despite reliability issues of conventional submicron MOSFETs, due to high RF voltage and current peaks. In this scenario, this paper investigates gate-oxide breakdown under RF stress by using a class-E Power Amplifier (PA) for experiments. We will show that maximum RF voltage peaks for safe device operation are much larger than usual DC limits, and that the physical mechanism of oxide degradation is triggered by the rms value of oxide field, and not by its maximum as generally believed. This finding has a strong impact on RF circuit designs, especially in MOSFET scaling perspectives. Finally, breakdown effects on PA operations will be discussed.

A granular NiFe thin film with large in-plane magnetic anisotropy and high ferromagnetic-resonance frequency developed for radio-frequency integrated circuit (IC) applications is presented. During the deposition, three-dimensional (3D) growth occurs, yielding NiFe grains (? ? 1.0??m). Nanonuclei (? ? 30–50?nm) are observed in single NiFe grains by atomic-force microscopy (AFM). The in-plane magnetic anisotropy is estimated to be ? 50?mT. The frequency-dependent complex permeability is extracted. By taking the NiFe film as a magnetic core, solenoid-type inductors are fabricated and demonstrated and show a high operating frequency ( ? 5.5?GHz) with a maximum quality factor ( ? 3).

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

A continuous-time analog delay is designed as a requirement for the autocorrelation function in the quadrature downconversion autocorrelation receiver (QDAR). An eight-order Fade approximation of its transfer function is selected to implement this delay. Subsequently, the orthonormal form is adopted, which is intrinsically semi-optimized for dynamic range, has low sensitivity to component mismatch, high sparsity and whose coefficients can be physically implemented. Each coefficient in the state-space description of the orthonormal ladder filter is implemented at circuit level using a novel 2-stage gm cell employing negative feedback. Simulation results in IBM's Bi-CMOS 0.12 μm technology show that this delay filter requires a total current of 70 mA at a 1.6 V power supply. The 1-dB compression point of the delay is at 565 mV and the SNR is 47.5 dB. On performing a Monte Carlo simulation it becomes evident that the response of the frequency selective analog delay does not suffer drastically from neither process variations nor component mismatch

A continuous-time analog delay is designed as a requirement for the autocorrelation function in the quadrature downconversion autocorrelation receiver (QDAR). An eight-order Fade approximation of its transfer function is selected to implement this delay. Subsequently, the orthonormal form is adopted, which is intrinsically semi-optimized for dynamic range, has low sensitivity to component mismatch, high sparsity and whose coefficients can be physically implemented. Each coefficient in the state-space description of the orthonormal ladder filter is implemented at circuit level using a novel 2-stage gm cell employing negative feedback. Simulation results in IBM's Bi-CMOS 0.12 μm technology show that this delay filter requires a total current of 70 mA at a 1.6 V power supply. The 1-dB compression point of the delay is at 565 mV and the SNR is 47.5 dB. On performing a Monte Carlo simulation it becomes evident that the response of the frequency selective analog delay does not suffer drastically from neither process variations nor component mismatch

The double-tuned overcoupled air transformer, commonly used in radio-frequency high-voltage supplies, is represented by an equivalent primary circuit. This circuit can be used very advantageously to develop the theory of operation of the oscillator, including the two possible operating frequencies, the necessary conditions for oscillation and maximum efficiency, and the variation of operating frequency and load resistance with primary tuning. It is shown that, at the operating frequency, the load impedance is purely resistive. The various resistances in the circuit representing the power losses and the load resistance are included in the equivalent circuit resistance, which appears as the plate load of the class-C oscillator tube. This greatly facilitates the design of a circuit to give any required power and voltage output. There are several ways in which this design problem can be approached, and the paper outlines the method which was used and found successful by the author., First published in the Proceedings of the I.R.E. (Vol 37, No. 2)