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This chapter presents an introduction to superconductor-semiconductor (S-Sm) tunnel junction coolers, before outlining some of the progresses made during the nanofunction program on electron cooling from 300 mK in silicon-based junctions. PtSi is an interesting material to consider as a Schottky barrier to Si because of its role as a contact material in the semiconductor industry. The chapter investigates carrier-phonon coupling in unstrained silicon, with both n- and p-type dopants, and the effect of increasing the strain in silicon grown on a Si1–xGex virtual substrate with the Ge fraction x of 20% and 30%. The reduction in e-ph coupling shows promise for dramatic improvements in performance of bolometric detectors for a variety of electromagnetic radiation sensing applications using silicon based cold electron bolometers.

We present a detailed direct current and radiofrequency study of fully depleted dopant-segregated Schottky barrier (SB) MOSFETs on thin-body Silicon-on-Insulator. On-wafer scattering-parameter measurements of n-type NiSi source/drain SB-MOSFETs provide an in-depth understanding of key device parameters (transconductances and capacitances) as a function of the implanted arsenic dose, i. e., different SB height. Devices with 80-nm-channel length show a high ON current of 1150 mA/mm and exhibit a unity-gain cutoff frequency of f(T) = 140 GHz.

Some unique characteristics of epitaxial growth of oxide thin films prepared by pulsed laser deposition have been observed in this study. The study demonstrates that deposition temperature is one of the most important parameters in controlling orientation and epitaxial growth of oxide thin films. Higher temperature is usually imperative for the epitaxial growth. The threshold temperature for epitaxial growth of oxide film depends on the substrate materials, which relate mainly to the lattice mismatch and component similarity between the film and the substrate. A small lattice mismatch and a high component similarity are favorable to epitaxial growth and may decrease the epitaxial threshold temperature significantly. In addition, the orientation of CeO 2 film, grown on Si substrate, possess a unique dependence on ambient oxygen pressure, which demonstrates the significant influence of oxygen pressure to the epitaxial orientation of oxide thin films.

Epitaxial CoSi2 layers were grown on Si(1 0 0) using molecular beam allotaxy. Boron ion implantations and rapid thermal oxidation (RTO) were performed. During oxidation, SiO2 formed on the surface of the CoSi2 layers, and the silicides was pushed into the substrate. The diffusion of boron was slightly retarded during oxidation for the specimen with a 20 nm epitaxial CoSi2 capping layer as compared to the specimen without CoSi2 capping layer. The electrical measurements showed that the silicide has good Schottky contacts with the boron doped silicon layer after RTO. A nanometer silicide patterning process, based on local oxidation of silicide (LOCOSI) layer, was also investigated. It shows two back-to-back Schottky diodes between the two separated parts of the silicide.

A novel nanometer patterning technique was developed to pattern epitaxial CoSi2 layers and to fabricate Schottky-tunneling MOSFETs. The nanopatterning method is based on the local oxidation of silicide layers. A feature size as small as 50 nm was obtained for 20 nm epitaxial CoSi2 layers on Si(100) after patterning by local rapid thermal oxidation in dry oxygen. A Schottky-tunneling MOSFET with epitaxial CoSi2 Schottky contacts at both the source and the drain was fabricated using this nanopatterning method to make the 100 nm gate. The device shows good I–V characteristics at 300 K.

In this work, Gd-oxide dielectric films were deposited on Si by pulse laser deposition method (PLD), moreover, the micro-structures and electrical properties were reported. High-resolution transmission electron microscopy (HRTEM) and X-ray diffraction (XRD) indicated that Gd-oxide was polycrystalline Gd2O3 structure, and no Gd metal phase was detected. In addition, both interface at Si and Ni fully silicide (FUSI) gate were smooth without the formation of Si-oxide. X-ray photoelectron spectroscopy (XPS) confirmed the formation of Gd2O3 and gave an atom ratio of 1:1 for Gd:O, indicating O vacancies existed in Gd2O3 polycrystal matrix even at O2 partial pressure of 20 mTorr. Electrical measurements indicated that the dielectric constant of Gd-oxide film was 6 and the leakage current was 0.1 A/cm2 at gate bias of 1 V.

Nanometer patterning of single crystalline CoSi2 layers on Si(100) by local oxidation was studied. Epitaxial CoSi2 layers with thicknesses around 20 nm were grown on Si(100) by molecular beam allotaxy. A nitride layer was deposited on the surface of the silicide and subsequently patterned along the 〈110〉 direction by optical lithography and dry etching. Rapid thermal oxidation was then performed at a temperature of 950°C in dry O2 ambient. During oxidation SiO2 forms on the unprotected regions of the CoSi2 layer. The silicide in this region is pushed into the substrate. Near the edges of the nitride mask the silicide layer thins and finally separates from the protected part. Using this patterning method highly uniform gaps with a width of 70 nm between the two silicide layers have been obtained. It was shown that the separation gap is not only dependent on the oxidation parameters, but also on the thickness and the width of the nitride mask due to the stress effects. Possible applications of this new technique are discussed.

Epitaxial growth of La 0.5 Sr 0.5 CoO 3 (LSCO) film has been achieved by pulsed laser deposition. Widely used substrates, MgO, SrTiO 3 and LaAlO 3 were chosen to examine the effect of the substrates on the growth of LSCO films. The influence of the substrate temperatures ( T s ) on the characteristics of the LSCO films was studied in a temperature range of 500–850°C. The LSCO films deposited at substrate temperatures of T s =800–850°C show good epitaxial features, better than that of the films deposited at lower T s . The experimental results reveal that the lattice mismatch and the difference of the expansion coefficients between the substrates and the LSCO films are important in the growth process of the LSCO films.

CeO2 thin films were grown on (1 0 0) silicon substrates by pulsed laser deposition. X-ray diffraction results indicated that fully (1 1 1) oriented and highly (1 0 0) oriented CeO2 films on Si (1 0 0) were achieved, respectively. Oxygen pressure was found to be important to control the crystallographic orientation. A possible mechanism was proposed to explain these results. Auger electron spectroscopy and Rutherford backscattering spectrometry analysis showed an uniform concentration distribution of Ce and O throughout the epitaxial layer independent of the oxygen pressure. The electrical properties of the films were characterized by capacitance–voltage measurements.

Growth of (K 0.5 Na 0.5 ) 0.2 (Sr 0.75 Ba 0.25 ) 0.9 Nb 2 O 6 (KNSBN) films on (0 0 1) MgO substrates and on (0 0 1) oriented La 0.5 Sr 0.5 CoO 3 (LSCO) layers by pulsed laser deposition has been studied. X-ray diffraction θ–2θ scans indicated that the KNSBN films were of c -axis orientation. X-ray Phi scans on the (2 2 1) reflection revealed that the films grown on the MgO substrates were epitaxial growth with two [1 0 0]KNSBN in-plane orientation rotating about ±18° with respect to [1 0 0]MgO. Sandwich structures of KNSBN films with LSCO as top and bottom electrodes have been performed on (0 0 1)LaAlO 3 (LAO) substrates. The measurements of the ferroelectricity of the as-grown film gave hysterisis loop with the remnant polarization of P r ∼ 8 μ C cm −2 and the coercive field of E c ∼ 55 KV cm −1 .

We have investigated a process for tailoring of epitaxial CoSi2/Si nanostructures using low temperature wet oxidation. A separation between two CoSi2 layers on a Si substrate in the range of 60 nm is generated by a self-assembly process. During subsequent low temperature wet oxidation, SiO2 formation on top of the silicide layers pushes the latter into the substrate. At the edges of the gap, the silicide layers are shifted in both and directions, leading to an effective reduction of the separation width to dimensions below 20 nm and eventually to merging of the two layers. The significantly lower oxidation rate of the silicon in the initial gap compared with the CoSi2 provides the excess Si for the shift in the direction. The structures were investigated using transmission electron microscopy (TEM) and scanning electron microscopy (SEM).

Steep slope devices, like Tunnel FETs (TFETs), provide small subthreshold slope (SS)

MOSFETs and Tunnel-FETs (TFETs) based on arrays of nanowires (NWs) with 10 × 10 nm2 cross-section have been fabricated with strained silicon on insulator substrates. MOSFET devices show near ideal subthreshold slope close to 60 mV/dec proving excellent channel control achieved by high-klmetal gate stack. As expected fundamental differences between MOSFETs and TFETs in current-voltage characteristics are observed and analyzed. Low frequency noise spectra are studied for both types of devices. The devices show different behavior in terms of noise spectral density as a function of the applied gate voltage. A Hooge parameter of α = 7.3 × 10−3 is derived for the NW MOSFETs.

Reducing the drain voltage, VDD, is the key leverage to lower power dissipation in circuits, since the dynamic losses increase proportional to VDD2 multiplied by the frequency. Presently, fully depleted silicon on insulator (FDSOI) technology sets the level pole for ultra-low power applications: At 0.6 V a clock frequency of 1 GHz has been achieved [1]. A further reduction of VDD limits the performance considerably. IMEC announced an ultralow power chip working at voltages from 1V down to 0.4 V. In the sub-threshold regime at 0.4 V the clock frequency reduces to 1 MHz but also the energy consumption drops to a fraction of standard circuits [2]. Numerous applications are foreseeable for battery-powered and energy scavenging smart devices. The question is will tunnel field effect transistors (TFET) provide superior performance.

This paper presents experimental results on tunneling field-effect transistors (TFETs) based on SiGe on SOI nanowire arrays. A SiGe-Si heterostructure TFET with a vertical tunneling junction consisting of an in situ doped SiGe source and a Si channel is demonstrated. The device shows switching behavior over a drain current range of up to 8 orders of magnitude with a minimum slope of 90 mV/dec. A larger tunneling area results in an increase of on-current. The heterojunction TFET shows great improvement compared to a homojunction SiGe on SOI nanowire design with implanted junctions. Temperature dependent measurements and device simulations are performed in order to analyze the tunnel transport mechanism in the devices.

Recent achievements of silicon based tunnel field effect transistors (TFETs) and remaining major challenges are overviewed. Particular emphasis is placed on the band to band tunneling (BTBT) junctions, the heart of the device. Dopant segregation from ion implanted ultrathin silicide contacts proved as viable method to achieve steep tunneling junctions. This avoids defect generation by direct implantation into the junction and thus minimizes the risk of trap assisted tunneling. The method was applied to strained silicon, specifically to nanowire array transistors. This enabled the realization of TFETs with fairly high currents and first complementary TFET inverters with sharp transitions and good static gain, even at very low drain voltages of VDD = 0.2 V. These achievements suggest a considerable potential of TFETs for ultralow power applications. Some novel concepts, e.g. to enlarge the tunneling area by “line tunneling”, are addressed. A benchmarking figure summarizes the present status.

Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at VDS=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is

An electron cooling junction using platinum silicide as a superconductor contact is demonstrated for the first time. The junction shows encouraging electrical characteristics and a fit to a standard cooling model predicts cooling from 100 mK to 50 mK for a test device. Silicides have been widely used in the semiconductor industry because of their reliability and reduced contact resistance; hence this technology could find wider application in a silicon-based electron refrigerator.

We present gate all around strained Si (sSi) nanowire array TFETs with high ION (64μA/μm at VDD=1.0V). Pulsed I-V measurements provide small SS and record I60 of 1×10-2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and ION. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response.

In this paper, the recent progress and applications of ion beam defect engineering (IBDE) are reported. IBDE in silicon shows that it can be used for (1) the reduction of secondary defects created by the dopant-ion implantation, (2) the gettering of F atoms from the B doped regions in BF2 implanted silicon; (3) the reduction of B diffusion in BF2 implanted silicon. IBDE applications in optoelectric crystals are also investigated. Waveguide can be formed in LiNbO3 by MeV Cu ion implantation and in KTiOPO4 (KTP) by multi-energy (MeV) He ion implantation. Mechanisms and trends of IBDE in the future are also discussed.

The reduction of secondary defects in 50 keV P + implanted silicon has been studied by the Rutherford backscattering/channeling technique. It is found that the secondary defects in the P + damaged region was reduced by MeV Si ion irradiation. As for the case of low dose P + ion implantation in Si, the reduction of pre-amorphization defects was less sensitive to the dose of MeV Si ions. However, in the higher dose P + implanted sample, more end of range defects were reduced by a higher dose MeV Si ion irradiation. The gettering effect of extended defects for point defects is discussed.

We report on field emission from SnO2 nanobelt arrays with the length of about 90 μm grown on silicon substrates. The turn-on field of the nanobelt arrays at the current density of 1μA∕cm2, is 4.5, 3.0, 2.4, and 2.3V∕μm as the distance between anode and cathode (d) is 0.1, 0.2, 0.35, and 0.5 mm, respectively. The current density rapidly reaches 2.1mA∕cm2 at the electrical field of 4.4V∕μm at d=0.35mm. The current density is higher than or comparable to those of the carbon nanotubes and other one-dimensional nanostructured materials. We also discuss the mechanism of high current densities and estimate the enhancement factor according to both the Fowler–Nordheim law and the reported model on micrometer-long of carbon nanotubes.

A silicidation process was developed to produce high-quality CoSi2 directly on SiO2, which can be used for metal gates of metal-oxide-semiconductor field-effect transistors (MOSFETs). Normally, the formation of a CoSi2 layer on SiO2 is very difficult because of the requirement for an exact Co/Si thickness ratio. In our process, an additional Si layer was deposited after the first rapid thermal processing (RTP) at 500 degreesC and selective etching of the unreacted Co. The additional Si layer provided a Si supply for the second RTP at a higher temperature. This method allows the Co layer thickness to be varied over a fairly large range, and in addition, the microstructure of the silicide layer and the CoSi2/SiO2 interface were substantially improved. (C) 2004 American Institute of Physics.

1.0 and 2.0 MeV Ti ions have been implanted into silicon at different angles to study longitudinal and transverse distributions. The profiles of implanted Ti ions in Si at different angles were measured by secondary ion mass spectrometry (SIMS). The longitudinal and transverse moments are compared with the TRIM'90 Monte Carlo simulation. The results show that the longitudinal moments-projected range and range straggling-are consistent with calculated values within 13% and 15% respectively and the transverse moment is in agreement with the TRIM'90 simulation within 29%. The depth distribution obtained is also compared to Gaussian and Pearson functions.

New empirical equations describing the rate of ion-induced crystallization at a Si crystal/amorphous interface have been developed. In our model, crystallization/amorphization at the interface arises from formation of hot spots and of knock-ons in the collision cascades. It is presumed that the hot spots induce amorphous-to-crystal transformation which lowers the free energy, similarly to heating to high temperatures, and that the bond rearrangement by a series of displacements by knock-ons and recombination to the original lattice point in collision cascades can lead to both crystal-to-amorphous and amorphous-to-crystal transformations. In both hot-spot and knock-on effects, the presence of di-vacancies under irradiation with ion beams is assumed to prohibit crystallization. The model can explain the experimental observation that the crystallization/amorphization rate is scaled by X = o 1 2 exp (C v /2kT) , the product of the root of the flux and the inverse of root of the Boltzmann factor for the motion of the di-vacancies. Crystallization rate in the hot-spots derived assuming that an incident ion induces spontaneous crystallization within a characteristic volume along the track reveals that the radius is 10 atomic distances and the thickness of is about 0.3 monolayer for 1.5 MeV Xe ions. The calculated crystallization/amorphization rate fits to experimental results over a wide temperature range.

Well-aligned arrays of ZnO nanoneedles were fabricated using a simple vapor phase growth. The diameters of the nanoneedle tips are as small as several nanometers, which is highly in favor of the field emission. Field-emission measurements using the nanoneedle arrays as cathode showed emission current density as high as 2.4 mA/cm2 under the field of 7 V/μm, and a very low turn-on field of 2.4 V/μm. Such a high emission current density is attributed to the high aspect ratio of the nanoneedles. The high emission current density, high stability, and low turn-on field make the ZnO nanoneedle arrays one of the promising candidates for field-emission displays.

Stoichiometric ZnSe nanowires have been synthesized through a vapor phase reaction of zinc and selenium powder on the (100) silicon substrate coated with a gold film of 2 nm in thickness. The microstructures and the chemical compositions of the as-grown nanowires have been investigated by means of electron microscopy, the energy dispersive spectroscopy, and Raman spectroscopy. The results reveal that the as-grown materials consist of ZnSe nanowires with diameters ranging from 5 to 50 nm. Photoluminescence of the sample demonstrates a strong green emission from room temperature down to 10 K. This is attributed to the recombination of electrons from conduction band to the medium deep Au acceptors.

Si Nanowire (NW) TFETs with a NW cross section of 30×7nm2 were fabricated on ultra thin SOI. Implanattion into epitaxial NiSi 2 silicide (IIS) source and drain and a subsequent anneal at low temperatures for dopant segregation (DS) were used for formation of junctions. Si NW Schottky MOSFETs with dopant segregated NiSi 2 source/drain showed very low Schottly barrier, which demonstrates a high concentration of dopants segregated at the NiSi 2 edges even after low temperature anneals. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n tunneling FETs. The steep junctions fromed at low temperature improve the band-to-band tunneling. P-channel TFETs showed high on-currents (I ON ) of 18.8 μA/μm, very low off-currents (I OFF ) and a large I ON /I OFF ratio up to 108.

In this work, we studied the nickel germano-silicide formation on thin SiGe layers epitaxially-grown on silicon substrate. Single crystal NiSiGe film with a thickness of 5.5nm was formed at 400°C and showed a low specific resistance of 30uΩcm. A thicker NiSiGe layer resulted from a thicker Ni showed poly-crystalline structure with rough surface and interface. We also found Ge and Ni diffuse simultaneously to the silicon substrate during germane-silicidation, causing degradation of the NiSiGe layers.

Planar and nanowire (NW) tunneling field effect transistors (TFETs) have been fabricated on ultra thin strained and unstrained SOI with shallow doped Nickel disilicide (NiSi 2 ) source and drain (S/D) contacts. We developed a novel, self-aligned process to form the p-i-n TFETs which greatly easies their fabrication by tilted dopant implantation using the high-k/metal gate as a shadow mask and dopant segregation. Two methods of dopant segregation are compared: Dopant segregation based on the “snow-plough” effect of dopants during silicidation and implantation into the silicide (IIS) followed by thermal outdiffusion. High drive currents of up to 60 μA/μm of planar p-TFETs were achieved indicating good silicide/silicon tunneling junctions. The non linear temperature dependence of the inverse subthreshold slope S indicates typical TFET behavior. Strained Si NW array n-TFETs with omega shaped HfO 2 /TiN gates showed high drive currents of 7 μA/μm @ 1V V dd and steep inverse subthreshold slopes with minimum values of 50mV/dec due to the smaller band gap of strained Si and optimized electrostatics.

Epitaxial growth of Ni germanosilicide on relaxed SiGe (30% Ge content) substrate has been achieved by using 3 nm Al interlayer. This epitaxial layer shows a very good uniformity and smooth interface and surface. The epitaxial layer and the SiGe substrate match very well and no misfit dislocation is found at the interface.

This paper presents experimental results on metal oxide semiconductor field-effect transistors (MOSFETs) featuring an array of 1000 trigated uniaxially strained nanowires with a cross-sections of 15 × 15 nm2 in combination with a HfO 2 /TiN gate stack. The high uniaxial strain along the wires reduces the band gap energy by approximately 140 meV and enhances the electron mobility. Ideal inverse subthreshold slopes of n- and p-channel devices of 60 (62) mV/dec at room temperature and I on /I off ratios up to 1010 were obtained.

Tunneling field-effect transistors (TFETs) were fabricated from compressively strained Si/SiGe wafers with a stepped gate to enhance band to band tunneling. In-situ highly p-doped Si 0.5 Ge 0.5 was used as source and As-implanted Si as drain. For the gate stack, conformal HfO 2 (k = 22) and TiN were deposited, which resulted in an effective oxide thickness (EOT) of ∼ 1nm. The TFET devices exhibit minimum point inverse subthreshold slopes as small as 65 mV/dec with applied back-gate voltage, and greatly suppressed ambipolar behavior. The improved performance compared to homogeneous planar devices is attributed to the superiority of the source/channel heterojunction and the shallow p-i junction.

Schottky Barrier MOSFETs were fabricated on ultra thin body (UTB) SOI with planar and NW-array device geometry. Implantation into Silicide (IIS) was used to lower the Schottky Barrier height for n- and p-type MOSFETs. The enhanced gate control of the NW array reduces Drain Induced Barrier Lowering (DIBL) and improves the subthreshold slope in n-type MOSFETs, whereas the corrected current drops. In p-type MOSFETs on current and Ion/Ioff ratio is enhanced.

High energy (MeV) Cu ions were implanted into n‐type Si samples at angles of 7°, 30°, 45°, and 60°. The doses were 5×1014 and 2×1014 ions/cm2. The damage profiles in Si(100) were investigated by a Rutherford backscattering/channeling technique with 2.1 MeV He ions. The longitudinal damage straggling and lateral damage spread are estimated for 1.0 MeV Cu+ implanted in Si(100). The values obtained are compared with the trim (transport of ions in matter) code. The results show that the longitudinal damage straggling is found to be in good agreement with the calculated one within 13% by use of the trim code, but the experimental value of the lateral damage spread is higher than the calculated one by about 28% using the trim code. The effect of dose rate, energy, and dose on damage distribution is investigated also.

Potassium titanyl phosphate (${\mathrm{KTiOPO}}_{4}$ or KTP) is a quadriatomic material made of O, P, K, and Ti which crystallizes in an orthorhombic structure with space group Pna2. The virgin KTP at different axial orientation, 〈100〉, 〈001〉, and 〈010〉, has been investigated by the channeling technique. The obtained corresponding minimum yields are 3.8, 4, and 11 %, respectively. Damage in KTP was created by 200 and 400 keV He-, Xe-, and Hg-ion irradiations with the dose varying from 1\ifmmode\times\else\texttimes\fi{}${10}^{13}$ to 1\ifmmode\times\else\texttimes\fi{}${10}^{16}$ ions/${\mathrm{cm}}^{2}$. The effect of ion mass, energy, dose, annealing temperature, and orientation of KTP on the damage has been studied. The number of displaced atoms, the damage peak, and damage width are extracted from the experimental data. The numbers of the displaced atoms obtained are compared with the trim code (the transport of ions in the matters). The result shows that the experimental numbers of the displaced atoms are in agreement with theoretical ones predicted by the trim code within the order of the magnitude. Also for the case of He ion implanted in KTP to a dose of 1\ifmmode\times\else\texttimes\fi{}${10}^{16}$ ions/${\mathrm{cm}}^{2}$, the recovery of the crystallinity of the KTP is observed after 800 \ifmmode^\circ\else\textdegree\fi{}C annealing.

The Rutherford backscattering (RBS) technique has been used to determine the range profiles of Ar+ implanted into polymer LPPS ([(C6H5) 8Si8O12]n) film at energies of 50, 70, 90, 100, 120, 150 and 170 keV. It is found that the range profiles are Gaussian, and the experimental projected ranges are in a good agreement with the theoretical values calculated by TRIM'89 code at energies below 120 keV. As for range straggling, the experimental values are higher than the prediction values. In addition, a variation in the implantation dose from 5 × 1015 to 1 × 1017 ions/cm2 at 50 keV does not affect the projected range, but the range straggling increases with the increasing implanted dose. The results of the implantation of Ar+ in polymer PVA ([C2H4O]n) and PAM ([C3H5ON]n) show that the implant Ar is released instantly during ion implantation.

We report on n-channel tunneling field-effect transistors (TFET) with a tensile strained Si channel and a compressively strained Si 0.5 Ge 0.5 source. The device shows good performance with an average subthreshold swing S of 80mV/dec over a drain current range of more than 3 orders of magnitude. We observed that an applied back-gate bias increases the on-current by a factor of 1.6, and improves the off-current and the subthreshold swing (S). Low temperature measurements show a slightly temperature dependent S, characteristic for a tunneling dominated device.

In this work, we address the effect of C+ ion implantation on the formation of nickel-germanosilicide NiSi 0.8 Ge 0.2 on relaxed Si 0.8 Ge 0.2 layers. The layer morphology and sheet resistance are investigated as a function of the C+ implantation dose and annealing temperature. The presence of C atoms increases the NiSiGe thermal stability by about 200°C. We demonstrate that the carbon atoms retard the growth of germanosilicide layers, stabilize the NiSiGe phase and, due to C segregation at grain boundaries and interface during annealing, smooth the Ni Si 0.8 Ge 0.2 /Si 0.8 Ge 0.2 interface.

Nano-contacts of NiSi to n+ and p+ doped strained and unstrained Si nanowires (NWs) were studied. Several Ni silicide phases were found: Ni 2 Si formed under the Ni electrodes, Ni 3 Si very close to the Ni electrodes, while NiSi was observed along the Si NWs. The NiSi nanowire length decreases with increasing wire cross section A. The silicidation speed along the Si NW shows a linear relation to 1/A, indicating volume silicidation of the Si NW. Uniaxial strain seems to have no effect on the silicidation speed. Contact resistivities as low as 1.2×10−8 Ω·cm2 were obtained for NiSi contacts to both, strained and unstrained Si nanowires.

Schottky barrier (SB)-MOSFETs with NiSi and epitaxial NiSi 2 S/D contacts with gate lengths as small as 20nm are presented. Epitaxial NiSi 2 FETs show higher on-currents than corresponding NiSi devices due to its lower SB height. A striking observation is that tunnelling currents through the fairly large SB decrease at very short gate lengths in SB-MOSFETs, in contrast to the scaling behavior of conventional MOSFETs. Simulations indicate that the potential in the channel increases due to overlap of the high source and drain barriers with decreasing gate length, leading to lower currents. Boron implantation into the silicide (IIS) was used to lower the SBH. Devices with epitaxial NiSi 2 show an improved performance after barrier lowering by dopant implantation into the silicide (IIS).

The chemical reactions at the higher-k LaLuO 3 /Ti 1 N X /poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO 3 with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed to explore the thermal stability of the gate stack. Based on these results an integration of TiN/LaLuO 3 in a gatefirst MOSFET process on SOI is shown.

Compressively strained Si 1−x Ge x band-to-band tunneling field effect transistors with planar structure and HfO 2 /TiN gate stack have been produced and analyzed, with different Germanium concentrations of x = 0.35, 0.50 and 0.65. Simulations using a nonlocal band-to-band-tunneling model have been carried out to understand the switching behavior and its dependence on the material parameters. One would expect an increase of the tunneling currents for the increase of x. However, the Si 0.5 Ge 0.5 devices show the highest I on and smallest S, whereas Si 0.35 Ge 0.65 devices exhibit decreased currents due to partial strain relaxation.

Strained SiGe heterostructure-on-insulator (0 0 1) and (1 1 0) PMOSFETs are investigated including important aspects like C–V characteristics, mobility, and ON current. The simulations are based on the self-consistent solution of 6 × 6 k · p Schrodinger Equation, multi subband Boltzmann Transport Equation and Poisson Equation, and capture size quantization, strain, crystallographic orientation, and SiGe alloy effects on a solid physical basis. The simulation results are validated by comparison with different experimental data sources. The simulation results show that the strained SiGe HOI PMOSFET with (1 1 0) surface orientation has a higher gate capacitance and a much higher mobility and ON current compared to a similar device with the traditional (0 0 1) surface orientation.

We report the study of high-dielectric-constant (high-kappa) dielectric LaLuO3 (LLO) thin film that is grown on AlGaN/GaN heterostructure by molecular beam deposition (MBD). The physical properties of LLO on AlGaN/GaN heterostrucure have been investigated with atomic force microscopy, x-ray photoelectron spectroscopy, and TEM. It is revealed that the MBD-grown 16 nm-thick LLO film is polycrystalline with a thin (similar to 2 nm) amorphous transition layer at the LLO/GaN interface. The bandgap of LLO is derived as 5.3 +/- 0.04 eV from O1s energy loss spectrum. Capacitance-voltage (C-V) characteristics of a Ni-Au/LLO/III-nitride metal-insulator-semiconductor diode exhibit small frequency dispersion (

Xe ions at energies from 50 to 350 keV, at increments of 50 keV, were implanted into Si3N4 films. The mean projected range and range straggling are measured by Rutherford backscattering using 2.1 MeV He ions. The longitudinal distribution parameters obtained are compared with our calculation procedure based on Biersack's angular diffusion model and Monte Carlo simulation (TRIM'89 code). Also the lateral spread of 100 keV Xe ions in Si3N4 film is obtained by means of implantation at tilted angles and Rutherford backscattering. The measured lateral spread is compared with TRIM'89. The result shows that the lateral spread of 100 keV Xe ions implanted in Si3N4 film is in good agreement with the TRIM'89 prediction within experimental error.

We have developed a method for fabricating epitaxial CoSi2 nanowires using only conventional optical lithography and standard silicon processing steps. This method was successfully applied to ultrathin epitaxial CoSi2 layers grown on Si(100) and silicon-on-insulator substrates. A nitride mask induces a stress field near its edges into the CoSi2/Si heterostructure and leads to the separation of the CoSi2 layer in this region during a rapid thermal oxidation step. A subsequent etching step and a second oxidation generate highly homogenous silicide wires with dimensions down to 50 nm. (C) 2001 American Institute of Physics.

Integration of lanthanum lutetium oxide (LaLuO 3 ) with a к value of 30 is demonstrated on high mobility biaxially tensile strained Si (sSi) and compressively strained SiGe for fully depleted n/p-MOSFETs as a gate dielectric. N-MOSFETs on sSi fabricated with a full replacement gate process indicated very good electrical performance with steep subthreshold slopes of ∼72 mV/dec and I on /I off ratios up to 109. Strained SOI (sSOI) channel devices show higher electron mobility of 385 cm2/Vs compared to the reference device on SOI which has a mobility of 188 cm2/Vs. P-MOSFETs fabricated on sSi/Si 0.5 Ge 0.5 /sSOI heterostructure with a gate first process showed a subthreshold swing of 92 mV/dec and an I on /I off ratio of 105. The extracted hole mobilities are similar to the reference device with HfO 2 as gate dielectric, and are much higher than the hole mobilities in Si.

The implementation of more powerful materials into leading edge CMOS devices allows performance improvements without scaling and without changing the circuit design libraries. This highly motivates the research on novel materials. In this paper we present various transistor fabrication processes like “gate first” and “replacement gate” for different channel stack configurations like strained Si, strained SiGe alloy layers and Ge channels with HfO2 and novel high-k dielectrics and metal gates. We discuss HfO2 as a reference material and various ternary rare earth oxides with k ≈ 30 desired for the next technology nodes in order to ensure optimum gate control and minimum short channel effects.